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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581c05sm84014866b.7.2024.06.06.04.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 04:36:04 -0700 (PDT) From: Konrad Dybcio Date: Thu, 06 Jun 2024 13:36:00 +0200 Subject: [PATCH v4 1/5] dt-bindings: clock: Add Qcom QCM2290 GPUCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org> References: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> In-Reply-To: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717673761; l=3930; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=sI0N+gXKPVP3QbPJPNuP8btkVLaRyBbKcbcqKnzx9k4=; b=+bolgQM0KQdj5ZJhddh9aE5/mCjBndTCLL1xVp7WhUrpIENDI929+TM02w5EBYb2f6o3qLwAu czIQuy40yC8D0H9txRfDhjnLc9mmZIw9o+lq74/MR56FHX6Nm/arbHg X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,qcm2290-gpucc.yaml | 77 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,qcm2290-gpucc.h | 32 +++++++++ 2 files changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yam= l b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml new file mode 100644 index 000000000000..734880805c1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCM2290 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and p= ower + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,qcm2290-gpucc.h + +properties: + compatible: + const: qcom,qcm2290-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required CX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@5990000 { + compatible =3D "qcom,qcm2290-gpucc"; + reg =3D <0x0 0x05990000 0x0 0x9000>; + clocks =3D <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains =3D <&rpmpd QCM2290_VDDCX>; + required-opps =3D <&rpmpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcm2290-gpucc.h b/include/dt-bi= ndings/clock/qcom,qcm2290-gpucc.h new file mode 100644 index 000000000000..7c76dd05278f --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_GFX3D_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GFX3D_CLK 8 +#define GPU_CC_GX_GFX3D_CLK_SRC 9 +#define GPU_CC_PLL0 10 +#define GPU_CC_SLEEP_CLK 11 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif --=20 2.45.2 From nobody Sat Feb 7 18:21:15 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 373F71957F5 for ; Thu, 6 Jun 2024 11:36:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717673771; cv=none; b=rroHc9U5O7wn7AqhxUaSgs9PLoI/s/OTqwditQjXieXlXJchxAS+52n/pw0ocu4aQqn61j24MaMRmrUoCXLTmIYN+Zfw9Qvjq8h2D4xWQOnEBol6RyHzza2T9QKoC0nLX+oRzsyXfy1qF9NZwL2qbKXgvqsWnyfrjvco9DX7YKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717673771; c=relaxed/simple; bh=/qpiheDuHQp2YaBAQ+Lb7FOLLyXtkg2hWH6UlH5R5zA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hEtLXQSCxSzH5SVfSGGb14UFFrpnVCUw0XEkJj6Kfwd05Lg5gQorc9Ho/gW/2CSurN4pXx7dRSvN6oT0ov5veSPfyCFQw8nXN5i7lBK40YM9Ev5ebs0uW4EBffxAyqkmZOdoVvjP/eUrYxzG2Lz8AR2ZQeaVVJfT2QbDka7Z2Eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dGd402fG; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dGd402fG" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-a6c8537bfa0so62736566b.3 for ; Thu, 06 Jun 2024 04:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717673766; x=1718278566; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BSnM/oZJbndKg9aMrgpLItXBoYBY1c6r3d9VAFK5xDQ=; b=dGd402fG9529ddAHpzxZW1wT0TkOU4jApJPXSILD81AVCaHzuAh86FqbZmSrfDiCd2 ge2DXOqKUxtlUPCX7Geo3Y29lIHOkOeivaMMp4OnOv6w+CLQ+3+ijVUOzMGvXvxA+T1c Dv9aNuY0MghBfO8EkZzljpiCk4QI2yMUDOGE7Mc7YTGHaRlSFkoUKdUBEBZuZPja0+d/ XqMOt6Xn8OxbN+OzHZ1Si5vK+6ntVQoloYcE7c4t8yRzVbXhkiVpk3Kki0PbIU/yPMP/ C5/ykOysucGi2bdhn6k2uOeRZ/7WfDwCA/X+kSs0eWbW7FMuOeH6HeISQ+KpCbmn33Ob xHAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717673766; x=1718278566; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BSnM/oZJbndKg9aMrgpLItXBoYBY1c6r3d9VAFK5xDQ=; b=p87d+K5nkaEmVSRs5JlasUlOLI5mkjUCvYSlDWRAKkGledz+TqR8nsZkmPyJxismoj to1y2toMJHkSCPxKAXoOkxIc83ySKQP2RKFYzIFM1A4ch5QRxY0skwQa8OKFiD6VMjn6 M7ne7sPDILA9qVaxM9u52dm0Bsk3+v7eJk0EvI/v7BsTP7yTO7h8OlxLC5CDHQuMd9eE hXqtkmD5TbCfXfes9dcGSDMgByEcBUczR5v3Xxf4xhS6NuMroCZocrhOiW+SBF/iIT6j 5VVzMouJ4BkGc1dNuQKiDEEqMVjMw9eopEEhzNQSMIbvNs/JVDslvmUqNsXDVXIK66k0 WC3w== X-Forwarded-Encrypted: i=1; AJvYcCVNUE2HuZASBR1GIiokpcgLszpT6eEjtW/sbgqq4eIeKQ+B2pFuJN2r0pb4n99zNqhV1OiD8JScgFQUbxNcXbttvLDWG77T3+p1IFVx X-Gm-Message-State: AOJu0YzbVTpecrf3JkMQ+//qwNhh9TTgd2ygkNq6dgXn24XTgWORiYuy g5pKYYBK0LGG97QbBW4I2FzxSJgSdwjTdscbzISQF00WZpC0839Pl3uTvErrcCk= X-Google-Smtp-Source: AGHT+IG8xikVZuweD3rhNVWlCVJ0Nl34MwZeFWaeQYyU9TiFrovwu5MglGA/y+cB5ZgrM1MbLvcKsw== X-Received: by 2002:a17:906:380c:b0:a68:fe1f:c0bd with SMTP id a640c23a62f3a-a69a023b4f4mr357937966b.73.1717673766605; Thu, 06 Jun 2024 04:36:06 -0700 (PDT) Received: from [192.168.128.139] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581c05sm84014866b.7.2024.06.06.04.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 04:36:06 -0700 (PDT) From: Konrad Dybcio Date: Thu, 06 Jun 2024 13:36:01 +0200 Subject: [PATCH v4 2/5] clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240606-topic-rb1_gpu-v4-2-4bc0c19da4af@linaro.org> References: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> In-Reply-To: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717673761; l=4384; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=/qpiheDuHQp2YaBAQ+Lb7FOLLyXtkg2hWH6UlH5R5zA=; b=I0Tu0zm0GJQ9wAY6hCkC5pb2eBz91xkdqluHUc+9wNOwFixJwEc8l50+kUXa/uitOpK4aETxU xJOOGym9oh9DGAtxY8Evnemf/Z5igWrl4ZNQjAzVKJgAg1R6sv0iykg X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-alpha-pll.c | 47 ++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 50 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index c51647e37df8..d87314042528 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -93,6 +93,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [PLL_OFF_TEST_CTL] =3D 0x30, [PLL_OFF_TEST_CTL_U] =3D 0x34, }, + [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] =3D { + [PLL_OFF_L_VAL] =3D 0x04, + [PLL_OFF_ALPHA_VAL] =3D 0x08, + [PLL_OFF_USER_CTL] =3D 0x0c, + [PLL_OFF_CONFIG_CTL] =3D 0x10, + [PLL_OFF_CONFIG_CTL_U] =3D 0x14, + [PLL_OFF_CONFIG_CTL_U1] =3D 0x18, + [PLL_OFF_TEST_CTL] =3D 0x1c, + [PLL_OFF_TEST_CTL_U] =3D 0x20, + [PLL_OFF_TEST_CTL_U1] =3D 0x24, + [PLL_OFF_OPMODE] =3D 0x28, + [PLL_OFF_STATUS] =3D 0x38, + }, [CLK_ALPHA_PLL_TYPE_BRAMMO] =3D { [PLL_OFF_L_VAL] =3D 0x04, [PLL_OFF_ALPHA_VAL] =3D 0x08, @@ -788,6 +801,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw= , unsigned long rate, return clamp(rate, min_freq, max_freq); } =20 +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regma= p *regmap, + const struct alpha_pll_config *config) +{ + u32 val; + + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ct= l_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_= ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config= _ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_va= l); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_= hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl= _hi1_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_va= l); + + /* Set PLL_BYPASSNL */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); + regmap_read(regmap, PLL_MODE(pll), &val); + + /* Wait 5 us between setting BYPASS and deasserting reset */ + udelay(5); + + /* Take PLL out from reset state */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + regmap_read(regmap, PLL_MODE(pll), &val); + + /* Wait 50us for PLL_LOCK_DET bit to go high */ + usleep_range(50, 55); + + /* Enable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); +} +EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); + static unsigned long alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index c7055b6c42f1..df8f0fe15531 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -16,6 +16,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT, CLK_ALPHA_PLL_TYPE_HUAYRA, CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, + CLK_ALPHA_PLL_TYPE_HUAYRA_2290, CLK_ALPHA_PLL_TYPE_BRAMMO, CLK_ALPHA_PLL_TYPE_FABIA, CLK_ALPHA_PLL_TYPE_TRION, @@ -194,6 +195,8 @@ extern const struct clk_ops clk_alpha_pll_rivian_evo_op= s; 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581c05sm84014866b.7.2024.06.06.04.36.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 04:36:08 -0700 (PDT) From: Konrad Dybcio Date: Thu, 06 Jun 2024 13:36:02 +0200 Subject: [PATCH v4 3/5] clk: qcom: Add QCM2290 GPU clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240606-topic-rb1_gpu-v4-3-4bc0c19da4af@linaro.org> References: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> In-Reply-To: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717673761; l=13178; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1PFi2jCo9ddV1uxQE7AhFuFIzWVGpFmWLCJB347r9hc=; b=MqCgjShDf/h3lyGxmLzJ4c6u86VcvYGPkYvqFvNFmpv+4iUYMGd01s7JlWF4F2s6YftqWE46s gG1z3g3DWbFCJsDLgduFd8KTm9O1qrjV+1t/ex8mFRk0IC3FygDcCtR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add a driver for the GPU clock controller block found on the QCM2290 SoC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-qcm2290.c | 423 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 433 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 20ba2eeb24ec..2ec8ee1d2230 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -65,6 +65,15 @@ config CLK_X1E80100_TCSRCC Support for the TCSR clock controller on X1E80100 devices. Say Y if you want to use peripheral devices such as SD/UFS. =20 +config CLK_QCM2290_GPUCC + tristate "QCM2290 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_QCM2290_GCC + help + Support for the graphics clock controller on QCM2290 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config QCOM_A53PLL tristate "MSM8916 A53 PLL" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b7de8600dc3d..fbed205e2091 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GPUCC) +=3D gpucc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_TCSRCC) +=3D tcsrcc-x1e80100.o +obj-$(CONFIG_CLK_QCM2290_GPUCC) +=3D gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) +=3D apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2= 290.c new file mode 100644 index 000000000000..b6e20d63ac85 --- /dev/null +++ b/drivers/clk/qcom/gpucc-qcm2290.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_GCC_AHB_CLK, + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_AUX, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco huayra_vco[] =3D { + { 600000000, 3300000000, 0 }, + { 600000000, 2200000000, 1 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x25, + .config_ctl_val =3D 0x200d4828, + .config_ctl_hi_val =3D 0x6, + .test_ctl_val =3D GENMASK(28, 26), + .test_ctl_hi_val =3D BIT(14), + .user_ctl_val =3D 0xf, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D huayra_vco, + .num_vco =3D ARRAY_SIZE(huayra_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO, }, + { .hw =3D &gpu_cc_pll0.clkr.hw, }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC, }, + { .index =3D DT_GCC_GPU_GPLL0_DIV_CLK_SRC, }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL0_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO, }, + { .hw =3D &gpu_cc_pll0.clkr.hw, }, + { .hw =3D &gpu_cc_pll0.clkr.hw, }, + { .hw =3D &gpu_cc_pll0.clkr.hw, }, + { .index =3D DT_GCC_GPU_GPLL0_CLK_SRC, }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x1120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] =3D { + F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src =3D { + .cmd_rcgr =3D 0x101c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_gfx3d_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x1078, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1078, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_ahb_clk", + .flags =3D CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x107c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x107c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_crc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk =3D { + .halt_reg =3D 0x10a4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_gfx3d_clk", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x1098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1098, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_gmu_clk", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk =3D { + .halt_reg =3D 0x108c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cx_snoc_dvm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk =3D { + .halt_reg =3D 0x1004, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_aon_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x109c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x109c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk =3D { + .halt_reg =3D 0x1054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1054, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_gx_gfx3d_clk", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x1090, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x1090, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x5000, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x5000, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc =3D { + .gdscr =3D 0x106c, + .gds_hw_ctrl =3D 0x1540, + .pd =3D { + .name =3D "gpu_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc =3D { + .gdscr =3D 0x100c, + .clamp_io_ctrl =3D 0x1508, + .resets =3D (unsigned int []){ GPU_GX_BCR }, + .reset_count =3D 1, + .pd =3D { + .name =3D "gpu_gx_gdsc", + }, + .parent =3D &gpu_cx_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO | AON_RESET | SW_RESET, +}; + +static struct clk_regmap *gpu_cc_qcm2290_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] =3D &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GFX3D_CLK] =3D &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] =3D &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_qcm2290_resets[] =3D { + [GPU_GX_BCR] =3D { 0x1008 }, +}; + +static struct gdsc *gpu_cc_qcm2290_gdscs[] =3D { + [GPU_CX_GDSC] =3D &gpu_cx_gdsc, + [GPU_GX_GDSC] =3D &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_qcm2290_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9000, + .fast_io =3D true, +}; + + +static const struct qcom_cc_desc gpu_cc_qcm2290_desc =3D { + .config =3D &gpu_cc_qcm2290_regmap_config, + .clks =3D gpu_cc_qcm2290_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_qcm2290_clocks), + .resets =3D gpu_cc_qcm2290_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_qcm2290_resets), + .gdscs =3D gpu_cc_qcm2290_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_qcm2290_gdscs), +}; + +static const struct of_device_id gpu_cc_qcm2290_match_table[] =3D { + { .compatible =3D "qcom,qcm2290-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table); + +static int gpu_cc_qcm2290_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gpu_cc_qcm2290_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D devm_pm_clk_create(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_clk_add(&pdev->dev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire ahb clock\n"); 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581c05sm84014866b.7.2024.06.06.04.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 04:36:09 -0700 (PDT) From: Konrad Dybcio Date: Thu, 06 Jun 2024 13:36:03 +0200 Subject: [PATCH v4 4/5] arm64: dts: qcom: qcm2290: Add GPU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240606-topic-rb1_gpu-v4-4-4bc0c19da4af@linaro.org> References: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> In-Reply-To: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717673761; l=5480; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=oEkR0OJ7HbU+SvpCsJqIooT/mtFwOiyIxsWq7bfXgKs=; b=Dwt92DIyZ+6++wATwwrQLT9y8Jtb0EcswLGK71pRAvbovJuiXi+ACqvOGzli4GzR0Si9gIexN lpGxe+0K2EHAM5OKTBTRF82Vt2wCzcqeEHKeqiC8ilvAMz2d5rz8bFt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Describe the GPU hardware on the QCM2290. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 154 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qc= om/qcm2290.dtsi index 106110a9f551..99d98afb1b2c 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include #include @@ -758,6 +759,11 @@ qusb2_hstx_trim: hstx-trim@25b { reg =3D <0x25b 0x1>; bits =3D <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg =3D <0x2006 0x2>; + bits =3D <5 8>; + }; }; =20 pmu@1b8e300 { @@ -1425,6 +1431,154 @@ usb_dwc3_ss: endpoint { }; }; =20 + gpu: gpu@5900000 { + compatible =3D "qcom,adreno-07000200", "qcom,adreno"; + reg =3D <0x0 0x05900000 0x0 0x40000>; + reg-names =3D "kgsl_3d0_reg_memory"; + + interrupts =3D ; + + clocks =3D <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names =3D "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interconnects =3D <&bimc MASTER_GFX3D RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names =3D "gfx-mem"; + + iommus =3D <&adreno_smmu 0 1>, + <&adreno_smmu 2 0>; + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&rpmpd QCM2290_VDDCX>; + qcom,gmu =3D <&gmu_wrapper>; + + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + #cooling-cells =3D <2>; + + status =3D "disabled"; + + zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ + opp-1123200000 { + opp-hz =3D /bits/ 64 <1123200000>; + required-opps =3D <&rpmpd_opp_turbo_plus>; + opp-peak-kBps =3D <6881000>; + opp-supported-hw =3D <0x3>; + turbo-mode; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + required-opps =3D <&rpmpd_opp_turbo>; + opp-peak-kBps =3D <6881000>; + opp-supported-hw =3D <0x3>; + turbo-mode; + }; + + opp-921600000 { + opp-hz =3D /bits/ 64 <921600000>; + required-opps =3D <&rpmpd_opp_nom_plus>; + opp-peak-kBps =3D <6881000>; + opp-supported-hw =3D <0x3>; + }; + + opp-844800000 { + opp-hz =3D /bits/ 64 <844800000>; + required-opps =3D <&rpmpd_opp_nom>; + opp-peak-kBps =3D <6881000>; + opp-supported-hw =3D <0x7>; + }; + + opp-672000000 { + opp-hz =3D /bits/ 64 <672000000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + opp-peak-kBps =3D <3879000>; + opp-supported-hw =3D <0xf>; + }; + + opp-537600000 { + opp-hz =3D /bits/ 64 <537600000>; + required-opps =3D <&rpmpd_opp_svs>; + opp-peak-kBps =3D <2929000>; + opp-supported-hw =3D <0xf>; + }; + + opp-355200000 { + opp-hz =3D /bits/ 64 <355200000>; + required-opps =3D <&rpmpd_opp_low_svs>; + opp-peak-kBps =3D <1720000>; + opp-supported-hw =3D <0xf>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible =3D "qcom,adreno-gmu-wrapper"; + reg =3D <0x0 0x0596a000 0x0 0x30000>; + reg-names =3D "gmu"; + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + }; + + gpucc: clock-controller@5990000 { + compatible =3D "qcom,qcm2290-gpucc"; + reg =3D <0x0 0x05990000 0x0 0x9000>; + clocks =3D <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains =3D <&rpmpd QCM2290_VDDCX>; + required-opps =3D <&rpmpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@59a0000 { + compatible =3D "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x059a0000 0x0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + ; + + clocks =3D <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names =3D "mem", + "hlos", + "iface"; + + power-domains =3D <&gpucc GPU_CX_GDSC>; + + #global-interrupts =3D <1>; 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581c05sm84014866b.7.2024.06.06.04.36.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 04:36:11 -0700 (PDT) From: Konrad Dybcio Date: Thu, 06 Jun 2024 13:36:04 +0200 Subject: [PATCH v4 5/5] arm64: dts: qcom: qrb2210-rb1: Enable the GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240606-topic-rb1_gpu-v4-5-4bc0c19da4af@linaro.org> References: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> In-Reply-To: <20240606-topic-rb1_gpu-v4-0-4bc0c19da4af@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717673761; l=915; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=836LbL/aePNRW0HFxVtuyVyeX07tYHWWbwxRLU++CbI=; b=RhzJDw+hairhy/yq1ZYOGYxYGjnX3/H9iekx82yl6hPvCrHqS/Gxcf4zNcgNp9N3xWgsgmiJE dL7v0+LGON9B1BrpmG8XZ7zq+LKLEt3nEjUUrbve0vtCRmpo6KkiXei X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Enable the A702 GPU (also marketed as "3D accelerator by qcom [1], lol). [1] https://docs.qualcomm.com/bundle/publicresource/87-61720-1_REV_A_QUALCO= MM_ROBOTICS_RB1_PLATFORM__QUALCOMM_QRB2210__PRODUCT_BRIEF.pdf Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts= /qcom/qrb2210-rb1.dts index bb5191422660..acecef743941 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -199,6 +199,14 @@ &gpi_dma0 { status =3D "okay"; }; =20 +&gpu { + status =3D "okay"; + + zap-shader { + firmware-name =3D "qcom/qcm2290/a702_zap.mbn"; + }; +}; + &i2c2 { clock-frequency =3D <400000>; status =3D "okay"; --=20 2.45.2