From nobody Thu Feb 12 23:19:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9330517BCD; Wed, 5 Jun 2024 15:36:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717601770; cv=none; b=PX4zWGoXIfDWqAkg8CHbu31lFZyic08d2oZC85tEQwImIaje2BM2owaWm5KzBza5wnqzW9u9x0i5xMaV86C1HxfkaHi/maWSTmfaWW8Zjg6jl8RXRr8fcvccUJZjeuplwzluv3aKY/ysHb1sQnWkpNtLPfdNLrGQqzjXRvxHpJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717601770; c=relaxed/simple; bh=gXaKI7GTzt1NrqrHwZPF0PvslVGiw4h9Hgff3rrnspM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Vahx8gBajDp/YFVh1NbnJbXqKtKHt4zEwZiUnn0AUU0hS6gXV5R98OEspFORZ6Qwc4PV4lOD3D5pGKPB5H6dRJZayZuSN+fLcnnQNJiGOo44R3B/e9T+Or5isZ68ZG8eVqh54f1R35CwhJtRwuchPP4FFB1zai2GNyRAmb8V5TU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=f2E+otj1; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="f2E+otj1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717601768; x=1749137768; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gXaKI7GTzt1NrqrHwZPF0PvslVGiw4h9Hgff3rrnspM=; b=f2E+otj1NFtoiDSAsnZ4vt4aI73t+67ZKSITdPJ9kz2iLe8waqmZ0EMU i3K8h8jx9xIpXfDSgqphXDW417p8NVZFOBKqj66rtJ1sO6ZdNAkhH1wHN W5OFdtkh8YOicGRiD5htEAjYcl0wMl3Zz8bwz1oXAGsNef8InOBl3qsyI IocOWe5Iuqi7oQ6N9OIG8DsnWCKF6pbdTxlpHsNEWUm011di+emomJ1gD NMYGcCRYROlal+Vr6XRUzv+QcUOyU2fc8ombVC06geun8wB93n+T1RK7L 4rMsj9vQ/0fVfB79ky3gut6bcLYKEuf3CODI2aUNfA3Lxwx7GSB1MHXef Q==; X-CSE-ConnectionGUID: soRZkM+oSMqvz+9sDfe8/Q== X-CSE-MsgGUID: WiQ24RrTRYeqrILkKomy1w== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14106010" X-IronPort-AV: E=Sophos;i="6.08,217,1712646000"; d="scan'208";a="14106010" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2024 08:36:08 -0700 X-CSE-ConnectionGUID: RQEn2ajOTU6ADnK2pWlGAA== X-CSE-MsgGUID: ZAtagq6+QhygoIbj1V72+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,217,1712646000"; d="scan'208";a="37765280" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa009.fm.intel.com with ESMTP; 05 Jun 2024 08:35:59 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v9 1/3] pps: generators: Add PPS Generator TIO Driver Date: Wed, 5 Jun 2024 21:05:52 +0530 Message-Id: <20240605153554.11584-2-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240605153554.11584-1-lakshmi.sowjanya.d@intel.com> References: <20240605153554.11584-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lakshmi Sowjanya D The Intel Timed IO PPS generator driver outputs a PPS signal using dedicated hardware that is more accurate than software actuated PPS. The Timed IO hardware generates output events using the ART timer. The ART timer period varies based on platform type, but is less than 100 nanoseconds for all current platforms. Timed IO output accuracy is within 1 ART period. PPS output is enabled by writing '1' the 'enable' sysfs attribute. The driver uses hrtimers to schedule a wake-up 10 ms before each event (edge) target time. At wakeup, the driver converts the target time in terms of CLOCK_REALTIME to ART trigger time and writes this to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 268 +++++++++++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index d615e640fcad..0f090932336f 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -12,3 +12,19 @@ config PPS_GENERATOR_PARPORT If you say yes here you get support for a PPS signal generator which utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. + +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makef= ile index 2589fd0f2481..714e847ae193 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -4,5 +4,6 @@ # =20 obj-$(CONFIG_PPS_GENERATOR_PARPORT) +=3D pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) +=3D pps_gen_tio.o =20 ccflags-$(CONFIG_PPS_DEBUG) :=3D -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/= pps_gen_tio.c new file mode 100644 index 000000000000..267233b3c99c --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) /* Safety time to set hrtimer = early */ +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct hrtimer timer; + struct device *dev; + spinlock_t lock; + struct attribute_group attrs; + void __iomem *base; + bool enabled; + u32 prev_count; +}; + +static inline u32 pps_tio_read(struct pps_tio *tio, u32 offset) +{ + return readl(tio->base + offset); +} + +static inline void pps_ctl_write(struct pps_tio *tio, u32 value) +{ + writel(value, tio->base + TIOCTL); +} + +/* For COMPV register, It's safer to write higher 32-bit followed by lower= 32-bit */ +static inline void pps_compv_write(struct pps_tio *tio, u64 value) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + return ktime_set(ktime_get_real_seconds() + 1, MAGIC_CONST); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_read(tio, TIOCTL); + pps_compv_write(tio, 0); + + ctrl &=3D ~TIOCTL_EN; + pps_ctl_write(tio, ctrl); + tio->enabled =3D false; + tio->prev_count =3D 0; + + return ctrl; +} + +static void pps_tio_enable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_read(tio, TIOCTL); + ctrl |=3D TIOCTL_EN; + pps_ctl_write(tio, ctrl); + tio->enabled =3D true; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_disable(tio); + + /* We enable the device, be sure that the 'compare' value is invalid */ + pps_compv_write(tio, 0); + + ctrl &=3D ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |=3D TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(tio, ctrl); + pps_tio_enable(tio); +} + +static bool pps_generate_next_pulse(struct pps_tio *tio, ktime_t expires) +{ + u64 art; + + if (!ktime_real_to_base_clock(expires, CSID_X86_ART, &art)) { + pps_tio_disable(tio); + return false; + } + + pps_compv_write(tio, art - ART_HW_DELAY_CYCLES); + return true; +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct pps_tio *tio =3D container_of(timer, struct pps_tio, timer); + ktime_t expires, now; + u32 event_count; + + guard(spinlock)(&tio->lock); + + /* Check if any event is missed. If an event is missed, TIO will be disab= led*/ + event_count =3D pps_tio_read(tio, TIOEC); + if (tio->prev_count && tio->prev_count =3D=3D event_count) + goto err; + tio->prev_count =3D event_count; + expires =3D hrtimer_get_expires(timer); + now =3D ktime_get_real(); + + if (now - expires >=3D SAFE_TIME_NS) + goto err; + + tio->enabled =3D pps_generate_next_pulse(tio, expires + SAFE_TIME_NS); + if (!tio->enabled) + return HRTIMER_NORESTART; + + hrtimer_forward(timer, now, NSEC_PER_SEC / 2); + return HRTIMER_RESTART; +err: + dev_err(tio->dev, "Event missed, Disabling Timed I/O"); + pps_tio_disable(tio); + return HRTIMER_NORESTART; +} + +static ssize_t enable_store(struct device *dev, struct device_attribute *a= ttr, const char *buf, + size_t count) +{ + struct pps_tio *tio =3D dev_get_drvdata(dev); + bool enable; + int err; + + if (!timekeeping_clocksource_has_base(CSID_X86_ART)) { + dev_err(dev, "PPS cannot be used as clock is not related to ART"); + return -EPERM; + } + + err =3D kstrtobool(buf, &enable); + if (err) + return err; + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !tio->enabled) { + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + } else if (!enable && tio->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + } + return count; +} + +static ssize_t enable_show(struct device *dev, struct device_attribute *de= vattr, char *buf) +{ + struct pps_tio *tio =3D dev_get_drvdata(dev); + u32 ctrl; + + ctrl =3D pps_tio_read(tio, TIOCTL); + ctrl &=3D TIOCTL_EN; + + return sysfs_emit(buf, "%u\n", ctrl); +} +static DEVICE_ATTR_RW(enable); + +static struct attribute *pps_tio_attrs[] =3D { + &dev_attr_enable.attr, + NULL +}; +ATTRIBUTE_GROUPS(pps_tio); + +static int pps_tio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio =3D devm_kzalloc(dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->dev =3D dev; + tio->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function =3D hrtimer_callback; + spin_lock_init(&tio->lock); + platform_set_drvdata(pdev, tio); + + return 0; +} + +static int pps_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio =3D platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + + return 0; +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] =3D { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_tio_driver =3D { + .probe =3D pps_tio_probe, + .remove =3D pps_tio_remove, + .driver =3D { + .name =3D "intel-pps-generator", + .acpi_match_table =3D intel_pmc_tio_acpi_match, + .dev_groups =3D pps_tio_groups, + }, +}; +module_platform_driver(pps_tio_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); --=20 2.35.3 From nobody Thu Feb 12 23:19:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1572F6A347; Wed, 5 Jun 2024 15:36:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717601772; cv=none; b=kPSdGozJJlt0jZ5TZx7VhA7oQafZyRoxdgUwSM8v6V+T0FrOoH0a8qzEMpI+y9BF9fh5B7unoHkttP1GSkfTi1q0QJPVXgbGxxmpbdGTCVtv0AIKcRGc8OprxyJuds3BLGohiEOO2FjuXoIfIG5kVFoWeDV1/xuNeomHc7Qd7Ng= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="37765307" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa009.fm.intel.com with ESMTP; 05 Jun 2024 08:36:05 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v9 2/3] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Wed, 5 Jun 2024 21:05:53 +0530 Message-Id: <20240605153554.11584-3-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240605153554.11584-1-lakshmi.sowjanya.d@intel.com> References: <20240605153554.11584-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lakshmi Sowjanya D Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti --- Documentation/driver-api/pps.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pp= s.rst index 78dded03e5d8..c812d1cb760e 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -246,3 +246,25 @@ delay between assert and clear edge as small as possib= le to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signals. + +Timed I/O and system time are both driven by same hardware clock. The sign= al +is generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +it can be used to share your clock with a device that receives PPS signal, +generated by Timed I/O device. There are dedicated Timed I/O pins to deliv= er +the PPS signal to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable --=20 2.35.3 From nobody Thu Feb 12 23:19:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7FDE15666F; Wed, 5 Jun 2024 15:36:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717601776; cv=none; b=qahmhl2qZcoTyiaCYQqCk/4W7ST09oS3WsY2/R+ugt5oZ/WH4G6eRW7mVLZQ0Cvgv7Vhv3b64GoSVq9tufCruwYe6O++34hCw7BnUXiyIOmwd6+BMU6ENdeMIvFz2EhkeOLyp87sGeXErlpmY7UGtuVIHWSDVov3acNM+kN113M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717601776; c=relaxed/simple; bh=9z/rDhWsENdERmVUQdtCDhLPPh2i3nZGdWjTuzNIFbw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ierqjG7Z/f4PbZeVHkAMtYgVR6Ioqxc0yELQI4mPlQo6HruJn2MfC8yDRW+QPgT2cvqYczpX3prjRdZRrfgxXBJYWj4Y3SJWyMjn+cIPdL/hSij+JMkKXQGeeKyaCGn7SGUtT1IwOlTvZirnsHeZzQa8W4wrQaHG7iwSjRH7TuE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WYi1rR0I; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WYi1rR0I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717601775; x=1749137775; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9z/rDhWsENdERmVUQdtCDhLPPh2i3nZGdWjTuzNIFbw=; b=WYi1rR0IHw4kXXmNFeznNK+xWftvkmFXHqH6MKxtcTPGqHHpgrFySKR1 MCI+1JrHDBVDZnZjpheLnmrotLEjTkEonnUeQ7Pq+uFTyIPZit+RHWMzD 93KtQj0ol1VS7iVsuDz0tcK5c0UcQKJhrSPl98Xei3iZnewMsP3RVev1C bfl92QfoTxDTSdjmaOvlaaG7OZoIXBZpreJ6SspSARF3m/p0dPnvn1HjR f7r+LHymdPhSEqN2Gx2nYJLKhym5uOib8SDm76VTB4l28Q1T6ZYVIE2SC 98ACTNNP1ybKnu59Wl2YkWYLm2HPmfFK76yRfSlxAbKWfFPd6QIMrz/T7 A==; X-CSE-ConnectionGUID: jcjPwT12Rqy0RsAKvLyk0g== X-CSE-MsgGUID: sEDFIe6VR6yuUNazNn5gpw== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14106039" X-IronPort-AV: E=Sophos;i="6.08,217,1712646000"; d="scan'208";a="14106039" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2024 08:36:14 -0700 X-CSE-ConnectionGUID: GdnqcmzyRq+IQidqyjDRLA== X-CSE-MsgGUID: tyhGzpZVQ8mpTh+vh87VJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,217,1712646000"; d="scan'208";a="37765326" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa009.fm.intel.com with ESMTP; 05 Jun 2024 08:36:10 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v9 3/3] ABI: pps: Add ABI documentation for Intel TIO Date: Wed, 5 Jun 2024 21:05:54 +0530 Message-Id: <20240605153554.11584-4-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240605153554.11584-1-lakshmi.sowjanya.d@intel.com> References: <20240605153554.11584-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lakshmi Sowjanya D Document sysfs interface for Intel Timed I/O PPS driver. Signed-off-by: Lakshmi Sowjanya D --- Documentation/ABI/testing/sysfs-platform-pps-tio | 7 +++++++ MAINTAINERS | 1 + 2 files changed, 8 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio diff --git a/Documentation/ABI/testing/sysfs-platform-pps-tio b/Documentati= on/ABI/testing/sysfs-platform-pps-tio new file mode 100644 index 000000000000..e461cea12d60 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pps-tio @@ -0,0 +1,7 @@ +What: /sys/devices/platform/INTCxxxx/enable +Date: September 2024 +KernelVersion: 6.11 +Contact: Lakshmi Sowjanya D +Description: + (RW) Enable or disable PPS TIO generator output, read to + see the status of hardware (Enabled/Disabled). diff --git a/MAINTAINERS b/MAINTAINERS index 8754ac2c259d..5c8a443233ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17948,6 +17948,7 @@ M: Rodolfo Giometti L: linuxpps@ml.enneenne.com (subscribers-only) S: Maintained W: http://wiki.enneenne.com/index.php/LinuxPPS_support +F: Documentation/ABI/testing/sysfs-platform-pps-tio F: Documentation/ABI/testing/sysfs-pps F: Documentation/devicetree/bindings/pps/pps-gpio.yaml F: Documentation/driver-api/pps.rst --=20 2.35.3