From nobody Thu Feb 12 23:04:08 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DF1E188CA4; Wed, 5 Jun 2024 12:49:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717591750; cv=none; b=qpa/bjyrE7GHhkit/rJRKkmNTIgq5fhsge/SHZrPrVPLF2B+g3906WVnW3S4z0RpolW38Roz7cGqKddf6uEDrwTwXaN+DcH4U99TL/w9G1e70hz0vrijBHtN3jQgMBUGdOwO2zGTOoXCJym0D2vEz+UmCSWseTCZuBndvB3Oy4g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717591750; c=relaxed/simple; bh=I6p66dNXgWuYF0sjf76h4FVqcCSW0xhy5njB8QURPwg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FKI2NazpnsBv672vgybqFD8vepkdWpfD2rA3+KVsGOEArayfr7r99GQdb8w+GDnJSNSw4xTwDzAOBP/cSRuFxY8QLMROkSbakLhcGfK+DanVkPT26XDyIKFsSnGpWLAqb/eur0yhErgXwzUUUp42QfXgrbbf/YkXJLO1EO/By1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=MVdWRqOf; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MVdWRqOf" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 455Cn0pb006029; Wed, 5 Jun 2024 07:49:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717591740; bh=WbdIYS/knOJHqyX7310+VXzxm1AWii1EXvlI4FnfTaU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MVdWRqOfZxXrJK9LsZ7fbKBiKLpAOyk4f1tNXmveXZOeQQv0D5FlCy7oPSvTHgUwS Q0onLgR0ZxoVE3DneGTqvTNMOutd2p/pjUNIhMz6zoAexfExNll3JOoBGaZyWYZfpC xg6Pe64+CiYp5rZ+cksjQk3tl4wOqJV1yYqVlmeg= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 455Cn0Qs006777 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Jun 2024 07:49:00 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Jun 2024 07:49:00 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Jun 2024 07:49:00 -0500 Received: from localhost ([10.249.48.175]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 455Cn0kJ108867; Wed, 5 Jun 2024 07:49:00 -0500 From: Hari Nagalla To: , , , , , CC: , , Subject: [PATCH v3 1/4] arm64: dts: k3-am62a-main: Add C7xv device node Date: Wed, 5 Jun 2024 07:48:56 -0500 Message-ID: <20240605124859.3034-2-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605124859.3034-1-hnagalla@ti.com> References: <20240605124859.3034-1-hnagalla@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jai Luthra AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index bf9c2d9c6439..0912cc31329c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1062,4 +1062,15 @@ vpu: video-codec@30210000 { clocks =3D <&k3_clks 204 2>; power-domains =3D <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + + c7x_0: dsp@7e000000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e000000 0x00 0x00100000>; + reg-names =3D "l2sram"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <208>; + ti,sci-proc-ids =3D <0x04 0xff>; + resets =3D <&k3_reset 208 1>; + firmware-name =3D "am62a-c71_0-fw"; + }; }; --=20 2.34.1 From nobody Thu Feb 12 23:04:08 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 643C9195FC9; Wed, 5 Jun 2024 12:49:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717591749; cv=none; b=MZ/dMabxl4qN2z2hAHpdSa2yRocMGa0gzfBmDU81sSndreJBmhognqln/Ro/53dR99YkVZpUax3dNFHf3iQMYAhbTYUokT+/dVz9p1V+JyK33QZr1ISctfJ2YdANQBMAxEZthoanXadTu+QXf3U0/ejabeBGc9IPcYMven620CI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717591749; c=relaxed/simple; bh=5RVPzMy/QPSlQXb8jYE2+R+rK4CFR75JBYXWa2TedWc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W4S4bLxK+O51UxsQ2D0AJVW3SBDNDeoNzzmYglYe9E6stIRLgTW6Hq5sXDVeB3GqOdtyaCsWhTDVqM0Xq1Q7nEuHFFBZDUWDwcBoKPRaCFBKkAWsZ01JNttDPVcHvnehkTcctuAVRcJ090zaYgruRDerFFvJgm0HQ1PFWY3OqxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=YLZhOLJ2; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YLZhOLJ2" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 455Cn03a118483; Wed, 5 Jun 2024 07:49:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717591740; bh=lRj86cxU3Xj9ynRAeceeFgH8EJzU6nWYxAQZqFM/a68=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YLZhOLJ2K8bFPoqlSuE84Fdjg0XCBg/zFi/lzjFTcc4pqwMXHVLz5px/Cj5Yd65wF 6r1DPgm4P7nv4lPdpq8P2WsSaDZbht+sBknX3sbUn9C2v3IIs/jPGjoAe4tq7ac/Po ej9dTk0WcwgX2blGHqxVW90CYlWMHb7ck8F1Z0rM= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 455Cn0Z5006783 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Jun 2024 07:49:00 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 5 Jun 2024 07:49:00 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 5 Jun 2024 07:49:00 -0500 Received: from localhost ([10.249.48.175]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 455Cn0tD108876; Wed, 5 Jun 2024 07:49:00 -0500 From: Hari Nagalla To: , , , , , CC: , , Subject: [PATCH v3 2/4] arm64: dts: k3-am62a-mcu: Add R5F remote proc node Date: Wed, 5 Jun 2024 07:48:57 -0500 Message-ID: <20240605124859.3034-3-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605124859.3034-1-hnagalla@ti.com> References: <20240605124859.3034-1-hnagalla@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AM62A SoCs have a single R5F core in the MCU voltage domain. The MCU domain also has a 512KB sram memory, the R5F core can use for applications needing fast memory access. Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 8c36e56f4138..803da3cce336 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -6,6 +6,17 @@ */ =20 &cbass_mcu { + mcu_ram: sram@79100000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x79100000 0x00 0x80000>; + ranges =3D <0x00 0x00 0x79100000 0x80000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mcu1-sram@0 { + reg =3D <0x0 0x80000>; + }; + }; mcu_pmx0: pinctrl@4084000 { compatible =3D "pinctrl-single"; reg =3D <0x00 0x04084000 0x00 0x88>; @@ -167,4 +178,28 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains =3D <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + mcu_r5fss0_core0: r5f@79000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <9>; + ti,sci-proc-ids =3D <0x03 0xff>; + resets =3D <&k3_reset 9 1>; + firmware-name =3D "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable =3D <0>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <0>; + sram =3D <&mcu_ram>; + }; + }; }; --=20 2.34.1 From nobody Thu Feb 12 23:04:08 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3F9F14C5A0; Wed, 5 Jun 2024 12:49:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717591750; cv=none; b=A2xHe03CUzdfeCpMVZQlJkIz+z9I3+/Vjdhl3YBB05bbsfokj3juzpNALQNKnu7XgEjM9qMoKBPH/Qxf8jXePg7UwpGTGhjIYTJBRF1mkau2if8JdLPdZYusIK71F/XXpFChdJytJ+UfjQElBJ8K3m7m2q2ApUlc+nmvM3llrUE= ARC-Message-Signature: i=1; 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Wed, 5 Jun 2024 07:49:00 -0500 Received: from localhost ([10.249.48.175]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 455Cn0ha058472; Wed, 5 Jun 2024 07:49:00 -0500 From: Hari Nagalla To: , , , , , CC: , , Subject: [PATCH v3 3/4] arm64: dts: k3-am62a-wakeup: Add R5F device node Date: Wed, 5 Jun 2024 07:48:58 -0500 Message-ID: <20240605124859.3034-4-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605124859.3034-1-hnagalla@ti.com> References: <20240605124859.3034-1-hnagalla@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar AM62A SoCs have a single R5F core in waekup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 98043e9aa316..70471d969aa6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -73,6 +73,29 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.34.1 From nobody Thu Feb 12 23:04:08 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A352195998; Wed, 5 Jun 2024 12:49:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717591749; cv=none; b=RKFt1BlbDmiz4Wzy3kwqoQ1uZ6Lw9WiC2mOQlwTAoftxFBQLKBoHxcoS9UKq8IUE1QIkjhT7nyuACj2XrjG9Uj6grZ38DK/xD9Zz9zz3gxU7HINs3oNT2roOrgSFtSXkwl7/3aRnXp2S3y4K1Z/9tT5jYfYa3y2XmsYu34hask8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 5 Jun 2024 07:49:00 -0500 Received: from localhost ([10.249.48.175]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 455Cn0Zh058475; Wed, 5 Jun 2024 07:49:00 -0500 From: Hari Nagalla To: , , , , , CC: , , Subject: [PATCH v3 4/4] arm64: dts: ti: k3-am62a7-sk: Enable ipc with remote proc nodes Date: Wed, 5 Jun 2024 07:48:59 -0500 Message-ID: <20240605124859.3034-5-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605124859.3034-1-hnagalla@ti.com> References: <20240605124859.3034-1-hnagalla@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar Reserve memory for remote rpoc IPC and bind the mailbox assignments for each remote proc. Two memory regions are reserved for each remote processor. The first region of 1Mb of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor, resource table and as tracebuffer. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 68 +++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index fa43cd0b631e..09bb8af53b1e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -52,11 +52,40 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0x01e00000>; no-map; }; + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0x0f00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0x01efffff>; + no-map; + }; }; =20 vmain_pd: regulator-0 { @@ -721,3 +750,42 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; --=20 2.34.1