From nobody Thu Feb 12 23:05:25 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E22A1B1436 for ; Wed, 5 Jun 2024 12:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589743; cv=none; b=gUrVve+rd70EZfbqAmo63GHcGN7MTmHup7XCgK0cFBxh6Sg2r7Xq70v0n0KLBT/+c+QPcRr3nKu7AI83CmD7Qzp11W5w0r2h+nSJM4w/SUqgdPVIwUWPrWb/Dk+YVTq36ILPEu3aafliLqlIwcIcjDcd3KTEAxJyIo9Zr59cAmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589743; c=relaxed/simple; bh=hTmtsdXYiGBOLJKJx4/m17z57Knu5252Lz/eRo2JFWI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=tVaScMzJzYCdbxTHMZhlJ3xHFGeO9AksEeM6Wjw1WLMJHdsLP7KRSrmX+GekxScIgW0rzlJO213sx6xjnRaJJaBtax+7yQc/DC5LUxYAY1NB3JSt3E07FXrLRrahSg09J90A9mNlCX/3J2f0z4J0pfaHQK51oSP3dGS+ruFFOPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=UDhwyHgP; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="UDhwyHgP" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-702342c60dfso1609516b3a.2 for ; Wed, 05 Jun 2024 05:15:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589740; x=1718194540; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=M6DDIEotd8EWgMMcCZznOzCPmVBacRxZ1YaVEsFTRqc=; b=UDhwyHgPpWAaVxQKTTVkYKghXtatBoosfgNf5Qj1AeEyBbAD8kumMCFCZAQay4BDx9 7KG9uioFFCmQ7n/dPaKE0M8H9u6ewES6wyge6sJQCIZHq6ZkEF23AulF+9h6webjFuQ3 neJHZU0fYs9ybdF77bhXaqBbsbtQBOdIKv/hlc402Cxcwt4+ZmtxFIObarHRox8bCNu0 20qLcLKiIjyLRxg8A9OUr19IRMdzbZGfmpxlCtmC5LpvUed290N1Vw4WIQxTMdFy/fVj vMB076wOOTurfbHJDRv1nVcqzCGXuWWGOfLNRQ77bHy3aKzjEY39CAbMViIdOh4f5c07 a1qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589740; x=1718194540; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=M6DDIEotd8EWgMMcCZznOzCPmVBacRxZ1YaVEsFTRqc=; b=uNqAjLO6CISb1GeYKTiRKqY4b8aRDm4w3PZ6MAEqesK5hYO19qL+6tPMvcHbYIZ6ZS 3K6SFVpMN0VqhEwxAmejqJWgF9pc6G1FIhrLF9G4/uM5npUaP93I7as00swVWlKzdAdN icDYxbGzC2K2cVDgVDiqsWtrkyRsTiuKgkqU5HPg0GJmmpEWnhb0XDdneBRxXqswoOgz GTPdOiYACBv8q0toJoe2ldPflBYtD4XEDbHwW5lJmZkH3hFaWtJNJZwGNppfoAgCx+C9 YNbH6d/PNF23w2A31IP+wCBjyJSwB7QpxLSxQyokevEufV9rMmc81XYBW0hDb9ZfJGAV J9vg== X-Gm-Message-State: AOJu0Yyo4xkrTW8I8fHgJ5W67JIq1cDKCPfsXus8cbFYVBa47zmGT9qY qYs3heYpwSlj3Pil7SZ4WglkC3EJXkqe4h/H/qqD2jmwffaYm2Fj3LRhfctTGeeiI/OlJfNzgSG WpKOaq4qkigwAi5f2//uNxhvGIZ+890WReL37w+BI2/1DMhcCegp2aIWVsAHNbzwPDp4LodIEbr Q9sGLWWQRRyGZfbh6SBNmTcWB29RRcRGY8jTfCkJul4ZpLnZdGnfDVZg== X-Google-Smtp-Source: AGHT+IH3nqH0HygTrtx132GmRiIh9ksqvzFGs1AgXrG45C29IYpnZlxfse4GWma8yLnINlc5RX1TYA== X-Received: by 2002:a05:6a00:b4b:b0:703:ee76:6e5a with SMTP id d2e1a72fcca58-703ee7670c1mr1282317b3a.0.1717589739980; Wed, 05 Jun 2024 05:15:39 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:39 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , wchen , Samuel Ortiz , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , "Mike Rapoport (IBM)" , Kemeng Shi , Samuel Holland , Jisheng Zhang , Charlie Jenkins , "Matthew Wilcox (Oracle)" , Leonardo Bras Subject: [PATCH v5 1/4] RISC-V: Add Svade and Svadu Extensions Support Date: Wed, 5 Jun 2024 20:15:07 +0800 Message-Id: <20240605121512.32083-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Svade and Svadu extensions represent two schemes for managing the PTE A/D bits. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. Since the Svade extension is mandatory and the Svadu extension is optional in RVA23 profile, by default the M-mode firmware will enable the Svadu extension in the menvcfg CSR when only Svadu is present in DT. This patch detects Svade and Svadu extensions from DT and adds arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() when we have the PTE A/D bits hardware updating support. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 14 +++++++++++++- arch/riscv/kernel/cpufeature.c | 2 ++ 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b94176e25be1..dbfe2be99bf9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -36,6 +36,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..524cd4131c71 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -195,6 +195,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..35d7aa49785d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADE 75 +#define RISCV_ISA_EXT_SVADU 76 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index aad8b8ca51f1..7287ea4a6160 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -120,6 +120,7 @@ #include #include #include +#include =20 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_S= HIFT) =20 @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) } =20 #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include =20 static __always_inline bool has_svnapot(void) { @@ -624,6 +624,18 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _p= rot) return __pgprot(prot); } =20 +/* + * Both Svade and Svadu control the hardware behavior when the PTE A/D bit= s need to be set. By + * default the M-mode firmware enables the hardware updating scheme when o= nly Svadu is present in + * DT. + */ +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU) && + !riscv_has_extension_likely(RISCV_ISA_EXT_SVADE); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5ef48cb20ee1..58565798cea0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), --=20 2.17.1 From nobody Thu Feb 12 23:05:25 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D9F41B1501 for ; Wed, 5 Jun 2024 12:15:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589748; cv=none; b=uN9QF6lwmHdTx9r9i3fqssnGh0D1dM+F0RqQk9xyvAY8UnvGzxpzZiZSMQJeQ22FyXSP+OT2Ob/GDCv7zh+Hi0+TJlAw8kds7hI2LmTQaziGnE5cHIVKfQM6vWj2zvdFJIbysfCG6YXJSb18i5+b6yqa1/KTgOPW4nTWb4iXqo0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589748; c=relaxed/simple; bh=7vv9BIxOlTAnkVcmOEbkz5pJ3DyqNEvdcN47CRhSbiU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=q02P3LOvo6XkoVPUAGbp8ukqDLA9nHy4Sd3Qe7dkpqOWzLtbwxj3GQBFfbtGSFdp90TkA+qAEyJu4L07J3NOP3Q8S/oCL7z44eNMSaiAvwDC+HWz54enHy6IkIWNpxqOP60EoRdwNPXUiP4T/9zsTnSasBfsCtAHqbTYJH32PP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=iAZOCUTk; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="iAZOCUTk" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-7025b253f64so3097505b3a.3 for ; Wed, 05 Jun 2024 05:15:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589746; x=1718194546; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=GpvzkiCxKozJEFTOhtS0qkQgzMcSqTc8pxD/W7VEhXs=; b=iAZOCUTk8lI8+n+8mWwcJ0NmiEDHnk1vcO8fqJcwNa0tQM5nv5fkI+3Jy8YP29dF81 D8Ah6eBR6hqtGY6jF+B0ABj2UMKQ+19NoS/ElCSdkB/CF1so69yUqThKEprEROcAeorn jkikUg9Yk0U4yWWGRVYcRBiHwUWfUpXGYIAzH1Zk4zTT8JuPjvpieLXJ1WRZUDRwRtyy 9HAZUfiPtVB/BVhCMJ3gA+qIxKvHporUhrs9oAYtD2vWfvU2/JtUX+x6Hy5yWDddL9yu d0jjyMjXhHH8SZPRiBBooR5p5w47z3QLpyx4u54qsryesmJVdYyn5BfqYstzeKFJs/jZ SLiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589746; x=1718194546; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GpvzkiCxKozJEFTOhtS0qkQgzMcSqTc8pxD/W7VEhXs=; b=HlsuY7eUp0iZb/B7A7m6QmdzR/DEhhK0mR+OywoNYD0LxtJIktifqBkRK4CwfxVjX/ maXYWP0iTJQc/IuQKC+ktRLWDFVvsruFNAKSQO5s3/+lRXIP4VGtjwZb3WjK+MWFhuyk 1ZwowopNg86ua06vbIDzgdROZ2ii+KUvh7CHwudSjpsuIWHP7102eNk7uVJzTv+92d1I weO7c4FLkgl181IGCJgaq011PzJJgJmW+Vwk6t9nEtBSM60/IUYIR0ANrSRr2A0CELxm Cnct7gWOgrxE4FW/QIVMAW+PAihbhBmvrqwyIte5ho2tO5H48QzUkVtopI0YOZFpcweo GzQQ== X-Gm-Message-State: AOJu0Yx/5COFnJMIuJFDLJrIox5YIKw9WRkJyb0ggOVbPYt4cVGlEHL1 VC/I2DXps/0r1wOfbo0tovVT8U6GVsn+zGjvnj8vt9YFu4rtvSp1/BZMNOCKmQnFiNIqSxv3RDb naF1kOdCkzmT6bfHzgehb/aPQmQ8dw8nnrAAg+7aAx0rQ1BFOTrttIKeo6SMRFocXzD2d3+i9eG vJjfcSIH7jCjeq0xP1HH2tQX3sz2FVPNBlH1+wjfBbUIwl53aY9kXtYw== X-Google-Smtp-Source: AGHT+IHxvvSw4LHcVUp46xf5eLnBwmt4LaRfb4YBe++3w64DoItEt1ztOFnT7PyaQMcSTm6fON3nVA== X-Received: by 2002:a05:6a00:1991:b0:6ed:de6e:dd24 with SMTP id d2e1a72fcca58-703e597aa21mr2623604b3a.16.1717589744922; Wed, 05 Jun 2024 05:15:44 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:44 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Date: Wed, 5 Jun 2024 20:15:08 +0800 Message-Id: <20240605121512.32083-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang --- .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..1e30988826b9 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,36 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. =20 + - const: svade + description: | + The standard Svade supervisor-level extension for raising page= -fault + exceptions when PTE A/D bits need be set as ratified in the 20= 240213 + version of the privileged ISA specification. + + Both Svade and Svadu extensions control the hardware behavior = when + the PTE A/D bits need to be set. The default behavior for the = four + possible combinations of these extensions in the device tree a= re: + 1. Neither svade nor svadu in DT: default to svade. + 2. Only svade in DT: use svade. + 3. Only svadu in DT: use svadu. + 4. Both svade and svadu in DT: default to svade (Linux can swi= tch to + svadu once the SBI FWFT extension is available). + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware upd= ating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull req= uest + #25 from ved-rivos/ratified") of riscv-svadu. + + Both Svade and Svadu extensions control the hardware behavior = when + the PTE A/D bits need to be set. The default behavior for the = four + possible combinations of these extensions in the device tree a= re: + 1. Neither svade nor svadu in DT: default to svade. + 2. Only svade in DT: use svade. + 3. Only svadu in DT: use svadu. + 4. Both svade and svadu in DT: default to svade (Linux can swi= tch to + svadu once the SBI FWFT extension is available). + - const: svinval description: The standard Svinval supervisor-level extension for fine-grain= ed --=20 2.17.1 From nobody Thu Feb 12 23:05:25 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00C7D198830 for ; Wed, 5 Jun 2024 12:15:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589752; cv=none; b=Nm3BRu7mE8KuAc6RRzDz6MqJ8f2KDkG8Nzg6DkSWCBko6t2iJdUXVqkooIIIEVRiiHNDsnuOh8ItaWXdJkBX5n50B1vgyiPsKrlUK2KoEyRMjrqvXz3+OSh0W+7ojRqZs6ptSi19m8C0uvcnYO6UagZ+vUM24sv+lhYTFkmgqnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589752; c=relaxed/simple; bh=CRu+PRCiIUbcgK7k+OALzNd3CLHlGYyDDJJ1/w/c3G0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=IlcVgViUHlQM1mr/H3CG9lmO1mY8hrQPJsPBhVMxxC9clc2ooOAuWOsxJWOcHqOMJuW5p5IvlX2tBGmiYifH6GLFnP7u97XU3dUwlauUUZMZ9pnASdoytgC5WNm48Rhvv8ZSI7iNnlszlDixhfKOFH/02qMdzbvWCPOTKdx+0zM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=TdXZ+kdV; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="TdXZ+kdV" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-70257104b4dso3371365b3a.1 for ; Wed, 05 Jun 2024 05:15:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589750; x=1718194550; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=C9yGW+vb+251DuCHvQ6eWHokjrDaPZ1CHdh15Wr7+D4=; b=TdXZ+kdVAYeqgf6FzrHoOcCipHaldgDwM/fSwuj5BsxAeA3j2UOuE6q55DCelFKbjh Lp97yCa0oHXKisVjjsxb5p/4OuM/weATVjS7bJmlCyakg8R/Lq3MELYNB7yfAeo9resh EnGTAFRW6KQQIRk6ImmTYvV6l/D1aYljinGQO23JG6qBsxKBoGJHFKwrxQr5ekrIIMcH /cTiTVl7HUD9an23rhSAWyXx2BfH3dZAE/JgUdP9M7cBtJKoQ9//GqyQLBJmM6Scf9R0 UHn9PIgtmTxvPKO2lAm+56eUrk3B4QWgtCSdMpX5rPZ+TZaIw8yonyS1h8sXXh6I9+Ri IuoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589750; x=1718194550; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=C9yGW+vb+251DuCHvQ6eWHokjrDaPZ1CHdh15Wr7+D4=; b=ZOKFGOoYCLTvXzYRen3bE3QiWAxsRx5qGhkSngvhgV850LY6usXxKbC+qmZJAj2+7+ rbzulO77Yn+RgTrZOTttBuRlvWao7gAfdlJzwrZV+QxeiztnOcrk64ycSWIcSPElZZ8K Z/H2kKl3kIAQWgXU9Iw4PRnVQECRSeidI2wiDJeQT257gH9QyMgG1gDxctGfdwC0hRlF MHJcFIXXJeUqPXad//1vaa1hDYss9v2qYZoqW0u1ZI/BBrFjpmDJVanF9DOWX/KXvnc4 i+XmkQqRLa3xCZ9lv10BM/EtmPSk7VZyVRR66Z7PdVqWbwDhJlaoFNlyy/UYHLSYkBDM gHNg== X-Gm-Message-State: AOJu0YzWgH4STmnJTlvI104SRyHTGJsc8WJGXHW/a4sfAIPGoQfVOhp2 6Cpw70JqgpID6XgToUcoaoMvEZRAECfCKuytgOO3D4ykROYqN5PZrgBwG2kdRUyPjnq/W/OrioC LpTMt9k5en+ysONP4SE3YsG3vbIlPpZ1YQd/a5D+4r0XEnzpMeG/TUwOtWq+ec/yHzRpAR5tsKb C9D7MCinoPYGObd/NS3r8gYFcu5plmwVPm4CPY7b3larT/PNDQcjZb5A== X-Google-Smtp-Source: AGHT+IHuMhXVgloS9T7u/eogW1nwS9cEhCJiBxA9pyATWrWX01kMIqq28iggOkL5AgJrH0kuilEjvg== X-Received: by 2002:a05:6a00:18a0:b0:6e6:98bf:7b62 with SMTP id d2e1a72fcca58-703e594abe7mr2644243b3a.8.1717589749923; Wed, 05 Jun 2024 05:15:49 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:49 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v5 3/4] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM Date: Wed, 5 Jun 2024 20:15:09 +0800 Message-Id: <20240605121512.32083-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svade and Svadu extensions for Guest/VM. Since the henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu extension is available for Guest/VM only when arch_has_hw_pte_young() is true. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu.c | 6 ++++++ arch/riscv/kvm/vcpu_onereg.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index e878e7cc3978..a5e0c35d7e9a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_SSCOFPMF, + KVM_RISCV_ISA_EXT_SVADE, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 17e21df36cc1..21edd60c4756 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -540,6 +540,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcp= u *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |=3D ENVCFG_CBZE; =20 + if (riscv_isa_extension_available(isa, SVADU)) + cfg->henvcfg |=3D ENVCFG_ADUE; + + if (riscv_isa_extension_available(isa, SVADE)) + cfg->henvcfg &=3D ~ENVCFG_ADUE; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { cfg->hstateen0 |=3D SMSTATEEN0_HSENVCFG; if (riscv_isa_extension_available(isa, SSAIA)) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index c676275ea0a0..06e930f1e206 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) @@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -105,6 +108,9 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned = long ext) return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); case KVM_RISCV_ISA_EXT_V: return riscv_v_vstate_ctrl_user_allowed(); + case KVM_RISCV_ISA_EXT_SVADU: + /* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. */ + return arch_has_hw_pte_young(); default: break; } --=20 2.17.1 From nobody Thu Feb 12 23:05:25 2026 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE2FB1B29CF for ; Wed, 5 Jun 2024 12:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589757; cv=none; b=INoNDvDZmqbWMPkm/dAwDomCSNqMmZzKOiH9cgjrSJOPhw6HOH4afb7RAxti+L7PrsFtn8P1G2pn7BzsOGZuas3w8m3HqNXGGESYK7yG2XmpJOtDNJVsAUrMbNPMj2pLj68wWvih/b3y8lmnGLI3sADrArcny+bavks81fw0Gbo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589757; c=relaxed/simple; bh=jTQnCjAYiOnyg83RQMSJJfcBlJdwMJJeulbs10TuFN0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=kB37lgirXrfC87J7nyspUe55yDzM5Xpzg6FTS8iUaD3cbmRSTydlRQC1LJfhlV6qkCaU2bvSiSTSw0AtWhqjv5VtCszdJO54+gUbzLfci4zLSEnDMzQkJlfAtFiJMO61UnjfXcpAOY/MHp3EBILgSdxDRX8ZILI46b7CPh4DhdI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=CBitWUsR; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="CBitWUsR" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-70260814b2dso757136b3a.1 for ; Wed, 05 Jun 2024 05:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589755; x=1718194555; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=s1s067gNcLroY85Io7X9j2HhTsy4/JNlR/TnSjjDyVA=; b=CBitWUsR33hB9HOopjBrDaBMynnxWxj9jsJptpQQEiMRYqcDTNOrzWqgU12T6nM/if Js42uzlCtjQ54l343H/Qt6ze3cksIGBBpN3P85Eu9VQg8F3J8rkPF7wr3jdciHklWuN7 LpqsnFHlIKWARFzMcHv95e3qd5iT1U88MdTD19Noi6zqiitE6BJY+DzB8FVAQL17neoe FHIV14Orizcq46ErCe3sEfnfdJwVLMbYHHHvcF/ZI684TX7hIvmosQNFCuTq0JQCKSPl gu6lrE2kQfKaf0IHv1QfA94jGI9yeJQQSKzFsOj87i1oolHhpvndPscP647SKDNs4ol1 qcwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589755; x=1718194555; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=s1s067gNcLroY85Io7X9j2HhTsy4/JNlR/TnSjjDyVA=; b=d9QmCMOWPXcFRjWYaju9Ay9oAVem+l0E9Rs37rl8NO+eRiZ6EpjzjVBEeHpHnBNKiz W2OTQdOJOiu3d4Ix90WYLVsy86B3jVXtR9hTy43ZcEfjEd+wq2TFT1O6/Aed/KcewKCf j3vmQhR1hrg7KxQIVlKwKRFFIYHYyVH76gsOtFQn8CWC6+HvHOD7mTdoz/4g9nnMKJNU uj1spZqURYQiewyT1FKSuPPSmV6xvdL6AUfNy7+k5WmLiJk6yvncQ8ZFLKRDrn0A3if2 bmxvEaDDf5Yeyg5XG5V6vRKnBOpJUyKv4D8nHZ3aH5NcYC2CLrkDdRLC6wLBaRmxGbvm 4OfA== X-Gm-Message-State: AOJu0YxmuI633b5FCQutXWQ9vy2aaavjksSW5djQSTkYtPk3Wwgx/cJV Z6qfcxCJ5H2njKf2OAFjpUw2YZCYPLyzo3En+1tidVfQS2lw/fchrVfb2yb3g8ST67OluR/jFhX j3rfbWyyOxZFyrwA0WMZGQCAo1loy8qKcWq8R8XFoaIKFYXX2r+zqwerDu40Ld+y3XMo4lz51EB elYzMGFI68sDNcrBhng25P+Zyfs7Wo4SeQX1OT40pDQG0InTq3QQ26hQ== X-Google-Smtp-Source: AGHT+IE2uyoTxe3pUNkQoaQt0ajX+GBn9F8zoOHdbUYCJhav/6GYlnkgU9F3LAFV0i5BxmNjeJ1V1Q== X-Received: by 2002:a05:6a00:6082:b0:702:5514:4cb8 with SMTP id d2e1a72fcca58-7027fba0d23mr6188351b3a.4.1717589754693; Wed, 05 Jun 2024 05:15:54 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:54 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org Subject: [PATCH v5 4/4] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test Date: Wed, 5 Jun 2024 20:15:10 +0800 Message-Id: <20240605121512.32083-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update the get-reg-list test to test the Svade and Svadu Extensions are available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 222198dd6d04..1d32351ad55e 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -45,6 +45,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVADE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVPBMT: @@ -411,6 +413,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -935,6 +939,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -991,6 +997,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_smstateen, &config_sscofpmf, &config_sstc, + &config_svade, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt, --=20 2.17.1