From nobody Fri Feb 13 01:40:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E988661FCF; Wed, 5 Jun 2024 02:45:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717555501; cv=none; b=Ow02E6LylN38qm0TirTfzkMPto7NImFudBybAFNUVR8n6a63kZGt8Bhj8N3ju+EbAjDY9wZkmlUAb9qhklR4nwgyBbFsUHbKYNMaJ3xe9XPW0wU2O+kjXxVVntIP2YbQep1aC3xLeP+LyQR8qcVzr8Eq6AquRXZwJuS7QjUiy6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717555501; c=relaxed/simple; bh=FDf5zzQ+v5cGiDh1foXKTg7f+Waq+BKAU/17GevLwGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TfCXlIJAyXD6huXzQ9RrJzwfOWbII+Ev1m6H/t7Jxz9QAhwK8g+B0sHxmEwkX/W1vTYzBhF5w+kAqkXTJhqIxYF12yc4RbxiSAHXlATE6tYk2nVtxYOjwtqX54iGhsBg4y2SQYeggWVcwwHTDCyLtSjBPJ8QCaLex4NTYL9K8Es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kMhJWntr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kMhJWntr" Received: by smtp.kernel.org (Postfix) with ESMTPS id 92883C32782; Wed, 5 Jun 2024 02:45:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717555500; bh=FDf5zzQ+v5cGiDh1foXKTg7f+Waq+BKAU/17GevLwGo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kMhJWntrpqBKRWB+Cx4UNADUFjicMNqSCTG2LceTVZJFAuGlMvkUkk46gDnkLV3B1 a6qBIUE2qdBk9v3830YPHIXdfPPXsNDP+1YZ+MmFtjGtC+BAmtNPCqZ+2DccMDnhrQ XJnAr2CqmEmcJvYVoBY3wTgUEa2dAMh+Dk1Yi1JHDVyIHqtIGWm1CUyleIVJ6JDEOk YaUATLaPJ9e+YHJyp+JJZhBkc/iDQ8gNt23Cd59kk+jNFss7kxwBS5zXuwpTnt/hr+ XZHaCuMdK4Ty0yT0oWwRorZPznZ1oSNaeAtptA38dP/buV2F76FwwrTen/GWs9+0wx Ozu+m1DruOs+A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81282C27C5F; Wed, 5 Jun 2024 02:45:00 +0000 (UTC) From: Kelvin Zhang via B4 Relay Date: Wed, 05 Jun 2024 10:44:56 +0800 Subject: [PATCH v7 2/2] arm64: dts: amlogic: Add Amlogic S4 PWM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240605-s4-pwm-v7-2-e822b271d7b0@amlogic.com> References: <20240605-s4-pwm-v7-0-e822b271d7b0@amlogic.com> In-Reply-To: <20240605-s4-pwm-v7-0-e822b271d7b0@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kelvin Zhang , Junyi Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717555496; l=4918; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=IOVTUcHNUX3vbRXiLL96K2G4xrbHGVHRPhA7LupksYg=; b=4mI0mnFa16nSUyGIwKZLWj9HCy5F5bnnM4Pk6lY556JvNmPQTMDsdEM7zFknOT3eR5FxI6ufW KGLEAXC7MWuBa2q13I1n3GOW+ONoIiwqqvS/pUcrwptxEQI+rYXD6Wa X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang Reply-To: kelvin.zhang@amlogic.com From: Junyi Zhao Add device nodes for PWM_AB, PWM_CD, PWM_EF, PWM_GH and PWM_IJ along with GPIO PIN configs of each channel. Signed-off-by: Junyi Zhao Signed-off-by: Kelvin Zhang Reviewed-by: George Stark --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 199 ++++++++++++++++++++++++++= ++++ 1 file changed, 199 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-s4.dtsi index 10896f9df682..b686eacb9662 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -312,6 +312,160 @@ mux { }; }; =20 + pwm_a_pins1: pwm-a-pins1 { + mux { + groups =3D "pwm_a_d"; + function =3D "pwm_a"; + }; + }; + + pwm_a_pins2: pwm-a-pins2 { + mux { + groups =3D "pwm_a_x"; + function =3D "pwm_a"; + }; + }; + + pwm_b_pins1: pwm-b-pins1 { + mux { + groups =3D "pwm_b_d"; + function =3D "pwm_b"; + }; + }; + + pwm_b_pins2: pwm-b-pins2 { + mux { + groups =3D "pwm_b_x"; + function =3D "pwm_b"; + }; + }; + + pwm_c_pins1: pwm-c-pins1 { + mux { + groups =3D "pwm_c_d"; + function =3D "pwm_c"; + }; + }; + + pwm_c_pins2: pwm-c-pins2 { + mux { + groups =3D "pwm_c_x"; + function =3D "pwm_c"; + }; + }; + + pwm_d_pins1: pwm-d-pins1 { + mux { + groups =3D "pwm_d_d"; + function =3D "pwm_d"; + }; + }; + + pwm_d_pins2: pwm-d-pins2 { + mux { + groups =3D "pwm_d_h"; + function =3D "pwm_d"; + }; + }; + + pwm_e_pins1: pwm-e-pins1 { + mux { + groups =3D "pwm_e_x"; + function =3D "pwm_e"; + }; + }; + + pwm_e_pins2: pwm-e-pins2 { + mux { + groups =3D "pwm_e_z"; + function =3D "pwm_e"; + }; + }; + + pwm_f_pins1: pwm-f-pins1 { + mux { + groups =3D "pwm_f_x"; + function =3D "pwm_f"; + }; + }; + + pwm_f_pins2: pwm-f-pins2 { + mux { + groups =3D "pwm_f_z"; + function =3D "pwm_f"; + }; + }; + + pwm_g_pins1: pwm-g-pins1 { + mux { + groups =3D "pwm_g_d"; + function =3D "pwm_g"; + }; + }; + + pwm_g_pins2: pwm-g-pins2 { + mux { + groups =3D "pwm_g_z"; + function =3D "pwm_g"; + }; + }; + + pwm_h_pins: pwm-h-pins { + mux { + groups =3D "pwm_h"; + function =3D "pwm_h"; + }; + }; + + pwm_i_pins1: pwm-i-pins1 { + mux { + groups =3D "pwm_i_d"; + function =3D "pwm_i"; + }; + }; + + pwm_i_pins2: pwm-i-pins2 { + mux { + groups =3D "pwm_i_h"; + function =3D "pwm_i"; + }; + }; + + pwm_j_pins: pwm-j-pins { + mux { + groups =3D "pwm_j"; + function =3D "pwm_j"; + }; + }; + + pwm_a_hiz_pins: pwm-a-hiz-pins { + mux { + groups =3D "pwm_a_hiz"; + function =3D "pwm_a_hiz"; + }; + }; + + pwm_b_hiz_pins: pwm-b-hiz-pins { + mux { + groups =3D "pwm_b_hiz"; + function =3D "pwm_b_hiz"; + }; + }; + + pwm_c_hiz_pins: pwm-c-hiz-pins { + mux { + groups =3D "pwm_c_hiz"; + function =3D "pwm_c_hiz"; + }; + }; + + pwm_g_hiz_pins: pwm-g-hiz-pins { + mux { + groups =3D "pwm_g_hiz"; + function =3D "pwm_g_hiz"; + }; + }; + spicc0_pins_x: spicc0-pins_x { mux { groups =3D "spi_a_mosi_x", @@ -399,6 +553,51 @@ spicc0: spi@50000 { status =3D "disabled"; }; =20 + pwm_ab: pwm@58000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x58000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_A>, + <&clkc_periphs CLKID_PWM_B>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_cd: pwm@5a000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x5a000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_C>, + <&clkc_periphs CLKID_PWM_D>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_ef: pwm@5c000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x5c000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_E>, + <&clkc_periphs CLKID_PWM_F>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_gh: pwm@5e000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x5e000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_G>, + <&clkc_periphs CLKID_PWM_H>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_ij: pwm@60000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x60000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_I>, + <&clkc_periphs CLKID_PWM_J>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + i2c0: i2c@66000 { compatible =3D "amlogic,meson-axg-i2c"; reg =3D <0x0 0x66000 0x0 0x20>; --=20 2.37.1