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[2003:c9:3f02:d100:4c15:7eb0:f018:dd01]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6ae4b4179f4sm30558826d6.113.2024.06.03.06.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:05:15 -0700 (PDT) From: Sebastian Ott To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Shaoqin Huang , Eric Auger Subject: [PATCH v4 1/6] KVM: arm64: unify code to prepare traps Date: Mon, 3 Jun 2024 15:05:02 +0200 Message-ID: <20240603130507.17597-2-sebott@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603130507.17597-1-sebott@redhat.com> References: <20240603130507.17597-1-sebott@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are 2 functions to calculate traps via HCR_EL2: * kvm_init_sysreg() called via KVM_RUN (before the 1st run or when the pid changes) * vcpu_reset_hcr() called via KVM_ARM_VCPU_INIT To unify these 2 and to support traps that are dependent on the ID register configuration, move the code from vcpu_reset_hcr() to sys_regs.c and call it via kvm_init_sysreg(). We still have to keep the non-FWB handling stuff in vcpu_reset_hcr(). Also the initialization with HCR_GUEST_FLAGS is kept there but guarded by !vcpu_has_run_once() to ensure that previous calculated values don't get overwritten. While at it rename kvm_init_sysreg() to kvm_calculate_traps() to better reflect what it's doing. Signed-off-by: Sebastian Ott Reviewed-by: Eric Auger --- arch/arm64/include/asm/kvm_emulate.h | 40 +++++++--------------------- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/kvm/arm.c | 2 +- arch/arm64/kvm/sys_regs.c | 34 +++++++++++++++++++++-- 4 files changed, 43 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 501e3e019c93..84dc3fac9711 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -69,39 +69,17 @@ static __always_inline bool vcpu_el1_is_32bit(struct kv= m_vcpu *vcpu) =20 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) { - vcpu->arch.hcr_el2 =3D HCR_GUEST_FLAGS; - if (has_vhe() || has_hvhe()) - vcpu->arch.hcr_el2 |=3D HCR_E2H; - if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { - /* route synchronous external abort exceptions to EL2 */ - vcpu->arch.hcr_el2 |=3D HCR_TEA; - /* trap error record accesses */ - vcpu->arch.hcr_el2 |=3D HCR_TERR; - } + if (!vcpu_has_run_once(vcpu)) + vcpu->arch.hcr_el2 =3D HCR_GUEST_FLAGS; =20 - if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) { - vcpu->arch.hcr_el2 |=3D HCR_FWB; - } else { - /* - * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C - * get set in SCTLR_EL1 such that we can detect when the guest - * MMU gets turned on and do the necessary cache maintenance - * then. - */ + /* + * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C + * get set in SCTLR_EL1 such that we can detect when the guest + * MMU gets turned on and do the necessary cache maintenance + * then. + */ + if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) vcpu->arch.hcr_el2 |=3D HCR_TVM; - } - - if (cpus_have_final_cap(ARM64_HAS_EVT) && - !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE)) - vcpu->arch.hcr_el2 |=3D HCR_TID4; - else - vcpu->arch.hcr_el2 |=3D HCR_TID2; - - if (vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 &=3D ~HCR_RW; - - if (kvm_has_mte(vcpu->kvm)) - vcpu->arch.hcr_el2 |=3D HCR_ATA; } =20 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 8170c04fde91..212ae77eefaf 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1122,7 +1122,7 @@ int __init populate_nv_trap_config(void); bool lock_all_vcpus(struct kvm *kvm); void unlock_all_vcpus(struct kvm *kvm); =20 -void kvm_init_sysreg(struct kvm_vcpu *); +void kvm_calculate_traps(struct kvm_vcpu *); =20 /* MMIO helpers */ void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 9996a989b52e..6b217afb4e8e 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -797,7 +797,7 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) * This needs to happen after NV has imposed its own restrictions on * the feature set */ - kvm_init_sysreg(vcpu); + kvm_calculate_traps(vcpu); =20 ret =3D kvm_timer_enable(vcpu); if (ret) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 22b45a15d068..41741bf4d2b2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4041,11 +4041,33 @@ int kvm_vm_ioctl_get_reg_writable_masks(struct kvm = *kvm, struct reg_mask_range * return 0; } =20 -void kvm_init_sysreg(struct kvm_vcpu *vcpu) +static void vcpu_set_hcr(struct kvm_vcpu *vcpu) { struct kvm *kvm =3D vcpu->kvm; =20 - mutex_lock(&kvm->arch.config_lock); + if (has_vhe() || has_hvhe()) + vcpu->arch.hcr_el2 |=3D HCR_E2H; + if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { + /* route synchronous external abort exceptions to EL2 */ + vcpu->arch.hcr_el2 |=3D HCR_TEA; + /* trap error record accesses */ + vcpu->arch.hcr_el2 |=3D HCR_TERR; + } + + if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) + vcpu->arch.hcr_el2 |=3D HCR_FWB; + + if (cpus_have_final_cap(ARM64_HAS_EVT) && + !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE)) + vcpu->arch.hcr_el2 |=3D HCR_TID4; + else + vcpu->arch.hcr_el2 |=3D HCR_TID2; + + if (vcpu_el1_is_32bit(vcpu)) + vcpu->arch.hcr_el2 &=3D ~HCR_RW; + + if (kvm_has_mte(vcpu->kvm)) + vcpu->arch.hcr_el2 |=3D HCR_ATA; =20 /* * In the absence of FGT, we cannot independently trap TLBI @@ -4054,6 +4076,14 @@ void kvm_init_sysreg(struct kvm_vcpu *vcpu) */ if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) vcpu->arch.hcr_el2 |=3D HCR_TTLBOS; +} + +void kvm_calculate_traps(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; 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[2003:c9:3f02:d100:4c15:7eb0:f018:dd01]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6ae4b4179f4sm30558826d6.113.2024.06.03.06.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:05:18 -0700 (PDT) From: Sebastian Ott To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Shaoqin Huang , Eric Auger Subject: [PATCH v4 2/6] KVM: arm64: maintain per VM value for CTR_EL0 Date: Mon, 3 Jun 2024 15:05:03 +0200 Message-ID: <20240603130507.17597-3-sebott@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603130507.17597-1-sebott@redhat.com> References: <20240603130507.17597-1-sebott@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for CTR_EL0 emulation maintain a per VM value for this register and use it where appropriate. Signed-off-by: Sebastian Ott Reviewed-by: Shaoqin Huang --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/sys_regs.c | 21 ++++++++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 212ae77eefaf..1259be5e2f3e 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -331,6 +331,8 @@ struct kvm_arch { #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) u64 id_regs[KVM_ARM_ID_REG_NUM]; =20 + u64 ctr_el0; + /* Masks for VNCR-baked sysregs */ struct kvm_sysreg_masks *sysreg_masks; =20 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 41741bf4d2b2..0213c96f73f2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -219,9 +219,9 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val,= int reg) * Returns the minimum line size for the selected cache, expressed as * Log2(bytes). */ -static u8 get_min_cache_line_size(bool icache) +static u8 get_min_cache_line_size(struct kvm *kvm, bool icache) { - u64 ctr =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + u64 ctr =3D kvm->arch.ctr_el0; u8 field; =20 if (icache) @@ -248,7 +248,7 @@ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) if (vcpu->arch.ccsidr) return vcpu->arch.ccsidr[csselr]; =20 - line_size =3D get_min_cache_line_size(csselr & CSSELR_EL1_InD); + line_size =3D get_min_cache_line_size(vcpu->kvm, csselr & CSSELR_EL1_InD); =20 /* * Fabricate a CCSIDR value as the overriding value does not exist. @@ -283,7 +283,7 @@ static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr= , u32 val) u32 i; =20 if ((val & CCSIDR_EL1_RES0) || - line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) + line_size < get_min_cache_line_size(vcpu->kvm, csselr & CSSELR_EL1_In= D)) return -EINVAL; =20 if (!ccsidr) { @@ -1886,7 +1886,7 @@ static bool access_ctr(struct kvm_vcpu *vcpu, struct = sys_reg_params *p, if (p->is_write) return write_to_read_only(vcpu, p, r); =20 - p->regval =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + p->regval =3D vcpu->kvm->arch.ctr_el0; return true; } =20 @@ -1906,7 +1906,7 @@ static bool access_clidr(struct kvm_vcpu *vcpu, struc= t sys_reg_params *p, */ static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { - u64 ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + u64 ctr_el0 =3D vcpu->kvm->arch.ctr_el0; u64 clidr; u8 loc; =20 @@ -1959,8 +1959,8 @@ static u64 reset_clidr(struct kvm_vcpu *vcpu, const s= truct sys_reg_desc *r) static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { - u64 ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); u64 idc =3D !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); + u64 ctr_el0 =3D vcpu->kvm->arch.ctr_el0; =20 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) return -EINVAL; @@ -3557,6 +3557,13 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) struct kvm *kvm =3D vcpu->kvm; unsigned long i; =20 + if (!kvm_vcpu_initialized(vcpu)) + /* + * Make sure CTR_EL0 is initialized before registers + * that depend on it are reset. + */ + kvm->arch.ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + for (i =3D 0; i < ARRAY_SIZE(sys_reg_descs); i++) { const struct sys_reg_desc *r =3D &sys_reg_descs[i]; =20 --=20 2.42.0 From nobody Fri Dec 19 14:06:44 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB81E12DD83 for ; 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[2003:c9:3f02:d100:4c15:7eb0:f018:dd01]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6ae4b4179f4sm30558826d6.113.2024.06.03.06.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:05:21 -0700 (PDT) From: Sebastian Ott To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Shaoqin Huang , Eric Auger Subject: [PATCH v4 3/6] KVM: arm64: add emulation for CTR_EL0 register Date: Mon, 3 Jun 2024 15:05:04 +0200 Message-ID: <20240603130507.17597-4-sebott@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603130507.17597-1-sebott@redhat.com> References: <20240603130507.17597-1-sebott@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CTR_EL0 is currently handled as an invariant register, thus guests will be presented with the host value of that register. Add emulation for CTR_EL0 based on a per VM value. Userspace can switch off DIC and IDC bits and reduce DminLine and IminLine sizes. When CTR_EL0 is changed validate that against CLIDR_EL1 and CCSIDR_EL1 to make sure we present the guest with consistent register values. Changes that affect the generated cache topology values are allowed if they don't clash with previous register writes. Signed-off-by: Sebastian Ott --- arch/arm64/kvm/sys_regs.c | 134 +++++++++++++++++++++++++++++++++----- 1 file changed, 118 insertions(+), 16 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0213c96f73f2..39057718fbcd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -215,13 +215,8 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val= , int reg) /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 =20 -/* - * Returns the minimum line size for the selected cache, expressed as - * Log2(bytes). - */ -static u8 get_min_cache_line_size(struct kvm *kvm, bool icache) +static u8 __get_min_cache_line_size(u64 ctr, bool icache) { - u64 ctr =3D kvm->arch.ctr_el0; u8 field; =20 if (icache) @@ -240,6 +235,15 @@ static u8 get_min_cache_line_size(struct kvm *kvm, boo= l icache) return field + 2; } =20 +/* + * Returns the minimum line size for the selected cache, expressed as + * Log2(bytes). + */ +static u8 get_min_cache_line_size(struct kvm *kvm, bool icache) +{ + return __get_min_cache_line_size(kvm->arch.ctr_el0, icache); +} + /* Which cache CCSIDR represents depends on CSSELR value. */ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) { @@ -1880,6 +1884,49 @@ static int set_wi_reg(struct kvm_vcpu *vcpu, const s= truct sys_reg_desc *rd, return 0; } =20 +static const struct sys_reg_desc *get_sys_reg_desc(u32 encoding); + +static int validate_clidr_el1(u64 clidr_el1, u64 ctr_el0) +{ + u64 idc =3D !CLIDR_LOC(clidr_el1) || + (!CLIDR_LOUIS(clidr_el1) && !CLIDR_LOUU(clidr_el1)); + + if ((clidr_el1 & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) + return -EINVAL; + + return 0; +} + +static int validate_cache_topology(struct kvm_vcpu *vcpu, u64 ctr_el0) +{ + const struct sys_reg_desc *clidr_el1; + unsigned int i; + int ret; + + clidr_el1 =3D get_sys_reg_desc(SYS_CLIDR_EL1); + if (!clidr_el1) + return -ENOENT; + + ret =3D validate_clidr_el1(__vcpu_sys_reg(vcpu, clidr_el1->reg), ctr_el0); + if (ret) + return ret; + + if (!vcpu->arch.ccsidr) + return 0; + + /* + * Make sure the cache line size per level obeys the minimum + * cache line setting. + */ + for (i =3D 0; i < CSSELR_MAX; i++) { + if ((FIELD_GET(CCSIDR_EL1_LineSize, get_ccsidr(vcpu, i)) + 4) + < __get_min_cache_line_size(ctr_el0, i & CSSELR_EL1_InD)) + return -EINVAL; + } + + return 0; +} + static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1890,6 +1937,55 @@ static bool access_ctr(struct kvm_vcpu *vcpu, struct= sys_reg_params *p, return true; } =20 +static u64 reset_ctr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) +{ + vcpu->kvm->arch.ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + return vcpu->kvm->arch.ctr_el0; +} + +static int get_ctr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 *val) +{ + *val =3D vcpu->kvm->arch.ctr_el0; + return 0; +} + +static int set_ctr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + u64 ctr, writable_mask =3D rd->val; + int ret =3D 0; + + mutex_lock(&vcpu->kvm->arch.config_lock); + ctr =3D vcpu->kvm->arch.ctr_el0; + if (val =3D=3D ctr) + goto out_unlock; + + ret =3D -EBUSY; + if (kvm_vm_has_ran_once(vcpu->kvm)) + goto out_unlock; + + ret =3D -EINVAL; + if ((ctr & ~writable_mask) !=3D (val & ~writable_mask)) + goto out_unlock; + + if (((ctr & CTR_EL0_DIC_MASK) < (val & CTR_EL0_DIC_MASK)) || + ((ctr & CTR_EL0_IDC_MASK) < (val & CTR_EL0_IDC_MASK)) || + ((ctr & CTR_EL0_DminLine_MASK) < (val & CTR_EL0_DminLine_MASK)) || + ((ctr & CTR_EL0_IminLine_MASK) < (val & CTR_EL0_IminLine_MASK))) { + goto out_unlock; + } + ret =3D validate_cache_topology(vcpu, val); + if (ret) + goto out_unlock; + + vcpu->kvm->arch.ctr_el0 =3D val; +out_unlock: + mutex_unlock(&vcpu->kvm->arch.config_lock); + + return ret; +} + static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1959,10 +2055,9 @@ static u64 reset_clidr(struct kvm_vcpu *vcpu, const = struct sys_reg_desc *r) static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { - u64 idc =3D !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); u64 ctr_el0 =3D vcpu->kvm->arch.ctr_el0; =20 - if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) + if (validate_clidr_el1(val, ctr_el0)) return -EINVAL; =20 __vcpu_sys_reg(vcpu, rd->reg) =3D val; @@ -2475,7 +2570,11 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, - { SYS_DESC(SYS_CTR_EL0), access_ctr }, + { SYS_DESC(SYS_CTR_EL0), access_ctr, .reset =3D reset_ctr, + .get_user =3D get_ctr, .set_user =3D set_ctr, .val =3D (CTR_EL0_DIC_MAS= K | + CTR_EL0_IDC_MASK | + CTR_EL0_DminLine_MASK | + CTR_EL0_IminLine_MASK)}, { SYS_DESC(SYS_SVCR), undef_access }, =20 { PMU_SYS_REG(PMCR_EL0), .access =3D access_pmcr, .reset =3D reset_pmcr, @@ -3651,6 +3750,13 @@ static bool index_to_params(u64 id, struct sys_reg_p= arams *params) } } =20 +static const struct sys_reg_desc *get_sys_reg_desc(u32 encoding) +{ + struct sys_reg_params params =3D encoding_to_params(encoding); + + return find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); +} + const struct sys_reg_desc *get_reg_by_id(u64 id, const struct sys_reg_desc table[], unsigned int num) @@ -3704,18 +3810,11 @@ FUNCTION_INVARIANT(midr_el1) FUNCTION_INVARIANT(revidr_el1) FUNCTION_INVARIANT(aidr_el1) =20 -static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) -{ - ((struct sys_reg_desc *)r)->val =3D read_sanitised_ftr_reg(SYS_CTR_EL0); - return ((struct sys_reg_desc *)r)->val; -} - /* ->val is filled in by kvm_sys_reg_table_init() */ static struct sys_reg_desc invariant_sys_regs[] __ro_after_init =3D { { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, - { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, }; =20 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) @@ -4083,6 +4182,9 @@ static void vcpu_set_hcr(struct kvm_vcpu *vcpu) */ if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) vcpu->arch.hcr_el2 |=3D HCR_TTLBOS; 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[2003:c9:3f02:d100:4c15:7eb0:f018:dd01]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6ae4b4179f4sm30558826d6.113.2024.06.03.06.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:05:25 -0700 (PDT) From: Sebastian Ott To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Shaoqin Huang , Eric Auger Subject: [PATCH v4 4/6] KVM: arm64: show writable masks for feature registers Date: Mon, 3 Jun 2024 15:05:05 +0200 Message-ID: <20240603130507.17597-5-sebott@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603130507.17597-1-sebott@redhat.com> References: <20240603130507.17597-1-sebott@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of using ~0UL provide the actual writable mask for non-id feature registers in the output of the KVM_ARM_GET_REG_WRITABLE_MASKS ioctl. This changes the mask for the CTR_EL0 and CLIDR_EL1 registers. Signed-off-by: Sebastian Ott Reviewed-by: Eric Auger --- arch/arm64/kvm/sys_regs.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 39057718fbcd..8008120d021b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2566,7 +2566,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, - .set_user =3D set_clidr }, + .set_user =3D set_clidr, .val =3D ~CLIDR_EL1_RES0 }, { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, @@ -4125,20 +4125,11 @@ int kvm_vm_ioctl_get_reg_writable_masks(struct kvm = *kvm, struct reg_mask_range * if (!is_feature_id_reg(encoding) || !reg->set_user) continue; =20 - /* - * For ID registers, we return the writable mask. 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[2003:c9:3f02:d100:4c15:7eb0:f018:dd01]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6ae4b4179f4sm30558826d6.113.2024.06.03.06.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:05:28 -0700 (PDT) From: Sebastian Ott To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Shaoqin Huang , Eric Auger Subject: [PATCH v4 5/6] KVM: arm64: rename functions for invariant sys regs Date: Mon, 3 Jun 2024 15:05:06 +0200 Message-ID: <20240603130507.17597-6-sebott@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603130507.17597-1-sebott@redhat.com> References: <20240603130507.17597-1-sebott@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Invariant system id registers are populated with host values at initialization time using their .reset function cb. These are currently called get_* which is usually used by the functions implementing the .get_user callback. Change their function names to reset_* to reflect what they are used for. Signed-off-by: Sebastian Ott Reviewed-by: Eric Auger --- arch/arm64/kvm/sys_regs.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8008120d021b..12ce8461323a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3799,8 +3799,8 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, */ =20 #define FUNCTION_INVARIANT(reg) \ - static u64 get_##reg(struct kvm_vcpu *v, \ - const struct sys_reg_desc *r) \ + static u64 reset_##reg(struct kvm_vcpu *v, \ + const struct sys_reg_desc *r) \ { \ ((struct sys_reg_desc *)r)->val =3D read_sysreg(reg); \ return ((struct sys_reg_desc *)r)->val; \ @@ -3812,9 +3812,9 @@ FUNCTION_INVARIANT(aidr_el1) =20 /* ->val is filled in by kvm_sys_reg_table_init() */ static struct sys_reg_desc invariant_sys_regs[] __ro_after_init =3D { - { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, - { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, - { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, + { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, + { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, + { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, }; 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[2003:c9:3f02:d100:4c15:7eb0:f018:dd01]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6ae4b4179f4sm30558826d6.113.2024.06.03.06.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 06:05:30 -0700 (PDT) From: Sebastian Ott To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Shaoqin Huang , Eric Auger Subject: [PATCH v4 6/6] KVM: selftests: arm64: Test writes to CTR_EL0 Date: Mon, 3 Jun 2024 15:05:07 +0200 Message-ID: <20240603130507.17597-7-sebott@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603130507.17597-1-sebott@redhat.com> References: <20240603130507.17597-1-sebott@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Test that CTR_EL0 is modifiable from userspace, that changes are visible to guests, and that they are preserved across a vCPU reset. Signed-off-by: Sebastian Ott Reviewed-by: Eric Auger --- .../testing/selftests/kvm/aarch64/set_id_regs.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/test= ing/selftests/kvm/aarch64/set_id_regs.c index a7de39fa2a0a..9583c04f1228 100644 --- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -219,6 +219,7 @@ static void guest_code(void) GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); + GUEST_REG_SYNC(SYS_CTR_EL0); =20 GUEST_DONE(); } @@ -490,11 +491,25 @@ static void test_clidr(struct kvm_vcpu *vcpu) test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] =3D clidr; } =20 +static void test_ctr(struct kvm_vcpu *vcpu) +{ + u64 ctr; + + vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), &ctr); + ctr &=3D ~CTR_EL0_DIC_MASK; + if (ctr & CTR_EL0_IminLine_MASK) + ctr--; + + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr); + test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] =3D ctr; +} + static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu) { u64 val; =20 test_clidr(vcpu); + test_ctr(vcpu); =20 vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &val); val++; @@ -525,6 +540,7 @@ static void test_reset_preserves_id_regs(struct kvm_vcp= u *vcpu) test_assert_id_reg_unchanged(vcpu, test_regs[i].reg); =20 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1); + test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0); =20 ksft_test_result_pass("%s\n", __func__); } --=20 2.42.0