From nobody Fri Sep 20 01:38:22 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED3B612B142; Mon, 3 Jun 2024 12:18:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717417139; cv=none; b=ICuGR+wphS7lUAJtyrzGpO5zQdoUQVHMWfzYbEGa97vObcH5EjEUVTnS5CFST+DSEM4NFuUn4BQtqlzZ6k1oDEe58qTGiHqn8ZUORKbgo84Fw3SyLnItulR1F8NMWxEua4nnVZq+v93ftlK715MOYMe7hP7INiW6npe5FH9S8x8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717417139; c=relaxed/simple; bh=sqCZwYWvBMtvjpEOvjUA+zfHkaJdBLdJ+YYFwV0eBpc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lEYJMRl1n0pUcrKGSTasmioETOmt/aBwNve7oZvjIIpr+rpoL3movSXS16DowZ/4Cw7vZz+/1IZzyoae5/Z/t7H7wM5TuySoZu8IIVdunoG4vYyfs2zVADSsZO+y1UaQs9wecC58/3likRN7P/WDrzUb29f34x8ccn7BNTG7FsM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=J5jwqs+W; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="J5jwqs+W" X-UUID: 70d57d0421a311efbfff99f2466cf0b4-20240603 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GpuF3TmSZqXX/fQEL18HoeX4b6lM36IwNoFDvo8pmbM=; b=J5jwqs+WuCcXbEKtMyUTMAXyiUXtEbdZBb4rSx8Qf6Ko4uFsCC2HJh2CCRV1yLVXBlddhNF9yLbUulFrgHYz+uqkpYYJj7WsRXBMGuTRDDnPmmL1W9lVfO20aZMupctmA0UYdSVOJylarwcPLeQx40dXW70KSUazVp/C9PdYKK0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:9ac5bb64-16e9-4120-acd9-97ba46f048c7,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:393d96e,CLOUDID:45312788-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 70d57d0421a311efbfff99f2466cf0b4-20240603 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 763679834; Mon, 03 Jun 2024 20:18:52 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 3 Jun 2024 20:18:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 3 Jun 2024 20:18:51 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next v6 1/5] net: phy: mediatek: Re-organize MediaTek ethernet phy drivers Date: Mon, 3 Jun 2024 20:18:30 +0800 Message-ID: <20240603121834.27433-2-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240603121834.27433-1-SkyLake.Huang@mediatek.com> References: <20240603121834.27433-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "SkyLake.Huang" Re-organize MediaTek ethernet phy driver files and get ready to integrate some common functions and add new 2.5G phy driver. mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988 mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988 Signed-off-by: SkyLake.Huang --- Changes in v5: - Change MEDIATEK_GE_SOC_PHY from bool back to tristate. --- MAINTAINERS | 4 ++-- drivers/net/phy/Kconfig | 17 +------------- drivers/net/phy/Makefile | 3 +-- drivers/net/phy/mediatek/Kconfig | 22 +++++++++++++++++++ drivers/net/phy/mediatek/Makefile | 3 +++ .../mtk-ge-soc.c} | 2 +- .../phy/{mediatek-ge.c =3D> mediatek/mtk-ge.c} | 0 7 files changed, 30 insertions(+), 21 deletions(-) create mode 100644 drivers/net/phy/mediatek/Kconfig create mode 100644 drivers/net/phy/mediatek/Makefile rename drivers/net/phy/{mediatek-ge-soc.c =3D> mediatek/mtk-ge-soc.c} (99%) rename drivers/net/phy/{mediatek-ge.c =3D> mediatek/mtk-ge.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index e291445..6deaf94 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13793,8 +13793,8 @@ M: Qingfang Deng M: SkyLake Huang L: netdev@vger.kernel.org S: Maintained -F: drivers/net/phy/mediatek-ge-soc.c -F: drivers/net/phy/mediatek-ge.c +F: drivers/net/phy/mediatek/mtk-ge-soc.c +F: drivers/net/phy/mediatek/mtk-ge.c F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c =20 MEDIATEK I2C CONTROLLER DRIVER diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 1df0595..e0e4b5e 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -251,22 +251,7 @@ config MAXLINEAR_GPHY Support for the Maxlinear GPY115, GPY211, GPY212, GPY215, GPY241, GPY245 PHYs. =20 -config MEDIATEK_GE_PHY - tristate "MediaTek Gigabit Ethernet PHYs" - help - Supports the MediaTek Gigabit Ethernet PHYs. - -config MEDIATEK_GE_SOC_PHY - tristate "MediaTek SoC Ethernet PHYs" - depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST - depends on NVMEM_MTK_EFUSE - help - Supports MediaTek SoC built-in Gigabit Ethernet PHYs. - - Include support for built-in Ethernet PHYs which are present in - the MT7981 and MT7988 SoCs. These PHYs need calibration data - present in the SoCs efuse and will dynamically calibrate VCM - (common-mode voltage) during startup. +source "drivers/net/phy/mediatek/Kconfig" =20 config MICREL_PHY tristate "Micrel PHYs" diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 197acfa..de38cbf 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -71,8 +71,7 @@ obj-$(CONFIG_MARVELL_PHY) +=3D marvell.o obj-$(CONFIG_MARVELL_88Q2XXX_PHY) +=3D marvell-88q2xxx.o obj-$(CONFIG_MARVELL_88X2222_PHY) +=3D marvell-88x2222.o obj-$(CONFIG_MAXLINEAR_GPHY) +=3D mxl-gpy.o -obj-$(CONFIG_MEDIATEK_GE_PHY) +=3D mediatek-ge.o -obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) +=3D mediatek-ge-soc.o +obj-y +=3D mediatek/ obj-$(CONFIG_MESON_GXL_PHY) +=3D meson-gxl.o obj-$(CONFIG_MICREL_KS8995MA) +=3D spi_ks8995.o obj-$(CONFIG_MICREL_PHY) +=3D micrel.o diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kc= onfig new file mode 100644 index 0000000..6839ea6 --- /dev/null +++ b/drivers/net/phy/mediatek/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only +config MEDIATEK_GE_PHY + tristate "MediaTek Gigabit Ethernet PHYs" + help + Supports the MediaTek non-built-in Gigabit Ethernet PHYs. + + Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531. + You may find mt7530 inside mt7621. This driver shares some + common operations with MediaTek SoC built-in Gigabit + Ethernet PHYs. + +config MEDIATEK_GE_SOC_PHY + tristate "MediaTek SoC Ethernet PHYs" + depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST + select NVMEM_MTK_EFUSE + help + Supports MediaTek SoC built-in Gigabit Ethernet PHYs. + + Include support for built-in Ethernet PHYs which are present in + the MT7981 and MT7988 SoCs. These PHYs need calibration data + present in the SoCs efuse and will dynamically calibrate VCM + (common-mode voltage) during startup. diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/M= akefile new file mode 100644 index 0000000..005bde2 --- /dev/null +++ b/drivers/net/phy/mediatek/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_MEDIATEK_GE_PHY) +=3D mtk-ge.o +obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) +=3D mtk-ge-soc.o diff --git a/drivers/net/phy/mediatek-ge-soc.c b/drivers/net/phy/mediatek/m= tk-ge-soc.c similarity index 99% rename from drivers/net/phy/mediatek-ge-soc.c rename to drivers/net/phy/mediatek/mtk-ge-soc.c index f4f9412..47af872 100644 --- a/drivers/net/phy/mediatek-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -1415,7 +1415,7 @@ static int mt7988_phy_probe_shared(struct phy_device = *phydev) * LED_C and LED_D respectively. At the same time those pins are used to * bootstrap configuration of the reference clock source (LED_A), * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). - * In practise this is done using a LED and a resistor pulling the pin + * In practice this is done using a LED and a resistor pulling the pin * either to GND or to VIO. * The detected value at boot time is accessible at run-time using the * TPBANK0 register located in the gpio base of the pinctrl, in order diff --git a/drivers/net/phy/mediatek-ge.c b/drivers/net/phy/mediatek/mtk-g= e.c similarity index 100% rename from drivers/net/phy/mediatek-ge.c rename to drivers/net/phy/mediatek/mtk-ge.c --=20 2.34.1