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[84.229.253.184]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd0649fb5sm6582412f8f.94.2024.06.02.10.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jun 2024 10:33:23 -0700 (PDT) From: Elad Yifee To: Cc: eladwf@gmail.com, Felix Fietkau , Sean Wang , Mark Lee , Lorenzo Bianconi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v5] net: ethernet: mtk_eth_soc: ppe: add support for multiple PPEs Date: Sun, 2 Jun 2024 20:32:40 +0300 Message-ID: <20240602173247.12651-1-eladwf@gmail.com> X-Mailer: git-send-email 2.45.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the missing pieces to allow multiple PPEs units, one for each GMAC. mtk_gdm_config has been modified to work on targted mac ID, the inner loop moved outside of the function to allow unrelated operations like setting the MAC's PPE index. Signed-off-by: Elad Yifee --- v5:=09 - add sanity check for ppe index on flow_offload_replace - moved ppe_num to mtk_soc_data v4:=20 - applied changes suggested by Jakub Kicinski - modified flow_offload_replace to get the correct PPE index from flow - add gdma_to_ppe[x] registers to mtk_reg_map instead of using defines v3: applied changes suggested by Daniel Golle v2: fixed CI warnings --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 112 +++++++++++------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +- .../net/ethernet/mediatek/mtk_ppe_offload.c | 17 ++- 3 files changed, 92 insertions(+), 45 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index cae46290a7ae..ef0c1cca03d1 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -80,7 +80,9 @@ static const struct mtk_reg_map mtk_reg_map =3D { .fq_blen =3D 0x1b2c, }, .gdm1_cnt =3D 0x2400, - .gdma_to_ppe =3D 0x4444, + .gdma_to_ppe =3D { + [0] =3D 0x4444, + }, .ppe_base =3D 0x0c00, .wdma_base =3D { [0] =3D 0x2800, @@ -144,7 +146,10 @@ static const struct mtk_reg_map mt7986_reg_map =3D { .tx_sch_rate =3D 0x4798, }, .gdm1_cnt =3D 0x1c00, - .gdma_to_ppe =3D 0x3333, + .gdma_to_ppe =3D { + [0] =3D 0x3333, + [1] =3D 0x4444, + }, .ppe_base =3D 0x2000, .wdma_base =3D { [0] =3D 0x4800, @@ -192,7 +197,11 @@ static const struct mtk_reg_map mt7988_reg_map =3D { .tx_sch_rate =3D 0x4798, }, .gdm1_cnt =3D 0x1c00, - .gdma_to_ppe =3D 0x3333, + .gdma_to_ppe =3D { + [0] =3D 0x3333, + [1] =3D 0x4444, + [2] =3D 0xcccc, + }, .ppe_base =3D 0x2000, .wdma_base =3D { [0] =3D 0x4800, @@ -2009,6 +2018,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, struct mtk_rx_dma_v2 *rxd, trxd; int done =3D 0, bytes =3D 0; dma_addr_t dma_addr =3D DMA_MAPPING_ERROR; + int ppe_idx =3D 0; =20 while (done < budget) { unsigned int pktlen, *rxdcsum; @@ -2052,6 +2062,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, goto release_desc; =20 netdev =3D eth->netdev[mac]; + ppe_idx =3D eth->mac[mac]->ppe_idx; =20 if (unlikely(test_bit(MTK_RESETTING, ð->state))) goto release_desc; @@ -2175,7 +2186,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, } =20 if (reason =3D=3D MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) - mtk_ppe_check_skb(eth->ppe[0], skb, hash); + mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash); =20 skb_record_rx_queue(skb, 0); napi_gro_receive(napi, skb); @@ -3266,37 +3277,27 @@ static int mtk_start_dma(struct mtk_eth *eth) return 0; } =20 -static void mtk_gdm_config(struct mtk_eth *eth, u32 config) +static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config) { - int i; + u32 val; =20 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) return; =20 - for (i =3D 0; i < MTK_MAX_DEVS; i++) { - u32 val; - - if (!eth->netdev[i]) - continue; + val =3D mtk_r32(eth, MTK_GDMA_FWD_CFG(id)); =20 - val =3D mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); + /* default setup the forward port to send frame to PDMA */ + val &=3D ~0xffff; =20 - /* default setup the forward port to send frame to PDMA */ - val &=3D ~0xffff; + /* Enable RX checksum */ + val |=3D MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; =20 - /* Enable RX checksum */ - val |=3D MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; + val |=3D config; =20 - val |=3D config; + if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id])) + val |=3D MTK_GDMA_SPECIAL_TAG; =20 - if (netdev_uses_dsa(eth->netdev[i])) - val |=3D MTK_GDMA_SPECIAL_TAG; - - mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); - } - /* Reset and enable PSE */ - mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); - mtk_w32(eth, 0, MTK_RST_GL); + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id)); } =20 =20 @@ -3356,7 +3357,10 @@ static int mtk_open(struct net_device *dev) { struct mtk_mac *mac =3D netdev_priv(dev); struct mtk_eth *eth =3D mac->hw; - int i, err; + struct mtk_mac *target_mac; + int i, err, ppe_num; + + ppe_num =3D eth->soc->ppe_num; =20 err =3D phylink_of_phy_connect(mac->phylink, mac->of_node, 0); if (err) { @@ -3380,18 +3384,38 @@ static int mtk_open(struct net_device *dev) for (i =3D 0; i < ARRAY_SIZE(eth->ppe); i++) mtk_ppe_start(eth->ppe[i]); =20 - gdm_config =3D soc->offload_version ? soc->reg_map->gdma_to_ppe - : MTK_GDMA_TO_PDMA; - mtk_gdm_config(eth, gdm_config); + for (i =3D 0; i < MTK_MAX_DEVS; i++) { + if (!eth->netdev[i]) + break; + + target_mac =3D netdev_priv(eth->netdev[i]); + if (!soc->offload_version) { + target_mac->ppe_idx =3D 0; + gdm_config =3D MTK_GDMA_TO_PDMA; + } else if (ppe_num >=3D 3 && target_mac->id =3D=3D 2) { + target_mac->ppe_idx =3D 2; + gdm_config =3D soc->reg_map->gdma_to_ppe[2]; + } else if (ppe_num >=3D 2 && target_mac->id =3D=3D 1) { + target_mac->ppe_idx =3D 1; + gdm_config =3D soc->reg_map->gdma_to_ppe[1]; + } else { + target_mac->ppe_idx =3D 0; + gdm_config =3D soc->reg_map->gdma_to_ppe[0]; + } + mtk_gdm_config(eth, target_mac->id, gdm_config); + } + /* Reset and enable PSE */ + mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); + mtk_w32(eth, 0, MTK_RST_GL); =20 napi_enable(ð->tx_napi); napi_enable(ð->rx_napi); mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); refcount_set(ð->dma_refcnt, 1); - } - else + } else { refcount_inc(ð->dma_refcnt); + } =20 phylink_start(mac->phylink); netif_tx_start_all_queues(dev); @@ -3468,7 +3492,8 @@ static int mtk_stop(struct net_device *dev) if (!refcount_dec_and_test(ð->dma_refcnt)) return 0; =20 - mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); + for (i =3D 0; i < MTK_MAX_DEVS; i++) + mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL); =20 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); @@ -4949,23 +4974,24 @@ static int mtk_probe(struct platform_device *pdev) } =20 if (eth->soc->offload_version) { - u32 num_ppe =3D mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; + u8 ppe_num =3D eth->soc->ppe_num; =20 - num_ppe =3D min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); - for (i =3D 0; i < num_ppe; i++) { - u32 ppe_addr =3D eth->soc->reg_map->ppe_base + i * 0x400; + ppe_num =3D min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num); + for (i =3D 0; i < ppe_num; i++) { + u32 ppe_addr =3D eth->soc->reg_map->ppe_base; =20 + ppe_addr +=3D (i =3D=3D 2 ? 0xc00 : i * 0x400); eth->ppe[i] =3D mtk_ppe_init(eth, eth->base + ppe_addr, i); =20 if (!eth->ppe[i]) { err =3D -ENOMEM; goto err_deinit_ppe; } - } + err =3D mtk_eth_offload_init(eth, i); =20 - err =3D mtk_eth_offload_init(eth); - if (err) - goto err_deinit_ppe; + if (err) + goto err_deinit_ppe; + } } =20 for (i =3D 0; i < MTK_MAX_DEVS; i++) { @@ -5070,6 +5096,7 @@ static const struct mtk_soc_data mt7621_data =3D { .required_pctl =3D false, .version =3D 1, .offload_version =3D 1, + .ppe_num =3D 1, .hash_offset =3D 2, .foe_entry_size =3D MTK_FOE_ENTRY_V1_SIZE, .tx =3D { @@ -5095,6 +5122,7 @@ static const struct mtk_soc_data mt7622_data =3D { .required_pctl =3D false, .version =3D 1, .offload_version =3D 2, + .ppe_num =3D 1, .hash_offset =3D 2, .has_accounting =3D true, .foe_entry_size =3D MTK_FOE_ENTRY_V1_SIZE, @@ -5120,6 +5148,7 @@ static const struct mtk_soc_data mt7623_data =3D { .required_pctl =3D true, .version =3D 1, .offload_version =3D 1, + .ppe_num =3D 1, .hash_offset =3D 2, .foe_entry_size =3D MTK_FOE_ENTRY_V1_SIZE, .disable_pll_modes =3D true, @@ -5169,6 +5198,7 @@ static const struct mtk_soc_data mt7981_data =3D { .required_pctl =3D false, .version =3D 2, .offload_version =3D 2, + .ppe_num =3D 2, .hash_offset =3D 4, .has_accounting =3D true, .foe_entry_size =3D MTK_FOE_ENTRY_V2_SIZE, @@ -5195,6 +5225,7 @@ static const struct mtk_soc_data mt7986_data =3D { .required_pctl =3D false, .version =3D 2, .offload_version =3D 2, + .ppe_num =3D 2, .hash_offset =3D 4, .has_accounting =3D true, .foe_entry_size =3D MTK_FOE_ENTRY_V2_SIZE, @@ -5221,6 +5252,7 @@ static const struct mtk_soc_data mt7988_data =3D { .required_pctl =3D false, .version =3D 3, .offload_version =3D 2, + .ppe_num =3D 3, .hash_offset =3D 4, .has_accounting =3D true, .foe_entry_size =3D MTK_FOE_ENTRY_V3_SIZE, diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index 4eab30b44070..7d3d4b0c0b4a 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -1130,7 +1130,7 @@ struct mtk_reg_map { u32 tx_sch_rate; /* tx scheduler rate control registers */ } qdma; u32 gdm1_cnt; - u32 gdma_to_ppe; + u32 gdma_to_ppe[3]; u32 ppe_base; u32 wdma_base[3]; u32 pse_iq_sta; @@ -1168,6 +1168,7 @@ struct mtk_soc_data { u8 offload_version; u8 hash_offset; u8 version; + u8 ppe_num; u16 foe_entry_size; netdev_features_t hw_features; bool has_accounting; @@ -1289,7 +1290,7 @@ struct mtk_eth { =20 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; =20 - struct mtk_ppe *ppe[2]; + struct mtk_ppe *ppe[3]; struct rhashtable flow_table; =20 struct bpf_prog __rcu *prog; @@ -1313,6 +1314,7 @@ struct mtk_eth { */ struct mtk_mac { int id; + u8 ppe_idx; phy_interface_t interface; int speed; struct device_node *of_node; @@ -1435,7 +1437,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, in= t mac_id); int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); =20 -int mtk_eth_offload_init(struct mtk_eth *eth); +int mtk_eth_offload_init(struct mtk_eth *eth, u8 id); int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/= ethernet/mediatek/mtk_ppe_offload.c index aa262e6f4b85..f80af73d0a1b 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c @@ -245,10 +245,10 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct = flow_cls_offload *f, int ppe_index) { struct flow_rule *rule =3D flow_cls_offload_flow_rule(f); + struct net_device *idev =3D NULL, *odev =3D NULL; struct flow_action_entry *act; struct mtk_flow_data data =3D {}; struct mtk_foe_entry foe; - struct net_device *odev =3D NULL; struct mtk_flow_entry *entry; int offload_type =3D 0; int wed_index =3D -1; @@ -264,6 +264,17 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct f= low_cls_offload *f, struct flow_match_meta match; =20 flow_rule_match_meta(rule, &match); + if (mtk_is_netsys_v2_or_greater(eth)) { + idev =3D __dev_get_by_index(&init_net, match.key->ingress_ifindex); + if (idev) { + struct mtk_mac *mac =3D netdev_priv(idev); + + if (WARN_ON(mac->ppe_idx >=3D eth->soc->ppe_num)) + return -EINVAL; + + ppe_index =3D mac->ppe_idx; + } + } } else { return -EOPNOTSUPP; } @@ -637,7 +648,9 @@ int mtk_eth_setup_tc(struct net_device *dev, enum tc_se= tup_type type, } } =20 -int mtk_eth_offload_init(struct mtk_eth *eth) +int mtk_eth_offload_init(struct mtk_eth *eth, u8 id) { + if (!eth->ppe[id] || !eth->ppe[id]->foe_table) + return 0; return rhashtable_init(ð->flow_table, &mtk_flow_ht_params); } --=20 2.45.1