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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Date: Sat, 1 Jun 2024 20:33:55 +0530 Message-Id: <20240601150411.1929783-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, move these functions to common location. Signed-off-by: Sunil V L Acked-by: Bjorn Helgaas Acked-by: Will Deacon --- arch/arm64/kernel/pci.c | 191 ---------------------------------------- drivers/pci/pci-acpi.c | 182 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 191 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index f872c57e9909..fd9a7bed83ce 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -6,28 +6,7 @@ * Copyright (C) 2014 ARM Ltd. */ =20 -#include -#include -#include -#include -#include #include -#include -#include -#include - -#ifdef CONFIG_ACPI -/* - * Try to assign the IRQ number when probing a new device - */ -int pcibios_alloc_irq(struct pci_dev *dev) -{ - if (!acpi_disabled) - acpi_pci_irq_enable(dev); - - return 0; -} -#endif =20 /* * raw_pci_read/write - Platform-specific PCI config space access. @@ -61,173 +40,3 @@ int pcibus_to_node(struct pci_bus *bus) EXPORT_SYMBOL(pcibus_to_node); =20 #endif - -#ifdef CONFIG_ACPI - -struct acpi_pci_generic_root_info { - struct acpi_pci_root_info common; - struct pci_config_window *cfg; /* config space mapping */ -}; - -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - struct pci_config_window *cfg =3D bus->sysdata; - struct acpi_device *adev =3D to_acpi_device(cfg->parent); - struct acpi_pci_root *root =3D acpi_driver_data(adev); - - return root->segment; -} - -int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) -{ - struct pci_config_window *cfg; - struct acpi_device *adev; - struct device *bus_dev; - - if (acpi_disabled) - return 0; - - cfg =3D bridge->bus->sysdata; - - /* - * On Hyper-V there is no corresponding ACPI device for a root bridge, - * therefore ->parent is set as NULL by the driver. And set 'adev' as - * NULL in this case because there is no proper ACPI device. - */ - if (!cfg->parent) - adev =3D NULL; - else - adev =3D to_acpi_device(cfg->parent); - - bus_dev =3D &bridge->bus->dev; - - ACPI_COMPANION_SET(&bridge->dev, adev); - set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); - - return 0; -} - -static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) -{ - struct resource_entry *entry, *tmp; - int status; - - status =3D acpi_pci_probe_root_resources(ci); - resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { - if (!(entry->res->flags & IORESOURCE_WINDOW)) - resource_list_destroy_entry(entry); - } - return status; -} - -/* - * Lookup the bus range for the domain in MCFG, and set up config space - * mapping. - */ -static struct pci_config_window * -pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) -{ - struct device *dev =3D &root->device->dev; - struct resource *bus_res =3D &root->secondary; - u16 seg =3D root->segment; - const struct pci_ecam_ops *ecam_ops; - struct resource cfgres; - struct acpi_device *adev; - struct pci_config_window *cfg; - int ret; - - ret =3D pci_mcfg_lookup(root, &cfgres, &ecam_ops); - if (ret) { - dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); - return NULL; - } - - adev =3D acpi_resource_consumer(&cfgres); - if (adev) - dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, - dev_name(&adev->dev)); - else - dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", - &cfgres); - - cfg =3D pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); - if (IS_ERR(cfg)) { - dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, - PTR_ERR(cfg)); - return NULL; - } - - return cfg; -} - -/* release_info: free resources allocated by init_info */ -static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) -{ - struct acpi_pci_generic_root_info *ri; - - ri =3D container_of(ci, struct acpi_pci_generic_root_info, common); - pci_ecam_free(ri->cfg); - kfree(ci->ops); - kfree(ri); -} - -/* Interface called from ACPI code to setup PCI host controller */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - struct acpi_pci_generic_root_info *ri; - struct pci_bus *bus, *child; - struct acpi_pci_root_ops *root_ops; - struct pci_host_bridge *host; - - ri =3D kzalloc(sizeof(*ri), GFP_KERNEL); - if (!ri) - return NULL; - - root_ops =3D kzalloc(sizeof(*root_ops), GFP_KERNEL); - if (!root_ops) { - kfree(ri); - return NULL; - } - - ri->cfg =3D pci_acpi_setup_ecam_mapping(root); - if (!ri->cfg) { - kfree(ri); - kfree(root_ops); - return NULL; - } - - root_ops->release_info =3D pci_acpi_generic_release_info; - root_ops->prepare_resources =3D pci_acpi_root_prepare_resources; - root_ops->pci_ops =3D (struct pci_ops *)&ri->cfg->ops->pci_ops; - bus =3D acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); - if (!bus) - return NULL; - - /* If we must preserve the resource configuration, claim now */ - host =3D pci_find_host_bridge(bus); - if (host->preserve_config) - pci_bus_claim_resources(bus); - - /* - * Assign whatever was left unassigned. If we didn't claim above, - * this will reassign everything. - */ - pci_assign_unassigned_root_bus_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - return bus; -} - -void pcibios_add_bus(struct pci_bus *bus) -{ - acpi_pci_add_bus(bus); -} - -void pcibios_remove_bus(struct pci_bus *bus) -{ - acpi_pci_remove_bus(bus); -} - -#endif diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 004575091596..e8d84fa435da 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1519,3 +1520,184 @@ static int __init acpi_pci_init(void) return 0; } arch_initcall(acpi_pci_init); + +#if defined(CONFIG_ARM64) + +/* + * Try to assign the IRQ number when probing a new device + */ +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (!acpi_disabled) + acpi_pci_irq_enable(dev); + + return 0; +} + +struct acpi_pci_generic_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; /* config space mapping */ +}; + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg =3D bus->sysdata; + struct acpi_device *adev =3D to_acpi_device(cfg->parent); + struct acpi_pci_root *root =3D acpi_driver_data(adev); + + return root->segment; +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg; + struct acpi_device *adev; + struct device *bus_dev; + + if (acpi_disabled) + return 0; + + cfg =3D bridge->bus->sysdata; + + /* + * On Hyper-V there is no corresponding ACPI device for a root bridge, + * therefore ->parent is set as NULL by the driver. And set 'adev' as + * NULL in this case because there is no proper ACPI device. + */ + if (!cfg->parent) + adev =3D NULL; + else + adev =3D to_acpi_device(cfg->parent); + + bus_dev =3D &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); + + return 0; +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct resource_entry *entry, *tmp; + int status; + + status =3D acpi_pci_probe_root_resources(ci); + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (!(entry->res->flags & IORESOURCE_WINDOW)) + resource_list_destroy_entry(entry); + } + return status; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + struct device *dev =3D &root->device->dev; + struct resource *bus_res =3D &root->secondary; + u16 seg =3D root->segment; + const struct pci_ecam_ops *ecam_ops; + struct resource cfgres; + struct acpi_device *adev; + struct pci_config_window *cfg; + int ret; + + ret =3D pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret) { + dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); + return NULL; + } + + adev =3D acpi_resource_consumer(&cfgres); + if (adev) + dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, + dev_name(&adev->dev)); + else + dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", + &cfgres); + + cfg =3D pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, + PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +/* release_info: free resources allocated by init_info */ +static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_generic_root_info *ri; + + ri =3D container_of(ci, struct acpi_pci_generic_root_info, common); + pci_ecam_free(ri->cfg); + kfree(ci->ops); + kfree(ri); +} + +/* Interface called from ACPI code to setup PCI host controller */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_pci_generic_root_info *ri; + struct pci_bus *bus, *child; + struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; + + ri =3D kzalloc(sizeof(*ri), GFP_KERNEL); + if (!ri) + return NULL; + + root_ops =3D kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(ri); + return NULL; + } + + ri->cfg =3D pci_acpi_setup_ecam_mapping(root); + if (!ri->cfg) { + kfree(ri); + kfree(root_ops); + return NULL; + } + + root_ops->release_info =3D pci_acpi_generic_release_info; + root_ops->prepare_resources =3D pci_acpi_root_prepare_resources; + root_ops->pci_ops =3D (struct pci_ops *)&ri->cfg->ops->pci_ops; + bus =3D acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); + if (!bus) + return NULL; + + /* If we must preserve the resource configuration, claim now */ + host =3D pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Date: Sat, 1 Jun 2024 20:33:56 +0530 Message-Id: <20240601150411.1929783-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike OF framework, the irqchip probe using IRQCHIP_ACPI_DECLARE has no order defined. Depending on the Makefile is not a good idea. So, usually it is worked around by mandating only root interrupt controller probed using IRQCHIP_ACPI_DECLARE and other interrupt controllers are probed via cascade mechanism. However, this is also not a clean solution because if there are multiple root controllers (ex: RINTC in RISC-V which is per CPU) which need to be probed first, then the cascade will happen for every root controller. So, introduce a architecture specific weak function to order the probing of the interrupt controllers which can be implemented by different architectures as per their interrupt controller hierarchy. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 3 +++ include/linux/acpi.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 503773707e01..b325b297bf77 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2744,6 +2744,8 @@ static int __init acpi_match_madt(union acpi_subtable= _headers *header, return 0; } =20 +void __weak arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int = nr) { } + int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int= nr) { int count =3D 0; @@ -2752,6 +2754,7 @@ int __init __acpi_probe_device_table(struct acpi_prob= e_entry *ap_head, int nr) return 0; =20 mutex_lock(&acpi_probe_mutex); + arch_sort_irqchip_probe(ap_head, nr); for (ape =3D ap_head; nr; ape++, nr--) { if (ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) { acpi_probe_count =3D 0; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 28c3fb2bef0d..ab3f2880d209 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1332,6 +1332,8 @@ struct acpi_probe_entry { kernel_ulong_t driver_data; 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Sat, 01 Jun 2024 08:04:42 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 03/17] ACPI: bus: Add acpi_riscv_init function Date: Sat, 1 Jun 2024 20:33:57 +0530 Message-Id: <20240601150411.1929783-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new function for RISC-V to do architecture specific initialization similar to acpi_arm_init(). Some of the ACPI tables are architecture specific and there is no reason trying to find them on other architectures. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 12 ++++++++++++ include/linux/acpi.h | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/init.c diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 787eca838410..8d0710ade8c6 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1457,6 +1457,7 @@ static int __init acpi_init(void) acpi_hest_init(); acpi_ghes_init(); acpi_arm_init(); + acpi_riscv_init(); acpi_scan_init(); acpi_ec_init(); acpi_debugfs_init(); diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 86b0925f612d..877de00d1b50 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o +obj-y +=3D rhct.o init.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c new file mode 100644 index 000000000000..5f7571143245 --- /dev/null +++ b/drivers/acpi/riscv/init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023-2024, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include + +void __init acpi_riscv_init(void) +{ +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index ab3f2880d209..0c6d9539f737 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1520,6 +1520,12 @@ void acpi_arm_init(void); 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Sat, 01 Jun 2024 08:04:49 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 04/17] ACPI: scan: Refactor dependency creation Date: Sat, 1 Jun 2024 20:33:58 +0530 Message-Id: <20240601150411.1929783-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some architectures like RISC-V will use implicit dependencies like GSI map to create dependencies between interrupt controller and devices. To support doing that, the function which creates the dependency, is refactored bit and made public so that dependency can be added from outside of scan.c as well. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 86 ++++++++++++++++++++++------------------- include/acpi/acpi_bus.h | 1 + 2 files changed, 48 insertions(+), 39 deletions(-) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index b325b297bf77..66038fc731fb 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2004,6 +2004,49 @@ void acpi_scan_hotplug_enabled(struct acpi_hotplug_p= rofile *hotplug, bool val) mutex_unlock(&acpi_scan_lock); } =20 +int acpi_scan_add_dep(acpi_handle handle, struct acpi_handle_list *dep_dev= ices) +{ + u32 count; + int i; + + for (count =3D 0, i =3D 0; i < dep_devices->count; i++) { + struct acpi_device_info *info; + struct acpi_dep_data *dep; + bool skip, honor_dep; + acpi_status status; + + status =3D acpi_get_object_info(dep_devices->handles[i], &info); + if (ACPI_FAILURE(status)) { + acpi_handle_debug(handle, "Error reading _DEP device info\n"); + continue; + } + + skip =3D acpi_info_matches_ids(info, acpi_ignore_dep_ids); + honor_dep =3D acpi_info_matches_ids(info, acpi_honor_dep_ids); + kfree(info); + + if (skip) + continue; + + dep =3D kzalloc(sizeof(*dep), GFP_KERNEL); + if (!dep) + continue; + + count++; + + dep->supplier =3D dep_devices->handles[i]; + dep->consumer =3D handle; + dep->honor_dep =3D honor_dep; + + mutex_lock(&acpi_dep_list_lock); + list_add_tail(&dep->node, &acpi_dep_list); + mutex_unlock(&acpi_dep_list_lock); + } + + acpi_handle_list_free(dep_devices); + return count; +} + static void acpi_scan_init_hotplug(struct acpi_device *adev) { struct acpi_hardware_id *hwid; @@ -2026,8 +2069,7 @@ static void acpi_scan_init_hotplug(struct acpi_device= *adev) static u32 acpi_scan_check_dep(acpi_handle handle) { struct acpi_handle_list dep_devices; - u32 count; - int i; + u32 count =3D 0; =20 /* * Check for _HID here to avoid deferring the enumeration of: @@ -2036,48 +2078,14 @@ static u32 acpi_scan_check_dep(acpi_handle handle) * Still, checking for _HID catches more then just these cases ... */ if (!acpi_has_method(handle, "_DEP") || !acpi_has_method(handle, "_HID")) - return 0; + return count; =20 if (!acpi_evaluate_reference(handle, "_DEP", NULL, &dep_devices)) { acpi_handle_debug(handle, "Failed to evaluate _DEP.\n"); - return 0; + return count; } =20 - for (count =3D 0, i =3D 0; i < dep_devices.count; i++) { - struct acpi_device_info *info; - struct acpi_dep_data *dep; - bool skip, honor_dep; - acpi_status status; - - status =3D acpi_get_object_info(dep_devices.handles[i], &info); - if (ACPI_FAILURE(status)) { - acpi_handle_debug(handle, "Error reading _DEP device info\n"); - continue; - } - - skip =3D acpi_info_matches_ids(info, acpi_ignore_dep_ids); - honor_dep =3D acpi_info_matches_ids(info, acpi_honor_dep_ids); - kfree(info); - - if (skip) - continue; - - dep =3D kzalloc(sizeof(*dep), GFP_KERNEL); - if (!dep) - continue; - - count++; - - dep->supplier =3D dep_devices.handles[i]; - dep->consumer =3D handle; - dep->honor_dep =3D honor_dep; - - mutex_lock(&acpi_dep_list_lock); - list_add_tail(&dep->node , &acpi_dep_list); - mutex_unlock(&acpi_dep_list_lock); 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Sat, 01 Jun 2024 08:04:56 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:04:56 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Date: Sat, 1 Jun 2024 20:33:59 +0530 Message-Id: <20240601150411.1929783-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V PLIC and APLIC will have dependency from devices using GSI. So, add these devices to the honor list. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 66038fc731fb..6f3152170084 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -832,6 +832,8 @@ static const char * const acpi_honor_dep_ids[] =3D { "INTC1095", /* IVSC (ADL) driver must be loaded to allow i2c access to ca= mera sensors */ "INTC100A", /* IVSC (RPL) driver must be loaded to allow i2c access to ca= mera sensors */ "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to ca= mera sensors */ + "RSCV0001", /* RISC-V PLIC */ + "RSCV0002", /* RISC-V APLIC */ NULL }; =20 --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-il1-f169.google.com (mail-il1-f169.google.com [209.85.166.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB422152E19 for ; Sat, 1 Jun 2024 15:05:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717254306; cv=none; b=AsI2bQlIBfBzo6Ni6FghJgGxeOBIAs2kEpmao8l+cv+XLYzpAkhQrjCSMsZBv21AXirdqdJrBVK2XJ/bJ6hs7+cnqA1cFcvb6FPdHclHCBYnYccxlT+R1YSJ9Vjeevtkeufvzo+1gpf3WSzdlHnsEyuYlvcuMmqa9J+oyG4Klus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717254306; c=relaxed/simple; bh=gUZ5nlwTeV/W2GAxqRBkwnxWUnWQmkvoylnNCHneLXI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DGS6A9BVBBD+D1msMSFhXeQ43UjUA9kDxt0P6rva7r6vADIey/MgVnjhuM7juU5VghRZxY3bn3sIZ/n/Dzf73j78z6R5Lu3F9xubeCz3Yp4jqkfgwicpnYRlqWtToqKaWjWPtZPRmgNtEBb1o9h8lojGTdTMGfYAZHylYHvY5Bg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=IZuwQd/J; arc=none smtp.client-ip=209.85.166.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="IZuwQd/J" Received: by mail-il1-f169.google.com with SMTP id e9e14a558f8ab-3748aa28d0fso7433795ab.3 for ; Sat, 01 Jun 2024 08:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1717254304; x=1717859104; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z/CsLBy86VnyNo2isQPCT1WZPGBpvem+xh2ISHmLXVs=; b=IZuwQd/Jc+GX1RaooXAgCSZ9pqgw4oZRgMY7PlmedJT+SD8NwxL7xPHt6OK0tpAAW3 rDexKMV0YFVSma+weZAs8Q7TtIb1c3g3JFHjTZr6Gaz48ZrNq/6FQ8onugsLGv+04EcI KdK4Eg4gan9h9VIXW/ZIIskIN3Os6NfDCQ1nrssG0UUi+cqNUa/BQgeKveir1kJy4Rsd aGbVfGJglSfBxfSHCbu3BCV8F8nOIuo1mbPRBtSyavX3Dx0J7dj7CL4G/w+XsPYwkvwj rKTCyAn0TdPCLwIhArVi15PjrFK7q5Zykhr4ps1/xTexc8IINOA7tUIMdUziqNBAfsr6 VRmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717254304; x=1717859104; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z/CsLBy86VnyNo2isQPCT1WZPGBpvem+xh2ISHmLXVs=; b=lLS9wOLm8RbYxnBvDlANuqNG6iTCV9PxLSEGPXA2fDsF8F5w7p2hW38WpuH3LwceB5 kYN0BQV+FQaYLmVJiYD08myGoNByuBScS+oqmuQDv2AveXK2Xki8RiBCJa9OuQG0KxH0 Ci21q8AlosXnifG0+KnvmgsTrUvMBwzGwh0GoWvNE4HnglcUc5OccQ7DBJ9BN7Dkly5Q s/GkdkXrummuJOThuKy7I7kGyZ8QIcv2g71m6gqbXHIxMDMHEWkPeREy4dFeT6Dorw/t ROvJfUxstk2jHL7Ca3hWI/DZPGT6AyVggZQm9qm6VPLoXe7MLnREVRnVswaOr2L1KxoQ rATA== X-Forwarded-Encrypted: i=1; AJvYcCUwxDNRJRJUTzNX21yEgG9FQEGJh0GSAiGMcxvIQOyoM5eghVo570den9rXhESwSq/+bi59YqKOBjx9/N0gHfqYwpfbwWD9mFIqhJQl X-Gm-Message-State: AOJu0YxlVK28moYPbheq77y84wK8Om2sjU5/e9Sg1ktR0thPN4a2yzXr rNZ6485HENfH8x8G00Re4Ex0625lCpI8WDqtuNAx7sR1oym2v3hr/Q3WDSW1OHk= X-Google-Smtp-Source: AGHT+IF3OVauvlGO1nxR3XDABScTnbIuW6VxwtguVbngDcxS9MthKKzwc9GQNZ47KhPfz+utEVmKGg== X-Received: by 2002:a05:6e02:1a63:b0:374:5672:6791 with SMTP id e9e14a558f8ab-3748b97ee00mr54534805ab.8.1717254303897; Sat, 01 Jun 2024 08:05:03 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:03 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 06/17] ACPI: scan: Define weak function to populate dependencies Date: Sat, 1 Jun 2024 20:34:00 +0530 Message-Id: <20240601150411.1929783-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some architectures like RISC-V need to add dependencies without explicit _DEP. Define a weak function which can be implemented by the architecture. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 11 +++++++++++ include/acpi/acpi_bus.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 6f3152170084..918e71fc54cb 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2068,11 +2068,22 @@ static void acpi_scan_init_hotplug(struct acpi_devi= ce *adev) } } =20 +u32 __weak arch_acpi_add_auto_dep(acpi_handle handle) { return 0; } + static u32 acpi_scan_check_dep(acpi_handle handle) { struct acpi_handle_list dep_devices; u32 count =3D 0; =20 + /* + * Some architectures like RISC-V need to add dependencies for + * all devices which use GSI to the interrupt controller so that + * interrupt controller is probed before any of those devices. + * Instead of mandating _DEP on all the devices, detect the + * dependency and add automatically. + */ + count +=3D arch_acpi_add_auto_dep(handle); + /* * Check for _HID here to avoid deferring the enumeration of: * 1. PCI devices. diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 28a9b87c23fa..5fba4075d764 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -994,6 +994,7 @@ static inline void acpi_put_acpi_dev(struct acpi_device= *adev) int acpi_wait_for_acpi_ipmi(void); =20 int acpi_scan_add_dep(acpi_handle handle, struct acpi_handle_list *dep_dev= ices); +u32 arch_acpi_add_auto_dep(acpi_handle handle); #else /* CONFIG_ACPI */ =20 static inline int register_acpi_bus_type(void *bus) { return 0; } --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF47F1534EA for ; Sat, 1 Jun 2024 15:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717254312; cv=none; b=pN/HNEU9TxISCwiQ1LqRghvCbbxXdFQ4UWF0C/LxC5mCEUg3Ayl/1zr7wDb/FCc91evtPkVIgywS5YvSsGYXDNMG+TsIFcwCeM/+mDzfmqSzWr7n9BU1KYUOV1oib8Rr3KIVyvj0P7yuE//7NeqG9APA0Ek51i1uwA515o/EtFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717254312; c=relaxed/simple; bh=MS3pYncxgjtaz9tqccBN5FjLqLx8afnodSL+vXxHJSE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Qh07ELgwGrCCAPNb3BoL2bt0+qjeelXxIblfGsVuZRwhDuvXQ8PdVYqpuzmOE0JaA+flp543d3VTX1jvG7r8h7z6um8Dlh3DCukV2bj+T/fvbf6ooAWoEqiL9oxW+wpCdUhyTPK0PQPI1jSUjVM78UWmw8qMWRGZ9/fKCMduEDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Kjz2fM/L; arc=none smtp.client-ip=209.85.216.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Kjz2fM/L" Received: by mail-pj1-f54.google.com with SMTP id 98e67ed59e1d1-2c1e6fcb2f1so1139053a91.1 for ; Sat, 01 Jun 2024 08:05:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1717254311; x=1717859111; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B4M/mYQsiafz27308Ygh9HE2jpjvmPpXdwbsDZU0p4U=; b=Kjz2fM/LXEMXrWPgy3sD+Wi5PZRi93ASTcmKlDmLh3ZGN0oPWD1oeZdpMNCKrd2QMN MrhFdYfjFFM3RS6qtHorNm7M7CfuypUyrkZpnY3FD68PI//gs0qtSjwEAPQXu0Ng/2sw nOFWvBQcnJVJyLituErWYCrzA8IYz68IyEoyckiu1lQaWO6JaHD5zABHo1wuAil2TJ2K 04h89Uk4D+8+/SfPXscz1RzEE5gIDVeJVqVs6+Fy7FYIIKcTr47CPgOPe/ZIxpHzlKWT 1KQw3Z6ESHZu/i9lNKHViesBqeju7+vOBZFy5DfS5K7KzhQavvh60k5MvtXtsM95WffU SwDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717254311; x=1717859111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B4M/mYQsiafz27308Ygh9HE2jpjvmPpXdwbsDZU0p4U=; b=MBFrv6Q1jGBSCyEfW10oL/4wPMz+oR/ReoWIN6UR5boBG7qjy8iAYUnobadDyZXB/i 7nY6AHyd6bfCvJr2hCZJjrgzBTRmaUUCEMJPq8xwDpAAKSFQJVupeQyr1McW1/L6LG2w ur9/QWiedhnkKovGJpHVtjbThkxJ89WdV3owDq2M4Jy8eK8LBA3XFqxWynRtUU4UgqzH mJkUH5W22mWN5IGyNaIedd3OE68Qi+SPHt6Li4etAXML0SNfWrIG+AXno3NcqONyy1iL rs1ot+QlzQTrJjhyi6w/Fqdh3S0xt8xan72a02Sz/RsK3AnFMhoroAieObBPkYEMvNtp AJfw== X-Forwarded-Encrypted: i=1; AJvYcCUI/wnr1o/VLaHUIKyUGr5P0CIgkF4PnbY5GPtAVyhumEgXBAXNfq+VVcBtvldu2TFGS/YSJtOUH4lOOFqf9w40gnoBMBKIPyq7Tf0j X-Gm-Message-State: AOJu0YxFOtucZCeYn+UXLDleVLXNKUg2BsUtc/kPP4YorUijZhw1JxVE 7tI6uFmYNCa4zDls22tCMYhuYQKh1qJG+b0aFIOTmBWQujFcu/HGxXWpcVf3svY= X-Google-Smtp-Source: AGHT+IH8CUtTilyts1LQmIwjtfiqczpJ90H7WVJzan1b3vUk1N8n0tjhHWRHLwYTOBrAh4nFvjs79Q== X-Received: by 2002:a17:90b:1bcd:b0:2c2:a2a:6151 with SMTP id 98e67ed59e1d1-2c20a2a631emr797621a91.39.1717254310835; Sat, 01 Jun 2024 08:05:10 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:10 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Date: Sat, 1 Jun 2024 20:34:01 +0530 Message-Id: <20240601150411.1929783-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 8d0710ade8c6..d5286e39668e 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1201,6 +1201,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_LPIC: message =3D "LPIC"; break; + case ACPI_IRQ_MODEL_RINTC: + message =3D "RINTC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 0c6d9539f737..3dd67ee09c39 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -107,6 +107,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_PLATFORM, ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, + ACPI_IRQ_MODEL_RINTC, ACPI_IRQ_MODEL_COUNT }; =20 --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-il1-f174.google.com (mail-il1-f174.google.com [209.85.166.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BE71534EA for ; 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Sat, 01 Jun 2024 08:05:17 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:17 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 08/17] ACPI: pci_link: Clear the dependencies after probe Date: Sat, 1 Jun 2024 20:34:02 +0530 Message-Id: <20240601150411.1929783-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V platforms need to use dependencies between PCI host bridge, Link devices and the interrupt controllers to ensure probe order. The dependency is like below. Interrupt controller <-- Link Device <-- PCI Host bridge. If there is no dependency added between Link device and PCI Host Bridge, then the PCI end points can get probed prior to link device, unable to get mapping for INTx. So, add the link device's HID to dependency honor list and also clear it after its probe. Signed-off-by: Sunil V L --- drivers/acpi/pci_link.c | 2 ++ drivers/acpi/scan.c | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c index aa1038b8aec4..b727db968f33 100644 --- a/drivers/acpi/pci_link.c +++ b/drivers/acpi/pci_link.c @@ -748,6 +748,8 @@ static int acpi_pci_link_add(struct acpi_device *device, if (result) kfree(link); =20 + acpi_dev_clear_dependencies(device); + return result < 0 ? result : 1; } =20 diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 918e71fc54cb..0280056a326b 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -834,6 +834,7 @@ static const char * const acpi_honor_dep_ids[] =3D { "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to ca= mera sensors */ "RSCV0001", /* RISC-V PLIC */ "RSCV0002", /* RISC-V APLIC */ + "PNP0C0F", /* PCI Link Device */ NULL }; =20 --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-il1-f177.google.com (mail-il1-f177.google.com [209.85.166.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36185154434 for ; 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Sat, 01 Jun 2024 08:05:25 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:24 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 09/17] ACPI: RISC-V: Implement PCI related functionality Date: Sat, 1 Jun 2024 20:34:03 +0530 Message-Id: <20240601150411.1929783-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the dummy implementation for PCI related functions with actual implementation. This needs ECAM and MCFG CONFIG options to be enabled for RISC-V. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 2 ++ arch/riscv/kernel/acpi.c | 33 +++++++++++++++------------------ drivers/pci/pci-acpi.c | 2 +- 3 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b94176e25be1..f143fbeea572 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION @@ -181,6 +182,7 @@ config RISCV select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI + select PCI_ECAM if (ACPI && PCI) select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL select RISCV_APLIC diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..41aa77c8484b 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address p= hys, acpi_size size) #ifdef CONFIG_PCI =20 /* - * These interfaces are defined just to enable building ACPI core. - * TODO: Update it with actual implementation when external interrupt - * controller support is added in RISC-V ACPI. + * raw_pci_read/write - Platform-specific PCI config space access. */ -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 *val) +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) { - return PCIBIOS_DEVICE_NOT_FOUND; + struct pci_bus *b =3D pci_find_bus(domain, bus); + + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->read(b, devfn, reg, len, val); } =20 -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devf= n, - int reg, int len, u32 val) +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) { - return PCIBIOS_DEVICE_NOT_FOUND; + struct pci_bus *b =3D pci_find_bus(domain, bus); + + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->write(b, devfn, reg, len, val); } =20 -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - return -1; -} - -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - return NULL; -} #endif /* CONFIG_PCI */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index e8d84fa435da..b5892d0fa68c 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void) } arch_initcall(acpi_pci_init); =20 -#if defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) =20 /* * Try to assign the IRQ number when probing a new device --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BB3D154434 for ; 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Sat, 01 Jun 2024 08:05:32 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:31 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Date: Sat, 1 Jun 2024 20:34:04 +0530 Message-Id: <20240601150411.1929783-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ACPI MADT entries for interrupt controllers don't have a way to describe the hierarchy. However, the hierarchy is known to the architecture and on RISC-V platforms, the MADT sub table types are ordered in the incremental order from the root controller which is RINTC. So, add architecture function for RISC-V to reorder the interrupt controller probing as per the hierarchy as below. Signed-off-by: Sunil V L --- drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/irq.c diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 877de00d1b50..a96fdf1e2cb8 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o init.o +obj-y +=3D rhct.o init.o irq.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c new file mode 100644 index 000000000000..f56e103a501f --- /dev/null +++ b/drivers/acpi/riscv/irq.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023-2024, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include + +static int irqchip_cmp_func(const void *in0, const void *in1) +{ + struct acpi_probe_entry *elem0 =3D (struct acpi_probe_entry *)in0; + struct acpi_probe_entry *elem1 =3D (struct acpi_probe_entry *)in1; + + return (elem0->type > elem1->type) - (elem0->type < elem1->type); +} + +/* + * RISC-V irqchips in MADT of ACPI spec are defined in the same order how + * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any + * order, this arch function will reorder the probe functions as per the + * required order for the architecture. + */ +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) +{ + struct acpi_probe_entry *ape =3D ap_head; + + if (nr =3D=3D 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) + return; + sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); +} --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 440A2153580 for ; Sat, 1 Jun 2024 15:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717254341; cv=none; b=jnirTq39r7CHXcC06GRWqwedtCilMnredyoNRUoEZWyMoib51GXOeF7jjQLMZyMj9aDMYEi+kG8CZobE7dJJ0IYRG2kiD4wCuCuBNwAIlq/65NCdI7z+g2S2F7BChSywZH9Lz9Qv+HdZQtGS2M/pDpEiOATrqNhQgIPU2TVBsdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717254341; c=relaxed/simple; bh=cR3uveiGxGLJmRft6U2PQ0/OsQCFgHzkLGPMHFEaI+Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pSYcPlxargftJ8i4dgqVLWqp/89mnXjBmoue79yrmkjWv6BPnFYYGwiVBptKgtNnSs+ys3eAHMFtNtj4com+V/fxtoNT5tWMjWMBCdQqWbCcovPadOAJPdmkljloZj/NUWr/Cu1FqlvnUklZOTb+QNndQ6PP7yvzBr19Z7IvSwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=PjAamX+f; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="PjAamX+f" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-702621d8725so62539b3a.0 for ; Sat, 01 Jun 2024 08:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1717254339; x=1717859139; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dz2b5NSEn3co4GBYyIFhq4o1B5yNhLUdwhxGlUjO5R4=; b=PjAamX+f7yZkKYMIE7m0+QyPkZFUFlLQ3FX7MhvGkclVykmuXPcOssfG37+H/nvZvg 5K5Tz+DQ7LF5QuSl5bcSxdvGnrX/QXJaoFYAjT6HRAE082prGc239qS4D2DNq2WLJHcr yf+OeyllsIb6ME49oShNrbbuKoQJ7D617x3wKlT0qFows/zTaSQkU4jX5piN2bZz7Rhh y8XNPa/+yBc5qwv2gA1677xeFytOacIUQ9Panmc6ff6WW6dOgUjpKKopQdL26nJ6x02j pvrzC8VLezFS6eFzZN6uJSgcu2gADGZLT1O7pjCHN8ykTk1qBWey54gkRI4smHg4dlN+ bGpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717254339; x=1717859139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dz2b5NSEn3co4GBYyIFhq4o1B5yNhLUdwhxGlUjO5R4=; b=jXisIdAMgTpRJFvhAU6NqBd/gtlTg0gEMTtvCsrjjdLsFtPdkoelY47anykre5ETfD ellkZCpGTEjKDHglM8FLy6w8FhzagTAmQrShY2+WYSBSqpKcYjtlu1hy/Dn+ya5MHP3J uUoaF1FdymsmAsBiS5MDjOtDlnmW+z6w3iePgA0MRrbBU5MY0d3Qyo/ll0Gu2pCmeZYu 5BwMm7N83G9ReJzoKXIenUkmQmfOO3cDsnjdODF1ZMv/uZn1TA90AiFWCqYk6B1Cj2kU lX0jfO80DyXtzHJ9g6pY0NH654imFO5tpGw7Z3j8MAM0h6uPvuZ1Wcooh9Z5zozPqquf 2wlQ== X-Forwarded-Encrypted: i=1; AJvYcCVhIjroDHopTjo8IsmHcp8Mvoh1Im1xJXQIXimWPVICEavmFZM6CcAEgy7bMVrfE9wp935XTWvvqVYw5lx85ii8pfjTP4qosUO3zUdB X-Gm-Message-State: AOJu0Yw6LwJvAt+CpSLiiGKHw42jxDxE0zR0Myn48phXYvSsm5q8eI1S Qx97ll3H3z1FN7B5YqS/eJus7GXRSo2kYRvRUvS1rDlNqrMAX/6wnpGkpSY3LrE= X-Google-Smtp-Source: AGHT+IFi9FvR07K+9EvB/LtbP5RxfWdx62HcMAj5Tgp+bEEJtSdzuKB0A31tUE7N74MPsHLQ+KB8vQ== X-Received: by 2002:a05:6a21:3288:b0:1a8:2cc0:290a with SMTP id adf61e73a8af0-1b26f185b75mr5513828637.30.1717254339312; Sat, 01 Jun 2024 08:05:39 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:38 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 11/17] ACPI: RISC-V: Initialize GSI mapping structures Date: Sat, 1 Jun 2024 20:34:05 +0530 Message-Id: <20240601150411.1929783-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V has PLIC and APLIC in MADT as well as namespace devices. Initialize the list of those structures using MADT and namespace devices to create mapping between the ACPI handle and the GSI ranges. This will be used later to add dependencies. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 22 ++++++ drivers/acpi/riscv/init.c | 2 + drivers/acpi/riscv/init.h | 4 + drivers/acpi/riscv/irq.c | 142 +++++++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8e10a94430a2..44a0b128c602 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -16,4 +16,26 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn= )(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); =20 +#ifdef CONFIG_ACPI + +enum riscv_irqchip_type { + ACPI_RISCV_IRQCHIP_INTC =3D 0x00, + ACPI_RISCV_IRQCHIP_IMSIC =3D 0x01, + ACPI_RISCV_IRQCHIP_PLIC =3D 0x02, + ACPI_RISCV_IRQCHIP_APLIC =3D 0x03, +}; + +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs); +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi); + +#else +static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs) +{ + return 0; +} + +#endif /* CONFIG_ACPI */ + #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index 5f7571143245..22db97f7a772 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ =20 #include +#include "init.h" =20 void __init acpi_riscv_init(void) { + riscv_acpi_init_gsi_mapping(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..0b9a07e4031f --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_init_gsi_mapping(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index f56e103a501f..0473428e8d1e 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -7,6 +7,21 @@ =20 #include #include +#include + +#include "init.h" + +struct riscv_ext_intc_list { + acpi_handle handle; + u32 gsi_base; + u32 nr_irqs; + u32 nr_idcs; + u32 id; + u32 type; + struct list_head list; +}; + +LIST_HEAD(ext_intc_list); =20 static int irqchip_cmp_func(const void *in0, const void *in1) { @@ -30,3 +45,130 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *a= p_head, int nr) return; sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); } + +static void riscv_acpi_update_gsi_handle(u32 gsi_base, acpi_handle handle) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (gsi_base =3D=3D ext_intc_element->gsi_base) { + ext_intc_element->handle =3D handle; + return; + } + } + + acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); +} + +int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, + u32 *id, u32 *nr_irqs, u32 *nr_idcs) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (ext_intc_element->handle =3D=3D ACPI_HANDLE_FWNODE(fwnode)) { + *gsi_base =3D ext_intc_element->gsi_base; + *id =3D ext_intc_element->id; + *nr_irqs =3D ext_intc_element->nr_irqs; + if (nr_idcs) + *nr_idcs =3D ext_intc_element->nr_idcs; + + return 0; + } + } + + return -ENODEV; +} + +struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct acpi_device *adev; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (gsi >=3D ext_intc_element->gsi_base && + gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) { + adev =3D acpi_fetch_acpi_dev(ext_intc_element->handle); + if (!adev) + return NULL; + + return acpi_fwnode_handle(adev); + } + } + + return NULL; +} + +static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, = u32 nr_idcs, + u32 id, u32 type) +{ + struct riscv_ext_intc_list *ext_intc_element; + + ext_intc_element =3D kzalloc(sizeof(*ext_intc_element), GFP_KERNEL); + if (!ext_intc_element) + return -ENOMEM; + + ext_intc_element->gsi_base =3D gsi_base; + ext_intc_element->nr_irqs =3D nr_irqs; + ext_intc_element->nr_idcs =3D nr_idcs; + ext_intc_element->id =3D id; + list_add_tail(&ext_intc_element->list, &ext_intc_list); + return 0; +} + +static acpi_status __init riscv_acpi_create_gsi_map(acpi_handle handle, u3= 2 level, + void *context, void **return_value) +{ + acpi_status status; + u64 gbase; + + if (!acpi_has_method(handle, "_GSB")) { + acpi_handle_err(handle, "_GSB method not found\n"); + return AE_OK; + } + + status =3D acpi_evaluate_integer(handle, "_GSB", NULL, &gbase); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to evaluate _GSB method\n"); + return AE_OK; + } + + riscv_acpi_update_gsi_handle((u32)gbase, handle); + return AE_OK; +} + +static int __init riscv_acpi_aplic_parse_madt(union acpi_subtable_headers = *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic =3D (struct acpi_madt_aplic *)header; + + return riscv_acpi_register_ext_intc(aplic->gsi_base, aplic->num_sources, = aplic->num_idcs, + aplic->id, ACPI_RISCV_IRQCHIP_APLIC); +} + +static int __init riscv_acpi_plic_parse_madt(union acpi_subtable_headers *= header, + const unsigned long end) +{ + struct acpi_madt_plic *plic =3D (struct acpi_madt_plic *)header; + + return riscv_acpi_register_ext_intc(plic->gsi_base, plic->num_irqs, 0, + plic->id, ACPI_RISCV_IRQCHIP_PLIC); +} + +void __init riscv_acpi_init_gsi_mapping(void) +{ + /* There can be either PLIC or APLIC */ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, riscv_acpi_plic_parse_madt= , 0) > 0) { + acpi_get_devices("RSCV0001", riscv_acpi_create_gsi_map, NULL, NULL); + return; + } + + if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_ma= dt, 0) > 0) + acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); +} --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03D11154C19 for ; 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Sat, 01 Jun 2024 08:05:46 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:45 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Date: Sat, 1 Jun 2024 20:34:06 +0530 Message-Id: <20240601150411.1929783-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V interrupt controllers for wired interrupts are platform devices and hence their driver will be probed late. Also, APLIC which is one such interrupt controller can not be probed early since it needs MSI services. This needs a probing order between the interrupt controller driver and the device drivers. _DEP is typically used to indicate such dependencies. However, the dependency may be already available like GSI mapping. Hence, instead of an explicit _DEP, architecture can find the implicit dependencies and add to the dependency list. For RISC-V, add the dependencies for below use cases. 1) For devices which has IRQ resource, find out the interrupt controller using GSI number map and add the dependency. 2) For PCI host bridges: a) If _PRT indicate PCI link devices, add dependency on the link device. b) If _PRT indicates GSI, find out the interrupt controller using GSI number map and add the dependency. Signed-off-by: Sunil V L --- drivers/acpi/riscv/irq.c | 155 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 0473428e8d1e..2878ae48131f 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -21,6 +21,12 @@ struct riscv_ext_intc_list { struct list_head list; }; =20 +struct acpi_irq_dep_ctx { + int rc; + unsigned int index; + acpi_handle handle; +}; + LIST_HEAD(ext_intc_list); =20 static int irqchip_cmp_func(const void *in0, const void *in1) @@ -62,6 +68,21 @@ static void riscv_acpi_update_gsi_handle(u32 gsi_base, a= cpi_handle handle) acpi_handle_err(handle, "failed to find the GSI mapping entry\n"); } =20 +static acpi_handle riscv_acpi_get_gsi_handle(u32 gsi) +{ + struct riscv_ext_intc_list *ext_intc_element; + struct list_head *i, *tmp; + + list_for_each_safe(i, tmp, &ext_intc_list) { + ext_intc_element =3D list_entry(i, struct riscv_ext_intc_list, list); + if (gsi >=3D ext_intc_element->gsi_base && + gsi < (ext_intc_element->gsi_base + ext_intc_element->nr_irqs)) + return ext_intc_element->handle; + } + + return NULL; +} + int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs) { @@ -172,3 +193,137 @@ void __init riscv_acpi_init_gsi_mapping(void) if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, riscv_acpi_aplic_parse_ma= dt, 0) > 0) acpi_get_devices("RSCV0002", riscv_acpi_create_gsi_map, NULL, NULL); } + +static acpi_status riscv_acpi_irq_get_parent(struct acpi_resource *ares, v= oid *context) +{ + struct acpi_irq_dep_ctx *ctx =3D context; + struct acpi_resource_irq *irq; + struct acpi_resource_extended_irq *eirq; + + switch (ares->type) { + case ACPI_RESOURCE_TYPE_IRQ: + irq =3D &ares->data.irq; + if (ctx->index >=3D irq->interrupt_count) { + ctx->index -=3D irq->interrupt_count; + return AE_OK; + } + ctx->handle =3D riscv_acpi_get_gsi_handle(irq->interrupts[ctx->index]); + return AE_CTRL_TERMINATE; + case ACPI_RESOURCE_TYPE_EXTENDED_IRQ: + eirq =3D &ares->data.extended_irq; + if (eirq->producer_consumer =3D=3D ACPI_PRODUCER) + return AE_OK; + + if (ctx->index >=3D eirq->interrupt_count) { + ctx->index -=3D eirq->interrupt_count; + return AE_OK; + } + + /* Support GSIs only */ + if (eirq->resource_source.string_length) + return AE_OK; + + ctx->handle =3D riscv_acpi_get_gsi_handle(eirq->interrupts[ctx->index]); + return AE_CTRL_TERMINATE; + } + + return AE_OK; +} + +static int riscv_acpi_irq_get_dep(acpi_handle handle, unsigned int index, = acpi_handle *gsi_handle) +{ + struct acpi_irq_dep_ctx ctx =3D {-EINVAL, index, NULL}; + + if (!gsi_handle) + return 0; + + acpi_walk_resources(handle, METHOD_NAME__CRS, riscv_acpi_irq_get_parent, = &ctx); + *gsi_handle =3D ctx.handle; + if (*gsi_handle) + return 1; + + return 0; +} + +static u32 riscv_acpi_add_prt_dep(acpi_handle handle) +{ + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct acpi_pci_routing_table *entry; + struct acpi_handle_list dep_devices; + acpi_handle gsi_handle; + acpi_handle link_handle; + acpi_status status; + u32 count =3D 0; + + status =3D acpi_get_irq_routing_table(handle, &buffer); + if (ACPI_FAILURE(status)) { + acpi_handle_err(handle, "failed to get IRQ routing table\n"); + kfree(buffer.pointer); + return 0; + } + + entry =3D buffer.pointer; + while (entry && (entry->length > 0)) { + if (entry->source[0]) { + acpi_get_handle(handle, entry->source, &link_handle); + dep_devices.count =3D 1; + dep_devices.handles =3D kcalloc(1, sizeof(*dep_devices.handles), GFP_KE= RNEL); + if (!dep_devices.handles) { + acpi_handle_err(handle, "failed to allocate memory\n"); + continue; + } + + dep_devices.handles[0] =3D link_handle; + count +=3D acpi_scan_add_dep(handle, &dep_devices); + } else { + gsi_handle =3D riscv_acpi_get_gsi_handle(entry->source_index); + dep_devices.count =3D 1; + dep_devices.handles =3D kcalloc(1, sizeof(*dep_devices.handles), GFP_KE= RNEL); + if (!dep_devices.handles) { + acpi_handle_err(handle, "failed to allocate memory\n"); + continue; + } + + dep_devices.handles[0] =3D gsi_handle; + count +=3D acpi_scan_add_dep(handle, &dep_devices); + } + + entry =3D (struct acpi_pci_routing_table *) + ((unsigned long)entry + entry->length); + } + + kfree(buffer.pointer); + return count; +} + +static u32 riscv_acpi_add_irq_dep(acpi_handle handle) +{ + struct acpi_handle_list dep_devices; + acpi_handle gsi_handle; + u32 count =3D 0; + int i; + + for (i =3D 0; + riscv_acpi_irq_get_dep(handle, i, &gsi_handle); + i++) { + dep_devices.count =3D 1; + dep_devices.handles =3D kcalloc(1, sizeof(*dep_devices.handles), GFP_KER= NEL); + if (!dep_devices.handles) { + acpi_handle_err(handle, "failed to allocate memory\n"); + continue; + } + + dep_devices.handles[0] =3D gsi_handle; + count +=3D acpi_scan_add_dep(handle, &dep_devices); + } + + return count; +} + +u32 arch_acpi_add_auto_dep(acpi_handle handle) +{ + if (acpi_has_method(handle, "_PRT")) + return riscv_acpi_add_prt_dep(handle); + + return riscv_acpi_add_irq_dep(handle); +} --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D14F1552EA for ; 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Sat, 01 Jun 2024 08:05:53 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:05:52 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 13/17] irqchip/riscv-intc: Add ACPI support for AIA Date: Sat, 1 Jun 2024 20:34:07 +0530 Message-Id: <20240601150411.1929783-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RINTC subtype structure in MADT also has information about other interrupt controllers. Save this information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 33 ++++++++++++ drivers/irqchip/irq-riscv-intc.c | 90 ++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 44a0b128c602..51d86f0b80d2 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,8 @@ =20 #include =20 +#define INVALID_CONTEXT UINT_MAX + void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); @@ -28,6 +30,11 @@ enum riscv_irqchip_type { int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base, u32 *id, u32 *nr_irqs, u32 *nr_idcs); struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi); +unsigned long acpi_get_intc_index_hartid(u32 index); +unsigned long acpi_get_ext_intc_parent_hartid(unsigned int plic_id, unsign= ed int ctxt_idx); +unsigned int acpi_get_plic_nr_contexts(unsigned int plic_id); +unsigned int acpi_get_plic_context(unsigned int plic_id, unsigned int ctxt= _idx); +int __init acpi_get_imsic_mmio_info(u32 index, struct resource *res); =20 #else static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u3= 2 *gsi_base, @@ -36,6 +43,32 @@ static inline int riscv_acpi_get_gsi_info(struct fwnode_= handle *fwnode, u32 *gsi return 0; } =20 +static inline unsigned long acpi_get_intc_index_hartid(u32 index) +{ + return INVALID_HARTID; +} + +static inline unsigned long acpi_get_ext_intc_parent_hartid(unsigned int p= lic_id, + unsigned int ctxt_idx) +{ + return INVALID_HARTID; +} + +static inline unsigned int acpi_get_plic_nr_contexts(unsigned int plic_id) +{ + return INVALID_CONTEXT; +} + +static inline unsigned int acpi_get_plic_context(unsigned int plic_id, uns= igned int ctxt_idx) +{ + return INVALID_CONTEXT; +} + +static inline int __init acpi_get_imsic_mmio_info(u32 index, struct resour= ce *res) +{ + return 0; +} + #endif /* CONFIG_ACPI */ =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 4f3a12383a1e..3c6494f1cb02 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -250,6 +250,85 @@ IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_int= c_init); =20 #ifdef CONFIG_ACPI =20 +struct rintc_data { + union { + u32 ext_intc_id; + struct { + u32 context_id : 16, + reserved : 8, + aplic_plic_id : 8; + }; + }; + unsigned long hart_id; + u64 imsic_addr; + u32 imsic_size; +}; + +static u32 nr_rintc; +static struct rintc_data *rintc_acpi_data[NR_CPUS]; + +#define for_each_matching_plic(_plic_id) \ + unsigned int _plic; \ + \ + for (_plic =3D 0; _plic < nr_rintc; _plic++) \ + if (rintc_acpi_data[_plic]->aplic_plic_id !=3D _plic_id) \ + continue; \ + else + +unsigned int acpi_get_plic_nr_contexts(unsigned int plic_id) +{ + unsigned int nctx =3D 0; + + for_each_matching_plic(plic_id) + nctx++; + + return nctx; +} + +static struct rintc_data *get_plic_context(unsigned int plic_id, unsigned = int ctxt_idx) +{ + unsigned int ctxt =3D 0; + + for_each_matching_plic(plic_id) { + if (ctxt =3D=3D ctxt_idx) + return rintc_acpi_data[_plic]; + + ctxt++; + } + + return NULL; +} + +unsigned long acpi_get_ext_intc_parent_hartid(unsigned int plic_id, unsign= ed int ctxt_idx) +{ + struct rintc_data *data =3D get_plic_context(plic_id, ctxt_idx); + + return data ? data->hart_id : INVALID_HARTID; +} + +unsigned int acpi_get_plic_context(unsigned int plic_id, unsigned int ctxt= _idx) +{ + struct rintc_data *data =3D get_plic_context(plic_id, ctxt_idx); + + return data ? data->context_id : INVALID_CONTEXT; +} + +unsigned long acpi_get_intc_index_hartid(u32 index) +{ + return index >=3D nr_rintc ? INVALID_HARTID : rintc_acpi_data[index]->har= t_id; +} + +int acpi_get_imsic_mmio_info(u32 index, struct resource *res) +{ + if (index >=3D nr_rintc) + return -1; + + res->start =3D rintc_acpi_data[index]->imsic_addr; + res->end =3D res->start + rintc_acpi_data[index]->imsic_size - 1; + res->flags =3D IORESOURCE_MEM; + return 0; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { @@ -258,6 +337,15 @@ static int __init riscv_intc_acpi_init(union acpi_subt= able_headers *header, int rc; =20 rintc =3D (struct acpi_madt_rintc *)header; + rintc_acpi_data[nr_rintc] =3D kzalloc(sizeof(*rintc_acpi_data[0]), GFP_KE= RNEL); + if (!rintc_acpi_data[nr_rintc]) + return -ENOMEM; + + rintc_acpi_data[nr_rintc]->ext_intc_id =3D rintc->ext_intc_id; + rintc_acpi_data[nr_rintc]->hart_id =3D rintc->hart_id; + rintc_acpi_data[nr_rintc]->imsic_addr =3D rintc->imsic_addr; + rintc_acpi_data[nr_rintc]->imsic_size =3D rintc->imsic_size; + nr_rintc++; =20 /* * The ACPI MADT will have one INTC for each CPU (or HART) @@ -277,6 +365,8 @@ static int __init riscv_intc_acpi_init(union acpi_subta= ble_headers *header, rc =3D riscv_intc_init_common(fn, &riscv_intc_chip); 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 14/17] irqchip/riscv-imsic-state: Create separate function for DT Date: Sat, 1 Jun 2024 20:34:08 +0530 Message-Id: <20240601150411.1929783-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While populating IMSIC global structure, many fields are initialized using DT properties. Make the code which uses DT properties as separate function so that it is easier to add ACPI support later. No functionality added/changed. Suggested-by: Thomas Gleixner Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-imsic-state.c | 97 ++++++++++++++----------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index 5479f872e62b..f9e70832863a 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -510,6 +510,60 @@ static int __init imsic_matrix_init(void) return 0; } =20 +static int __init imsic_populate_global_dt(struct fwnode_handle *fwnode, + struct imsic_global_config *global, + u32 *nr_parent_irqs) +{ + int rc; + + /* Find number of guest index bits in MSI address */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits", + &global->guest_index_bits); + if (rc) + global->guest_index_bits =3D 0; + + /* Find number of HART index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits", + &global->hart_index_bits); + if (rc) { + /* Assume default value */ + global->hart_index_bits =3D __fls(*nr_parent_irqs); + if (BIT(global->hart_index_bits) < *nr_parent_irqs) + global->hart_index_bits++; + } + + /* Find number of group index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits", + &global->group_index_bits); + if (rc) + global->group_index_bits =3D 0; + + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift", + &global->group_index_shift); + if (rc) + global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + + /* Find number of interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-ids", + &global->nr_ids); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", fwnode); + return rc; + } + + /* Find number of guest interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids", + &global->nr_guest_ids); + if (rc) + global->nr_guest_ids =3D global->nr_ids; + + return 0; +} + static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, u32 index, unsigned long *hartid) { @@ -578,50 +632,9 @@ static int __init imsic_parse_fwnode(struct fwnode_han= dle *fwnode, return -EINVAL; } =20 - /* Find number of guest index bits in MSI address */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits", - &global->guest_index_bits); + rc =3D imsic_populate_global_dt(fwnode, global, nr_parent_irqs); if (rc) - global->guest_index_bits =3D 0; - - /* Find number of HART index bits */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits", - &global->hart_index_bits); - if (rc) { - /* Assume default value */ - global->hart_index_bits =3D __fls(*nr_parent_irqs); - if (BIT(global->hart_index_bits) < *nr_parent_irqs) - global->hart_index_bits++; - } - - /* Find number of group index bits */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits", - &global->group_index_bits); - if (rc) - global->group_index_bits =3D 0; - - /* - * Find first bit position of group index. - * If not specified assumed the default APLIC-IMSIC configuration. - */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift", - &global->group_index_shift); - if (rc) - global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; - - /* Find number of interrupt identities */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-ids", - &global->nr_ids); - if (rc) { - pr_err("%pfwP: number of interrupt identities not found\n", fwnode); return rc; - } - - /* Find number of guest interrupt identities */ - rc =3D of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids", - &global->nr_guest_ids); - if (rc) - global->nr_guest_ids =3D global->nr_ids; =20 /* Sanity check guest index bits */ i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; --=20 2.40.1 From nobody Fri Feb 13 04:40:19 2026 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBC9F1534E5 for ; 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Sat, 01 Jun 2024 08:06:08 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:06:06 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 15/17] irqchip/riscv-imsic: Add ACPI support Date: Sat, 1 Jun 2024 20:34:09 +0530 Message-Id: <20240601150411.1929783-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V IMSIC interrupt controller provides IPI and MSI support. Currently, DT based drivers setup the IPI feature early during boot but defer setting up the MSI functionality. However, in ACPI systems, PCI subsystem is probed early and assume MSI controller is already setup. Hence, both IPI and MSI features need to be initialized early itself. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-imsic-early.c | 64 +++++++++++++++++++++- drivers/irqchip/irq-riscv-imsic-platform.c | 32 +++++++++-- drivers/irqchip/irq-riscv-imsic-state.c | 57 +++++++++++-------- drivers/irqchip/irq-riscv-imsic-state.h | 2 +- include/linux/irqchip/riscv-imsic.h | 9 +++ 5 files changed, 134 insertions(+), 30 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c index 4fbb37074d29..c5c2e6929a2f 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -5,13 +5,16 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include #include #include #include +#include #include +#include #include #include =20 @@ -182,7 +185,7 @@ static int __init imsic_early_dt_init(struct device_nod= e *node, struct device_no int rc; =20 /* Setup IMSIC state */ - rc =3D imsic_setup_state(fwnode); + rc =3D imsic_setup_state(fwnode, NULL); if (rc) { pr_err("%pfwP: failed to setup state (error %d)\n", fwnode, rc); return rc; @@ -199,3 +202,62 @@ static int __init imsic_early_dt_init(struct device_no= de *node, struct device_no } =20 IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); + +#ifdef CONFIG_ACPI + +static struct fwnode_handle *imsic_acpi_fwnode; + +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) +{ + return imsic_acpi_fwnode; +} + +static int __init imsic_early_acpi_init(union acpi_subtable_headers *heade= r, + const unsigned long end) +{ + struct acpi_madt_imsic *imsic =3D (struct acpi_madt_imsic *)header; + int rc; + + imsic_acpi_fwnode =3D irq_domain_alloc_named_fwnode("imsic"); + if (!imsic_acpi_fwnode) { + pr_err("unable to allocate IMSIC FW node\n"); + return -ENOMEM; + } + + /* Setup IMSIC state */ + rc =3D imsic_setup_state(imsic_acpi_fwnode, imsic); + if (rc) { + pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, r= c); + return rc; + } + + /* Do early setup of IMSIC state and IPIs */ + rc =3D imsic_early_probe(imsic_acpi_fwnode); + if (rc) { + irq_domain_free_fwnode(imsic_acpi_fwnode); + imsic_acpi_fwnode =3D NULL; + return rc; + } + + rc =3D imsic_platform_acpi_probe(imsic_acpi_fwnode); + +#ifdef CONFIG_PCI + if (!rc) + pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode); +#endif + + if (rc) + pr_err("%pfwP: failed to register IMSIC for MSI functionality (error %d)= \n", + imsic_acpi_fwnode, rc); + + /* + * Even if imsic_platform_acpi_probe() fails, the IPI part of IMSIC can + * continue to work. So, no need to return failure. This is similar to + * DT where IPI works but MSI probe fails for some reason. + */ + return 0; +} + +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL, + 1, imsic_early_acpi_init); +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 11723a763c10..64905e6f52d7 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -5,6 +5,7 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -348,18 +349,37 @@ int imsic_irqdomain_init(void) return 0; } =20 -static int imsic_platform_probe(struct platform_device *pdev) +static int imsic_platform_probe_common(struct fwnode_handle *fwnode) { - struct device *dev =3D &pdev->dev; - - if (imsic && imsic->fwnode !=3D dev->fwnode) { - dev_err(dev, "fwnode mismatch\n"); + if (imsic && imsic->fwnode !=3D fwnode) { + pr_err("%pfwP: fwnode mismatch\n", fwnode); return -ENODEV; } =20 return imsic_irqdomain_init(); } =20 +static int imsic_platform_dt_probe(struct platform_device *pdev) +{ + return imsic_platform_probe_common(pdev->dev.fwnode); +} + +#ifdef CONFIG_ACPI + +/* + * On ACPI based systems, PCI enumeration happens early during boot in + * acpi_scan_init(). PCI enumeration expects MSI domain setup before + * it calls pci_set_msi_domain(). Hence, unlike in DT where + * imsic-platform drive probe happens late during boot, ACPI based + * systems need to setup the MSI domain early. + */ +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode) +{ + return imsic_platform_probe_common(fwnode); +} + +#endif + static const struct of_device_id imsic_platform_match[] =3D { { .compatible =3D "riscv,imsics" }, {} @@ -370,6 +390,6 @@ static struct platform_driver imsic_platform_driver =3D= { .name =3D "riscv-imsic", .of_match_table =3D imsic_platform_match, }, - .probe =3D imsic_platform_probe, + .probe =3D imsic_platform_dt_probe, }; builtin_platform_driver(imsic_platform_driver); diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index f9e70832863a..73faa64bffda 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -5,6 +5,7 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -564,18 +565,36 @@ static int __init imsic_populate_global_dt(struct fwn= ode_handle *fwnode, return 0; } =20 +static int __init imsic_populate_global_acpi(struct fwnode_handle *fwnode, + struct imsic_global_config *global, + u32 *nr_parent_irqs, void *opaque) +{ + struct acpi_madt_imsic *imsic =3D (struct acpi_madt_imsic *)opaque; + + global->guest_index_bits =3D imsic->guest_index_bits; + global->hart_index_bits =3D imsic->hart_index_bits; + global->group_index_bits =3D imsic->group_index_bits; + global->group_index_shift =3D imsic->group_index_shift; + global->nr_ids =3D imsic->num_ids; + global->nr_guest_ids =3D imsic->num_guest_ids; + return 0; +} + static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, u32 index, unsigned long *hartid) { struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(fwnode)) - return -EINVAL; + if (!is_of_node(fwnode)) { + if (hartid) + *hartid =3D acpi_get_intc_index_hartid(index); + + if (!hartid || (*hartid =3D=3D INVALID_HARTID)) + return -EINVAL; + + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(fwnode), index, &parent); if (rc) @@ -594,12 +613,8 @@ static int __init imsic_get_parent_hartid(struct fwnod= e_handle *fwnode, static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, u32 index, struct resource *res) { - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_imsic_mmio_info(index, res); =20 return of_address_to_resource(to_of_node(fwnode), index, res); } @@ -607,20 +622,14 @@ static int __init imsic_get_mmio_resource(struct fwno= de_handle *fwnode, static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, - u32 *nr_mmios) + u32 *nr_mmios, + void *opaque) { unsigned long hartid; struct resource res; int rc; u32 i; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(fwnode)) - return -EINVAL; - *nr_parent_irqs =3D 0; *nr_mmios =3D 0; =20 @@ -632,7 +641,11 @@ static int __init imsic_parse_fwnode(struct fwnode_han= dle *fwnode, return -EINVAL; } =20 - rc =3D imsic_populate_global_dt(fwnode, global, nr_parent_irqs); + if (is_of_node(fwnode)) + rc =3D imsic_populate_global_dt(fwnode, global, nr_parent_irqs); + else + rc =3D imsic_populate_global_acpi(fwnode, global, nr_parent_irqs, opaque= ); + if (rc) return rc; =20 @@ -701,7 +714,7 @@ static int __init imsic_parse_fwnode(struct fwnode_hand= le *fwnode, return 0; } =20 -int __init imsic_setup_state(struct fwnode_handle *fwnode) +int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) { u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers =3D 0; struct imsic_global_config *global; @@ -742,7 +755,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwno= de) } =20 /* Parse IMSIC fwnode */ - rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios); + rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios, opa= que); if (rc) goto out_free_local; =20 diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index 5ae2f69b035b..391e44280827 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -102,7 +102,7 @@ void imsic_vector_debug_show_summary(struct seq_file *m= , int ind); =20 void imsic_state_online(void); void imsic_state_offline(void); -int imsic_setup_state(struct fwnode_handle *fwnode); +int imsic_setup_state(struct fwnode_handle *fwnode, void *opaque); int imsic_irqdomain_init(void); =20 #endif diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index faf0b800b1b0..7494952c5518 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -8,6 +8,8 @@ =20 #include #include +#include +#include #include =20 #define IMSIC_MMIO_PAGE_SHIFT 12 @@ -84,4 +86,11 @@ static inline const struct imsic_global_config *imsic_ge= t_global_config(void) =20 #endif =20 +#ifdef CONFIG_ACPI +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode); 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Sat, 01 Jun 2024 08:06:14 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 16/17] irqchip/riscv-aplic: Add ACPI support Date: Sat, 1 Jun 2024 20:34:10 +0530 Message-Id: <20240601150411.1929783-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ACPI support in APLIC drivers. Use the mapping created early during boot to get the details about the APLIC. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-aplic-direct.c | 22 +++++--- drivers/irqchip/irq-riscv-aplic-main.c | 68 ++++++++++++++++-------- drivers/irqchip/irq-riscv-aplic-main.h | 1 + drivers/irqchip/irq-riscv-aplic-msi.c | 9 +++- 4 files changed, 68 insertions(+), 32 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq= -riscv-aplic-direct.c index 4a3ffe856d6c..34540a0ca4da 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -4,6 +4,7 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ =20 +#include #include #include #include @@ -189,17 +190,22 @@ static int aplic_direct_starting_cpu(unsigned int cpu) } =20 static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, - u32 *parent_hwirq, unsigned long *parent_hartid) + u32 *parent_hwirq, unsigned long *parent_hartid, + struct aplic_priv *priv) { struct of_phandle_args parent; + unsigned long hartid; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + hartid =3D acpi_get_ext_intc_parent_hartid(priv->id, index); + if (hartid =3D=3D INVALID_HARTID) + return -ENODEV; + + *parent_hartid =3D hartid; + *parent_hwirq =3D RV_IRQ_EXT; + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(dev->fwnode), index, &parent); if (rc) @@ -237,7 +243,7 @@ int aplic_direct_setup(struct device *dev, void __iomem= *regs) /* Setup per-CPU IDC and target CPU mask */ current_cpu =3D get_cpu(); for (i =3D 0; i < priv->nr_idcs; i++) { - rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid); + rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid, priv); if (rc) { dev_warn(dev, "parent irq for IDC%d not found\n", i); continue; diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-r= iscv-aplic-main.c index 774a0c97fdab..c1fd328ddf7d 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.c +++ b/drivers/irqchip/irq-riscv-aplic-main.c @@ -4,8 +4,10 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ =20 +#include #include #include +#include #include #include #include @@ -125,39 +127,50 @@ static void aplic_init_hw_irqs(struct aplic_priv *pri= v) writel(0, priv->regs + APLIC_DOMAINCFG); } =20 +#ifdef CONFIG_ACPI +static const struct acpi_device_id aplic_acpi_match[] =3D { + { "RSCV0002", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, aplic_acpi_match); + +#endif + int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __i= omem *regs) { struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; - /* Save device pointer and register base */ priv->dev =3D dev; priv->regs =3D regs; =20 - /* Find out number of interrupt sources */ - rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,num-sources", - &priv->nr_irqs); - if (rc) { - dev_err(dev, "failed to get number of interrupt sources\n"); - return rc; - } + if (is_of_node(dev->fwnode)) { + /* Find out number of interrupt sources */ + rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,num-sources", + &priv->nr_irqs); + if (rc) { + dev_err(dev, "failed to get number of interrupt sources\n"); + return rc; + } =20 - /* - * Find out number of IDCs based on parent interrupts - * - * If "msi-parent" property is present then we ignore the - * APLIC IDCs which forces the APLIC driver to use MSI mode. - */ - if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { - while (!of_irq_parse_one(to_of_node(dev->fwnode), priv->nr_idcs, &parent= )) - priv->nr_idcs++; + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { + while (!of_irq_parse_one(to_of_node(dev->fwnode), priv->nr_idcs, &paren= t)) + priv->nr_idcs++; + } + } else { + rc =3D riscv_acpi_get_gsi_info(dev->fwnode, &priv->gsi_base, &priv->id, + &priv->nr_irqs, &priv->nr_idcs); + if (rc) { + dev_err(dev, "failed to find GSI mapping\n"); + return rc; + } } =20 /* Setup initial state APLIC interrupts */ @@ -186,6 +199,9 @@ static int aplic_probe(struct platform_device *pdev) */ if (is_of_node(dev->fwnode)) msi_mode =3D of_property_present(to_of_node(dev->fwnode), "msi-parent"); + else + msi_mode =3D imsic_acpi_get_fwnode(NULL) ? 1 : 0; + if (msi_mode) rc =3D aplic_msi_setup(dev, regs); else @@ -193,6 +209,11 @@ static int aplic_probe(struct platform_device *pdev) if (rc) dev_err(dev, "failed to setup APLIC in %s mode\n", msi_mode ? "MSI" : "d= irect"); =20 +#ifdef CONFIG_ACPI + if (!acpi_disabled) + acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); +#endif + return rc; } =20 @@ -205,6 +226,7 @@ static struct platform_driver aplic_driver =3D { .driver =3D { .name =3D "riscv-aplic", .of_match_table =3D aplic_match, + .acpi_match_table =3D ACPI_PTR(aplic_acpi_match), }, .probe =3D aplic_probe, }; diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-r= iscv-aplic-main.h index 4393927d8c80..9fbf45c7b4f7 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.h +++ b/drivers/irqchip/irq-riscv-aplic-main.h @@ -28,6 +28,7 @@ struct aplic_priv { u32 gsi_base; u32 nr_irqs; u32 nr_idcs; + u32 id; void __iomem *regs; struct aplic_msicfg msicfg; }; diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-ri= scv-aplic-msi.c index 028444af48bd..f5020241e0ed 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -157,6 +157,7 @@ static const struct msi_domain_template aplic_msi_templ= ate =3D { int aplic_msi_setup(struct device *dev, void __iomem *regs) { const struct imsic_global_config *imsic_global; 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Sat, 01 Jun 2024 08:06:22 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.187.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6c35a4ba741sm2559410a12.85.2024.06.01.08.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Jun 2024 08:06:21 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Andrew Jones , Andy Shevchenko , Marc Zyngier , Atish Kumar Patra , Haibo1 Xu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Sunil V L Subject: [PATCH v6 17/17] irqchip/sifive-plic: Add ACPI support Date: Sat, 1 Jun 2024 20:34:11 +0530 Message-Id: <20240601150411.1929783-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com> References: <20240601150411.1929783-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ACPI support in PLIC driver. Use the mapping created early during boot to get details about the PLIC. Signed-off-by: Sunil V L Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu --- drivers/irqchip/irq-sifive-plic.c | 94 ++++++++++++++++++++++++------- 1 file changed, 73 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 8fb183ced1e7..89c04f257f81 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ +#include #include #include #include @@ -70,6 +71,8 @@ struct plic_priv { unsigned long plic_quirks; unsigned int nr_irqs; unsigned long *prio_save; + u32 gsi_base; + int id; }; =20 struct plic_handler { @@ -324,6 +327,10 @@ static int plic_irq_domain_translate(struct irq_domain= *d, { struct plic_priv *priv =3D d->host_data; =20 + /* For DT, gsi_base is always zero. */ + if (fwspec->param[0] >=3D priv->gsi_base) + fwspec->param[0] =3D fwspec->param[0] - priv->gsi_base; + if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) return irq_domain_translate_twocell(d, fwspec, hwirq, type); =20 @@ -424,18 +431,37 @@ static const struct of_device_id plic_match[] =3D { {} }; =20 +#ifdef CONFIG_ACPI + +static const struct acpi_device_id plic_acpi_match[] =3D { + { "RSCV0001", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, plic_acpi_match); + +#endif static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, - u32 *nr_irqs, u32 *nr_contexts) + u32 *nr_irqs, u32 *nr_contexts, + u32 *gsi_base, u32 *id) { struct device *dev =3D &pdev->dev; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc =3D riscv_acpi_get_gsi_info(dev->fwnode, gsi_base, id, nr_irqs, NULL); + if (rc) { + dev_err(dev, "failed to find GSI mapping\n"); + return rc; + } + + *nr_contexts =3D acpi_get_plic_nr_contexts(*id); + if (WARN_ON(!*nr_contexts)) { + dev_err(dev, "no PLIC context available\n"); + return -EINVAL; + } + + return 0; + } =20 rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irq= s); if (rc) { @@ -449,23 +475,29 @@ static int plic_parse_nr_irqs_and_contexts(struct pla= tform_device *pdev, return -EINVAL; } =20 + *gsi_base =3D 0; + *id =3D 0; + return 0; } =20 static int plic_parse_context_parent(struct platform_device *pdev, u32 con= text, - u32 *parent_hwirq, int *parent_cpu) + u32 *parent_hwirq, int *parent_cpu, u32 id) { struct device *dev =3D &pdev->dev; struct of_phandle_args parent; unsigned long hartid; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + hartid =3D acpi_get_ext_intc_parent_hartid(id, context); + if (hartid =3D=3D INVALID_HARTID) + return -EINVAL; + + *parent_cpu =3D riscv_hartid_to_cpuid(hartid); + *parent_hwirq =3D RV_IRQ_EXT; + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); if (rc) @@ -490,7 +522,9 @@ static int plic_probe(struct platform_device *pdev) struct irq_domain *domain; struct plic_priv *priv; irq_hw_number_t hwirq; + int id, context_id; bool cpuhp_setup; + u32 gsi_base; =20 if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -500,7 +534,7 @@ static int plic_probe(struct platform_device *pdev) plic_quirks =3D (unsigned long)id->data; } =20 - error =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); + error =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &= gsi_base, &id); if (error) return error; =20 @@ -511,6 +545,8 @@ static int plic_probe(struct platform_device *pdev) priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; priv->nr_irqs =3D nr_irqs; + priv->gsi_base =3D gsi_base; + priv->id =3D id; =20 priv->regs =3D devm_platform_ioremap_resource(pdev, 0); if (WARN_ON(!priv->regs)) @@ -521,12 +557,22 @@ static int plic_probe(struct platform_device *pdev) return -ENOMEM; =20 for (i =3D 0; i < nr_contexts; i++) { - error =3D plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu); + error =3D plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->= id); if (error) { dev_warn(dev, "hwirq for context%d not found\n", i); continue; } =20 + if (is_of_node(dev->fwnode)) { + context_id =3D i; + } else { + context_id =3D acpi_get_plic_context(priv->id, i); + if (context_id =3D=3D INVALID_CONTEXT) { + dev_warn(dev, "invalid context id for context%d\n", i); + continue; + } + } + /* * Skip contexts other than external interrupts for our * privilege level. @@ -572,10 +618,10 @@ static int plic_probe(struct platform_device *pdev) cpumask_set_cpu(cpu, &priv->lmask); handler->present =3D true; handler->hart_base =3D priv->regs + CONTEXT_BASE + - i * CONTEXT_SIZE; + context_id * CONTEXT_SIZE; raw_spin_lock_init(&handler->enable_lock); handler->enable_base =3D priv->regs + CONTEXT_ENABLE_BASE + - i * CONTEXT_ENABLE_SIZE; + context_id * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 handler->enable_save =3D devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32), @@ -591,8 +637,8 @@ static int plic_probe(struct platform_device *pdev) nr_handlers++; } =20 - priv->irqdomain =3D irq_domain_add_linear(to_of_node(dev->fwnode), nr_irq= s + 1, - &plic_irqdomain_ops, priv); + priv->irqdomain =3D irq_domain_create_linear(dev->fwnode, nr_irqs + 1, + &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) goto fail_cleanup_contexts; =20 @@ -619,13 +665,18 @@ static int plic_probe(struct platform_device *pdev) } } =20 +#ifdef CONFIG_ACPI + if (!acpi_disabled) + acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); +#endif + dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; =20 fail_cleanup_contexts: for (i =3D 0; i < nr_contexts; i++) { - if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu)) + if (plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu, priv->id)) continue; if (parent_hwirq !=3D RV_IRQ_EXT || cpu < 0) continue; @@ -644,6 +695,7 @@ static struct platform_driver plic_driver =3D { .driver =3D { .name =3D "riscv-plic", .of_match_table =3D plic_match, + .acpi_match_table =3D ACPI_PTR(plic_acpi_match), }, .probe =3D plic_probe, }; --=20 2.40.1