From nobody Fri Feb 13 10:18:21 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 703C515217C; Sat, 1 Jun 2024 12:16:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717244186; cv=none; b=cIO2QoyPsOYP4v2QfjnIPTrS+B/AA7xmG74Ct6kb6PZvaX4nc2IEn4/8AkTMMrHkBSoyxQeBnYrx7WC9m1GJk52+1Ofe4ik/LquQ+ijU8dB75IwHjHH7+M0nnacsLF9FDBPKNmMlcG+lKwZs0K29HmFj64z/lVJ8U4apKVBS7oI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717244186; c=relaxed/simple; bh=sNsfCLDSoS4Lb5xb6DcVnNWKUWXobq4WpSsLB3Mr78s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PlKJSiu/pXQ85YcT86VE5Q0ywq+t05Gaxmq5UGELRoKkFCj+u6oUWYlvwUGoRWEU2NFziIGA7wQnkGJncvZxV5Wh/v3fG6JEfHkeRvGIgyBVyJ6bXLKsm9rZhMVuhahlz+Ne0SaDHCqAUDeAxVZgA4afj24728x2r5EKa+1EH0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=h21h0z5D; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="h21h0z5D" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 451CGHc1024779; Sat, 1 Jun 2024 07:16:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717244177; bh=Q7pP6w33g+D2x7AiTL1/nhq3ZoeesRe4xp5X2WkVzyY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h21h0z5D3BCcYqxXKrU0vs7Uam5OOb4u+j66sWQD/+0LMOj7wHaAJJ1LuTaeTe53N eOPPz9HdT4KKr7feYbkC/9i445+Z0uK9ylp8C5KJu0E6g2mgESnpRFcPDGicACt1Fl tf8zYXBaJFYyLkWRJumPr9xqrQGlLpXm62I+7v5w= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 451CGHuO001048 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 1 Jun 2024 07:16:17 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 1 Jun 2024 07:16:17 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 1 Jun 2024 07:16:17 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 451CFtkI009323; Sat, 1 Jun 2024 07:16:13 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v4 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi Date: Sat, 1 Jun 2024 17:45:51 +0530 Message-ID: <20240601121554.2860403-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601121554.2860403-1-s-vadapalli@ti.com> References: <20240601121554.2860403-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which contains the nodes shared with AM62P, followed by including the J722S specific main domain peripherals contained in "k3-j722s-main.dtsi". Signed-off-by: Siddharth Vadapalli --- No changelog since this patch is introduced in this version of the series. arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c75744edb143..9e04e6a5c0fd 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -10,12 +10,107 @@ #include #include =20 -#include "k3-am62p5.dtsi" +#include "k3-am62p-j722s-common.dtsi" +#include "k3-j722s-main.dtsi" =20 / { model =3D "Texas Instruments K3 J722S SoC"; compatible =3D "ti,j722s"; =20 + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + cbass_main: bus@f0000 { compatible =3D "simple-bus"; #address-cells =3D <2>; --=20 2.40.1