From nobody Fri Feb 13 06:09:24 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF180154C0E; Sat, 1 Jun 2024 13:13:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717247599; cv=none; b=DEqzC36fx196QGAci7/hQ2KYIvq4jAsyOWb2hOk/UAAr5X7Dkj+ibeQfO6PUxQ+6LV8/5FmNE65JwYRhVBcJN7oMWVEnKv+nDc19aYmiTI/ZCJMWWdg9fjRNtfGuqkDNuLYL2YLi98+1buOt0GQroTBj1tSkTI4Y8hKR+zTgAls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717247599; c=relaxed/simple; bh=dHkP8AoXM9OeuHhfm4CkLokGlK4S7/NMp/ySjSWfBTA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d04PSiWDYw4qAzd2LQe218ytltBqWZxGm+EvxlqggAWm6Z6WKe/xazHWm1IxP9A9YYSro/bLdmZ0zXprMvN8l0n0/N0alFxIQSW4iz7kvZ/hS05A7LT3YpFbE5snAaXbZ25rTx7FEyIHJvyXM5Z0j2nM5BVa+Cmz1KpspTwuqTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=FyN2F3Ah; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="FyN2F3Ah" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1717247596; bh=dHkP8AoXM9OeuHhfm4CkLokGlK4S7/NMp/ySjSWfBTA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FyN2F3AheUN0awtYaBAGablhrLpOTf6AVSlsDFHla87av/hL+KkdItp4nYjj6Hq7M gTUJ1JRde3N9aWehPv64QVSzBMGfLMflb5TKfGDytOPfJGdDNJBJ2cE3K+mQSQAKbL wr7hgsgfYZoMADL2BPTdE9hK6xC8x4DSfCz65x2NMYUKn+X71ZqcDIogl8j30FKvNf CcheRkYg6gRVrHvWR1bqZasujpwk3YOeJKCKNIzJzGyeDqkQHF3YttG7XiDDxkyv1S xZvUiVL3zYJxr1Qzwzj/JHEQveo1S07zrvaI0G+X7FgCv6IMlXFWHyUo/oIZRD9jn5 tUKt9wGRRtiDA== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id BD7B037821EC; Sat, 1 Jun 2024 13:13:15 +0000 (UTC) From: Cristian Ciocaltea Date: Sat, 01 Jun 2024 16:12:36 +0300 Subject: [PATCH 14/14] drm/rockchip: dw_hdmi: Add basic RK3588 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240601-b4-rk3588-bridge-upstream-v1-14-f6203753232b@collabora.com> References: <20240601-b4-rk3588-bridge-upstream-v1-0-f6203753232b@collabora.com> In-Reply-To: <20240601-b4-rk3588-bridge-upstream-v1-0-f6203753232b@collabora.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Yao Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com, Alexandre ARNOUD , Luis de Arquer , Algea Cao X-Mailer: b4 0.14-dev-f7c49 The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block. Add just the basic support for now, i.e. RGB output up to 4K@60Hz, without audio, CEC or any of the HDMI 2.1 specific features. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 261 ++++++++++++++++++++++++= +++- 1 file changed, 253 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/= rockchip/dw_hdmi-rockchip.c index ca6728a43159..48a777fe4214 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -29,8 +29,8 @@ =20 #define RK3288_GRF_SOC_CON6 0x025C #define RK3288_HDMI_LCDC_SEL BIT(4) -#define RK3328_GRF_SOC_CON2 0x0408 =20 +#define RK3328_GRF_SOC_CON2 0x0408 #define RK3328_HDMI_SDAIN_MSK BIT(11) #define RK3328_HDMI_SCLIN_MSK BIT(10) #define RK3328_HDMI_HPD_IOE BIT(2) @@ -54,6 +54,21 @@ #define RK3568_HDMI_SDAIN_MSK BIT(15) #define RK3568_HDMI_SCLIN_MSK BIT(14) =20 +#define RK3588_GRF_SOC_CON2 0x0308 +#define RK3588_HDMI0_HPD_INT_MSK BIT(13) +#define RK3588_HDMI0_HPD_INT_CLR BIT(12) +#define RK3588_GRF_SOC_CON7 0x031c +#define RK3588_SET_HPD_PATH_MASK (0x3 << 12) +#define RK3588_GRF_SOC_STATUS1 0x0384 +#define RK3588_HDMI0_LEVEL_INT BIT(16) +#define RK3588_GRF_VO1_CON3 0x000c +#define RK3588_SCLIN_MASK BIT(9) +#define RK3588_SDAIN_MASK BIT(10) +#define RK3588_MODE_MASK BIT(11) +#define RK3588_I2S_SEL_MASK BIT(13) +#define RK3588_GRF_VO1_CON9 0x0024 +#define RK3588_HDMI0_GRANT_SEL BIT(10) + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) =20 /** @@ -71,6 +86,7 @@ struct rockchip_hdmi_chip_data { struct rockchip_hdmi { struct device *dev; struct regmap *regmap; + struct regmap *vo1_regmap; struct rockchip_encoder encoder; const struct rockchip_hdmi_chip_data *chip_data; const struct dw_hdmi_plat_data *plat_data; @@ -78,6 +94,10 @@ struct rockchip_hdmi { struct clk *grf_clk; struct dw_hdmi *hdmi; struct phy *phy; + + bool is_hdmi_qp; + struct gpio_desc *qp_enable_gpio; + struct delayed_work qp_hpd_work; }; =20 static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) @@ -206,8 +226,12 @@ static const struct dw_hdmi_phy_config rockchip_phy_co= nfig[] =3D { =20 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) { + static const char * const qp_clk_names[] =3D { + "pclk", "hdp", "earc", "aud", "hclk_vo1", + }; struct device_node *np =3D hdmi->dev->of_node; - int ret; + struct clk *qp_clk; + int ret, i; =20 hdmi->regmap =3D syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(hdmi->regmap)) { @@ -234,6 +258,34 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi= *hdmi) return ret; } =20 + if (hdmi->is_hdmi_qp) { + hdmi->vo1_regmap =3D syscon_regmap_lookup_by_phandle(np, "rockchip,vo1_g= rf"); + if (IS_ERR(hdmi->vo1_regmap)) { + drm_err(hdmi, "Unable to get rockchip,vo1_grf\n"); + return PTR_ERR(hdmi->vo1_regmap); + } + + for (i =3D 0; i < ARRAY_SIZE(qp_clk_names); i++) { + qp_clk =3D devm_clk_get_optional_enabled(hdmi->dev, qp_clk_names[i]); + + if (IS_ERR(qp_clk)) { + ret =3D PTR_ERR(qp_clk); + if (ret !=3D -EPROBE_DEFER) + drm_err(hdmi, "failed to get %s clock: %d\n", + qp_clk_names[i], ret); + return ret; + } + } + + hdmi->qp_enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", + GPIOD_OUT_HIGH); + if (IS_ERR(hdmi->qp_enable_gpio)) { + ret =3D PTR_ERR(hdmi->qp_enable_gpio); + drm_err(hdmi, "failed to request enable GPIO: %d\n", ret); + return ret; + } + } + ret =3D devm_regulator_get_enable(hdmi->dev, "avdd-0v9"); if (ret) return ret; @@ -303,8 +355,32 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct d= rm_encoder *encoder, static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi *hdmi =3D to_rockchip_hdmi(encoder); + struct drm_crtc *crtc =3D encoder->crtc; u32 val; - int ret; + int ret, rate; + + if (hdmi->is_hdmi_qp) { + /* Unconditionally switch to TMDS as FRL is not yet supported */ + gpiod_set_value(hdmi->qp_enable_gpio, 1); + + if (crtc && crtc->state) { + clk_set_rate(hdmi->ref_clk, + crtc->state->adjusted_mode.crtc_clock * 1000); + /* + * FIXME: Temporary workaround to pass pixel clock rate + * to the PHY driver until phy_configure_opts_hdmi + * becomes available in the PHY API. See also the related + * comment in rk_hdptx_phy_power_on() from + * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c + */ + if (hdmi->phy) { + rate =3D crtc->state->mode.clock * 10; + phy_set_bus_width(hdmi->phy, rate); + drm_dbg(hdmi, "%s set bus_width=3D%u\n", + __func__, rate); + } + } + } =20 if (hdmi->chip_data->lcdsel_grf_reg < 0) return; @@ -356,6 +432,9 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi = *dw_hdmi, void *data, { struct rockchip_hdmi *hdmi =3D (struct rockchip_hdmi *)data; =20 + if (hdmi->is_hdmi_qp) + dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display); + return phy_power_on(hdmi->phy); } =20 @@ -430,6 +509,29 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *d= w_hdmi, void *data) RK3328_HDMI_HPD_IOE)); } =20 +static enum drm_connector_status +dw_hdmi_rk3588_read_hpd(struct dw_hdmi *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi =3D (struct rockchip_hdmi *)data; + u32 val; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); + + return val & RK3588_HDMI0_LEVEL_INT ? + connector_status_connected : connector_status_disconnected; +} + +static void dw_hdmi_rk3588_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi =3D (struct rockchip_hdmi *)data; + + regmap_write(hdmi->regmap, + RK3588_GRF_SOC_CON2, + HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR | + RK3588_HDMI0_HPD_INT_MSK)); +} + static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops =3D { .init =3D dw_hdmi_rockchip_genphy_init, .disable =3D dw_hdmi_rockchip_genphy_disable, @@ -513,6 +615,82 @@ static const struct dw_hdmi_plat_data rk3568_hdmi_drv_= data =3D { .use_drm_infoframe =3D true, }; =20 +static const struct dw_hdmi_phy_ops rk3588_hdmi_phy_ops =3D { + .init =3D dw_hdmi_rockchip_genphy_init, + .disable =3D dw_hdmi_rockchip_genphy_disable, + .read_hpd =3D dw_hdmi_rk3588_read_hpd, + .setup_hpd =3D dw_hdmi_rk3588_setup_hpd, +}; + +struct rockchip_hdmi_chip_data rk3588_chip_data =3D { + .lcdsel_grf_reg =3D -1, +}; + +static const struct dw_hdmi_plat_data rk3588_hdmi_drv_data =3D { + .phy_data =3D &rk3588_chip_data, + .phy_ops =3D &rk3588_hdmi_phy_ops, + .phy_name =3D "samsung_hdptx_phy", + .phy_force_vendor =3D true, + .use_drm_infoframe =3D true, + .is_hdmi_qp =3D true, +}; + +static void dw_hdmi_rk3588_hpd_work(struct work_struct *p_work) +{ + struct rockchip_hdmi *hdmi =3D container_of(p_work, struct rockchip_hdmi, + qp_hpd_work.work); + + struct drm_device *drm =3D hdmi->encoder.encoder.dev; + bool changed; + + if (drm) { + changed =3D drm_helper_hpd_irq_event(drm); + if (changed) + drm_dbg(hdmi, "connector status changed\n"); + } +} + +static irqreturn_t dw_hdmi_rk3588_hardirq(int irq, void *dev_id) +{ + struct rockchip_hdmi *hdmi =3D dev_id; + u32 intr_stat, val; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); + + if (intr_stat) { + val =3D HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, + RK3588_HDMI0_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t dw_hdmi_rk3588_irq(int irq, void *dev_id) +{ + struct rockchip_hdmi *hdmi =3D dev_id; + u32 intr_stat, val; + int debounce_ms; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); + if (!intr_stat) + return IRQ_NONE; + + val =3D HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + debounce_ms =3D intr_stat & RK3588_HDMI0_LEVEL_INT ? 150 : 20; + mod_delayed_work(system_wq, &hdmi->qp_hpd_work, + msecs_to_jiffies(debounce_ms)); + + val |=3D HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + return IRQ_HANDLED; +} + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] =3D { { .compatible =3D "rockchip,rk3228-dw-hdmi", .data =3D &rk3228_hdmi_drv_data @@ -529,6 +707,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_id= s[] =3D { { .compatible =3D "rockchip,rk3568-dw-hdmi", .data =3D &rk3568_hdmi_drv_data }, + { .compatible =3D "rockchip,rk3588-dw-hdmi", + .data =3D &rk3588_hdmi_drv_data + }, {}, }; MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); @@ -542,7 +723,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, st= ruct device *master, struct drm_device *drm =3D data; struct drm_encoder *encoder; struct rockchip_hdmi *hdmi; - int ret; + int ret, irq; + u32 val; =20 if (!pdev->dev.of_node) return -ENODEV; @@ -553,13 +735,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, = struct device *master, =20 match =3D of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); plat_data =3D devm_kmemdup(&pdev->dev, match->data, - sizeof(*plat_data), GFP_KERNEL); + sizeof(*plat_data), GFP_KERNEL); if (!plat_data) return -ENOMEM; =20 hdmi->dev =3D &pdev->dev; hdmi->plat_data =3D plat_data; hdmi->chip_data =3D plat_data->phy_data; + hdmi->is_hdmi_qp =3D plat_data->is_hdmi_qp; plat_data->phy_data =3D hdmi; plat_data->priv_data =3D hdmi; encoder =3D &hdmi->encoder.encoder; @@ -598,6 +781,37 @@ static int dw_hdmi_rockchip_bind(struct device *dev, s= truct device *master, RK3568_HDMI_SCLIN_MSK, RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK)); + } else if (hdmi->is_hdmi_qp) { + val =3D HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + + val =3D HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val =3D HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); + + val =3D HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK= ); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + INIT_DELAYED_WORK(&hdmi->qp_hpd_work, dw_hdmi_rk3588_hpd_work); + + irq =3D platform_get_irq(pdev, 4); + if (irq < 0) + return irq; + + ret =3D devm_request_threaded_irq(hdmi->dev, irq, + dw_hdmi_rk3588_hardirq, + dw_hdmi_rk3588_irq, + IRQF_SHARED, "dw-hdmi-qp-hpd", + hdmi); + if (ret) + return ret; } =20 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); @@ -605,7 +819,10 @@ static int dw_hdmi_rockchip_bind(struct device *dev, s= truct device *master, =20 platform_set_drvdata(pdev, hdmi); =20 - hdmi->hdmi =3D dw_hdmi_bind(pdev, encoder, plat_data); + if (hdmi->is_hdmi_qp) + hdmi->hdmi =3D dw_hdmi_qp_bind(pdev, encoder, plat_data); + else + hdmi->hdmi =3D dw_hdmi_bind(pdev, encoder, plat_data); =20 /* * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), @@ -629,7 +846,13 @@ static void dw_hdmi_rockchip_unbind(struct device *dev= , struct device *master, { struct rockchip_hdmi *hdmi =3D dev_get_drvdata(dev); =20 - dw_hdmi_unbind(hdmi->hdmi); + if (hdmi->is_hdmi_qp) { + cancel_delayed_work_sync(&hdmi->qp_hpd_work); + dw_hdmi_qp_unbind(hdmi->hdmi); + } else { + dw_hdmi_unbind(hdmi->hdmi); + } + drm_encoder_cleanup(&hdmi->encoder.encoder); } =20 @@ -651,8 +874,30 @@ static void dw_hdmi_rockchip_remove(struct platform_de= vice *pdev) static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev) { struct rockchip_hdmi *hdmi =3D dev_get_drvdata(dev); + u32 val; + + if (hdmi->is_hdmi_qp) { + val =3D HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); =20 - dw_hdmi_resume(hdmi->hdmi); + val =3D HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val =3D HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); + + dw_hdmi_qp_resume(dev, hdmi->hdmi); + + if (hdmi->encoder.encoder.dev) + drm_helper_hpd_irq_event(hdmi->encoder.encoder.dev); + } else { + dw_hdmi_resume(hdmi->hdmi); + } =20 return 0; } --=20 2.45.0