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charset="utf-8" This patch fixes a compile error by using the devm_pwmchip_alloc() helper function along the way. Signed-off-by: Hironori KIKUCHI --- drivers/pwm/pwm-sun20i.c | 45 ++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c index 3e3b5b138b3..93782023af6 100644 --- a/drivers/pwm/pwm-sun20i.c +++ b/drivers/pwm/pwm-sun20i.c @@ -102,7 +102,7 @@ struct sun20i_pwm_chip { =20 static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *= chip) { - return container_of(chip, struct sun20i_pwm_chip, chip); + return pwmchip_get_drvdata(chip); } =20 static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip, @@ -308,12 +308,31 @@ static void sun20i_pwm_reset_ctrl_release(void *data) =20 static int sun20i_pwm_probe(struct platform_device *pdev) { + struct pwm_chip *chip; struct sun20i_pwm_chip *sun20i_chip; + const struct sun20i_pwm_data *data; + u32 npwm; int ret; =20 - sun20i_chip =3D devm_kzalloc(&pdev->dev, sizeof(*sun20i_chip), GFP_KERNEL= ); - if (!sun20i_chip) - return -ENOMEM; + data =3D of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + + ret =3D of_property_read_u32(pdev->dev.of_node, "allwinner,pwm-channels",= &npwm); + if (ret) + npwm =3D 8; + + if (npwm > 16) { + dev_info(&pdev->dev, "Limiting number of PWM lines from %u to 16", npwm); + npwm =3D 16; + } + + chip =3D devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*sun20i_chip)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + sun20i_chip =3D to_sun20i_pwm_chip(chip); + + sun20i_chip->data =3D data; =20 sun20i_chip->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sun20i_chip->base)) @@ -339,17 +358,6 @@ static int sun20i_pwm_probe(struct platform_device *pd= ev) return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->rst), "failed to get bus reset\n"); =20 - ret =3D of_property_read_u32(pdev->dev.of_node, "allwinner,pwm-channels", - &sun20i_chip->chip.npwm); - if (ret) - sun20i_chip->chip.npwm =3D 8; - - if (sun20i_chip->chip.npwm > 16) { - dev_info(&pdev->dev, "Limiting number of PWM lines from %u to 16", - sun20i_chip->chip.npwm); - sun20i_chip->chip.npwm =3D 16; - } - /* Deassert reset */ ret =3D reset_control_deassert(sun20i_chip->rst); if (ret) @@ -359,17 +367,14 @@ static int sun20i_pwm_probe(struct platform_device *p= dev) if (ret) return ret; =20 - sun20i_chip->chip.dev =3D &pdev->dev; - sun20i_chip->chip.ops =3D &sun20i_pwm_ops; + chip->ops =3D &sun20i_pwm_ops; =20 mutex_init(&sun20i_chip->mutex); =20 - ret =3D devm_pwmchip_add(&pdev->dev, &sun20i_chip->chip); + ret =3D devm_pwmchip_add(&pdev->dev, chip); if (ret < 0) return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); =20 - platform_set_drvdata(pdev, sun20i_chip); - return 0; } =20 --=20 2.45.1 From nobody Fri Feb 13 06:07:12 2026 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E275176228; Fri, 31 May 2024 14:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 31 May 2024 07:12:24 -0700 (PDT) Received: from noel.flets-west.jp ([2405:6586:4480:a10:167:9818:d778:5c14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b057besm1418103b3a.162.2024.05.31.07.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 07:12:24 -0700 (PDT) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Aleksandr Shubin , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 2/5] pwm: sun20i: Add support for Allwinner H616 PWM Date: Fri, 31 May 2024 23:11:34 +0900 Message-ID: <20240531141152.327592-3-kikuchan98@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240531141152.327592-1-kikuchan98@gmail.com> References: <20240531141152.327592-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allwinner H616 SoC has a PWM controller similar to the one in the D1, which is supported by the pwm-sun20i driver. This patch adds support for the Allwinner H616 PWM. The main difference is in the register layout. Specifically, the GATING flag is placed in the PCCR register instead of the individual PCGR register. Thus, it must be handled properly. Signed-off-by: Hironori KIKUCHI --- drivers/pwm/pwm-sun20i.c | 109 ++++++++++++++++++++++++++++++--------- 1 file changed, 86 insertions(+), 23 deletions(-) diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c index 93782023af6..d07ce0ebd2a 100644 --- a/drivers/pwm/pwm-sun20i.c +++ b/drivers/pwm/pwm-sun20i.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329) + * PWM Controller Driver for sunxi platforms (D1, T113-S3, R329 and H616) * * Limitations: * - When the parameters change, current running period will not be comple= ted @@ -20,8 +20,17 @@ #include #include =20 +#define SUN20I_PWM_REG_OFFSET_PER_D1 (0x0080) +#define SUN20I_PWM_REG_OFFSET_PCR_D1 (0x0100 + 0x0000) +#define SUN20I_PWM_REG_OFFSET_PPR_D1 (0x0100 + 0x0004) +#define SUN20I_PWM_REG_OFFSET_PER_H616 (0x0040) +#define SUN20I_PWM_REG_OFFSET_PCR_H616 (0x0060 + 0x0000) +#define SUN20I_PWM_REG_OFFSET_PPR_H616 (0x0060 + 0x0004) + #define SUN20I_PWM_CLK_CFG(chan) (0x20 + (((chan) >> 1) * 0x4)) #define SUN20I_PWM_CLK_CFG_SRC GENMASK(8, 7) +#define SUN20I_PWM_CLK_CFG_BYPASS(chan) BIT(5 + ((chan) & 1)) +#define SUN20I_PWM_CLK_CFG_GATING BIT(4) #define SUN20I_PWM_CLK_CFG_DIV_M GENMASK(3, 0) #define SUN20I_PWM_CLK_DIV_M_MAX 8 =20 @@ -29,15 +38,15 @@ #define SUN20I_PWM_CLK_GATE_BYPASS(chan) BIT((chan) + 16) #define SUN20I_PWM_CLK_GATE_GATING(chan) BIT(chan) =20 -#define SUN20I_PWM_ENABLE 0x80 +#define SUN20I_PWM_ENABLE(chip) ((chip)->data->reg_per) #define SUN20I_PWM_ENABLE_EN(chan) BIT(chan) =20 -#define SUN20I_PWM_CTL(chan) (0x100 + (chan) * 0x20) +#define SUN20I_PWM_CTL(chip, chan) ((chip)->data->reg_pcr + (chan) * 0x20) #define SUN20I_PWM_CTL_ACT_STA BIT(8) #define SUN20I_PWM_CTL_PRESCAL_K GENMASK(7, 0) #define SUN20I_PWM_CTL_PRESCAL_K_MAX field_max(SUN20I_PWM_CTL_PRESCAL_K) =20 -#define SUN20I_PWM_PERIOD(chan) (0x104 + (chan) * 0x20) +#define SUN20I_PWM_PERIOD(chip, chan) ((chip)->data->reg_ppr + (chan) * 0= x20) #define SUN20I_PWM_PERIOD_ENTIRE_CYCLE GENMASK(31, 16) #define SUN20I_PWM_PERIOD_ACT_CYCLE GENMASK(15, 0) =20 @@ -91,6 +100,13 @@ */ #define SUN20I_PWM_MAGIC (255 * 65537 + 2 * 65536 + 1) =20 +struct sun20i_pwm_data { + unsigned long reg_per; + unsigned long reg_pcr; + unsigned long reg_ppr; + bool has_pcgr; +}; + struct sun20i_pwm_chip { struct clk *clk_bus, *clk_hosc, *clk_apb; struct reset_control *rst; @@ -98,6 +114,7 @@ struct sun20i_pwm_chip { void __iomem *base; /* Mutex to protect pwm apply state */ struct mutex mutex; + const struct sun20i_pwm_data *data; }; =20 static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *= chip) @@ -139,16 +156,16 @@ static int sun20i_pwm_get_state(struct pwm_chip *chip, else clk_rate =3D clk_get_rate(sun20i_chip->clk_apb); =20 - val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(sun20i_chip, pwm->hw= pwm)); state->polarity =3D (SUN20I_PWM_CTL_ACT_STA & val) ? PWM_POLARITY_NORMAL : PWM_POLARITY_INVERSED; =20 prescale_k =3D FIELD_GET(SUN20I_PWM_CTL_PRESCAL_K, val) + 1; =20 - val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE); + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE(sun20i_chip)); state->enabled =3D (SUN20I_PWM_ENABLE_EN(pwm->hwpwm) & val) ? true : fals= e; =20 - val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_PERIOD(pwm->hwpwm)); + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_PERIOD(sun20i_chip, pwm-= >hwpwm)); =20 mutex_unlock(&sun20i_chip->mutex); =20 @@ -187,23 +204,32 @@ static int sun20i_pwm_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 mutex_lock(&sun20i_chip->mutex); =20 - pwm_en =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE); + pwm_en =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE(sun20i_chip)); =20 - if (state->enabled !=3D pwm->state.enabled) { - clk_gate =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_GATE); - - if (!state->enabled) { + if (state->enabled !=3D pwm->state.enabled && !state->enabled) { + if (sun20i_chip->data->has_pcgr) { + /* Disabling the gate via PWM Clock Gating Register */ + clk_gate =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_GATE); clk_gate &=3D ~SUN20I_PWM_CLK_GATE_GATING(pwm->hwpwm); - pwm_en &=3D ~SUN20I_PWM_ENABLE_EN(pwm->hwpwm); - sun20i_pwm_writel(sun20i_chip, pwm_en, SUN20I_PWM_ENABLE); sun20i_pwm_writel(sun20i_chip, clk_gate, SUN20I_PWM_CLK_GATE); + } else if (!(pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1))) { + /* + * Disabling the gate via PWM Clock Configuration Register + * if and only if the counterpart channel is disabled + */ + clk_cfg =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm= )); + clk_cfg &=3D ~SUN20I_PWM_CLK_CFG_GATING; + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); } + + pwm_en &=3D ~SUN20I_PWM_ENABLE_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, sun20i_chip->data->reg_per); } =20 if (state->polarity !=3D pwm->state.polarity || state->duty_cycle !=3D pwm->state.duty_cycle || state->period !=3D pwm->state.period) { - ctl =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); + ctl =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(sun20i_chip, pwm->h= wpwm)); clk_cfg =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm)= ); hosc_rate =3D clk_get_rate(sun20i_chip->clk_hosc); bus_rate =3D clk_get_rate(sun20i_chip->clk_apb); @@ -234,7 +260,8 @@ static int sun20i_pwm_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, } =20 /* set up the CLK_DIV_M and clock CLK_SRC */ - clk_cfg =3D FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); + clk_cfg &=3D ~(SUN20I_PWM_CLK_CFG_DIV_M | SUN20I_PWM_CLK_CFG_SRC); + clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); =20 sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); @@ -265,21 +292,33 @@ static int sun20i_pwm_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, * Duty-cycle =3D T high-level / T period */ reg_period |=3D FIELD_PREP(SUN20I_PWM_PERIOD_ACT_CYCLE, act_cycle); - sun20i_pwm_writel(sun20i_chip, reg_period, SUN20I_PWM_PERIOD(pwm->hwpwm)= ); + sun20i_pwm_writel(sun20i_chip, reg_period, + SUN20I_PWM_PERIOD(sun20i_chip, pwm->hwpwm)); =20 ctl =3D FIELD_PREP(SUN20I_PWM_CTL_PRESCAL_K, prescale_k); if (state->polarity =3D=3D PWM_POLARITY_NORMAL) ctl |=3D SUN20I_PWM_CTL_ACT_STA; =20 - sun20i_pwm_writel(sun20i_chip, ctl, SUN20I_PWM_CTL(pwm->hwpwm)); + sun20i_pwm_writel(sun20i_chip, ctl, SUN20I_PWM_CTL(sun20i_chip, pwm->hwp= wm)); } =20 if (state->enabled !=3D pwm->state.enabled && state->enabled) { - clk_gate &=3D ~SUN20I_PWM_CLK_GATE_BYPASS(pwm->hwpwm); - clk_gate |=3D SUN20I_PWM_CLK_GATE_GATING(pwm->hwpwm); + if (sun20i_chip->data->has_pcgr) { + /* Enabling the gate via PWM Clock Gating Register */ + clk_gate =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_GATE); + clk_gate &=3D ~SUN20I_PWM_CLK_GATE_BYPASS(pwm->hwpwm); + clk_gate |=3D SUN20I_PWM_CLK_GATE_GATING(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, clk_gate, SUN20I_PWM_CLK_GATE); + } else { + /* Enabling the gate via PWM Clock Configuration Register */ + clk_cfg =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm= )); + clk_cfg &=3D ~SUN20I_PWM_CLK_CFG_BYPASS(pwm->hwpwm); + clk_cfg |=3D SUN20I_PWM_CLK_CFG_GATING; + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); + } + pwm_en |=3D SUN20I_PWM_ENABLE_EN(pwm->hwpwm); - sun20i_pwm_writel(sun20i_chip, pwm_en, SUN20I_PWM_ENABLE); - sun20i_pwm_writel(sun20i_chip, clk_gate, SUN20I_PWM_CLK_GATE); + sun20i_pwm_writel(sun20i_chip, pwm_en, SUN20I_PWM_ENABLE(sun20i_chip)); } =20 unlock_mutex: @@ -293,8 +332,29 @@ static const struct pwm_ops sun20i_pwm_ops =3D { .get_state =3D sun20i_pwm_get_state, }; =20 +static const struct sun20i_pwm_data sun20i_d1_pwm_data =3D { + .reg_per =3D SUN20I_PWM_REG_OFFSET_PER_D1, + .reg_pcr =3D SUN20I_PWM_REG_OFFSET_PCR_D1, + .reg_ppr =3D SUN20I_PWM_REG_OFFSET_PPR_D1, + .has_pcgr =3D true, +}; + +static const struct sun20i_pwm_data sun50i_h616_pwm_data =3D { + .reg_per =3D SUN20I_PWM_REG_OFFSET_PER_H616, + .reg_pcr =3D SUN20I_PWM_REG_OFFSET_PCR_H616, + .reg_ppr =3D SUN20I_PWM_REG_OFFSET_PPR_H616, + .has_pcgr =3D false, +}; + static const struct of_device_id sun20i_pwm_dt_ids[] =3D { - { .compatible =3D "allwinner,sun20i-d1-pwm" }, + { + .compatible =3D "allwinner,sun20i-d1-pwm", + .data =3D &sun20i_d1_pwm_data + }, + { + .compatible =3D "allwinner,sun50i-h616-pwm", + .data =3D &sun50i_h616_pwm_data + }, { }, }; MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids); @@ -338,6 +398,8 @@ static int sun20i_pwm_probe(struct platform_device *pde= v) if (IS_ERR(sun20i_chip->base)) return PTR_ERR(sun20i_chip->base); =20 + sun20i_chip->data =3D data; + sun20i_chip->clk_bus =3D devm_clk_get_enabled(&pdev->dev, "bus"); if (IS_ERR(sun20i_chip->clk_bus)) return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_bus), @@ -388,5 +450,6 @@ static struct platform_driver sun20i_pwm_driver =3D { module_platform_driver(sun20i_pwm_driver); =20 MODULE_AUTHOR("Aleksandr Shubin "); +MODULE_AUTHOR("Hironori KIKUCHI "); MODULE_DESCRIPTION("Allwinner sun20i PWM driver"); MODULE_LICENSE("GPL"); --=20 2.45.1 From nobody Fri Feb 13 06:07:12 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10D64178369; Fri, 31 May 2024 14:12:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 31 May 2024 07:12:28 -0700 (PDT) Received: from noel.flets-west.jp ([2405:6586:4480:a10:167:9818:d778:5c14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b057besm1418103b3a.162.2024.05.31.07.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 07:12:28 -0700 (PDT) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Aleksandr Shubin , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/5] dt-bindings: pwm: sun20i: Add compatible string for Allwinner H616 PWM Date: Fri, 31 May 2024 23:11:35 +0900 Message-ID: <20240531141152.327592-4-kikuchan98@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240531141152.327592-1-kikuchan98@gmail.com> References: <20240531141152.327592-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allwinner H616 SoC has a PWM controller similar to the one in the D1, which is supported by the pwm-sun20i driver. The main difference is in the register layout. Specifically, the GATING flag is placed in the PCCR register instead of the individual PCGR register. Add a compatible string to distinguish them. Signed-off-by: Hironori KIKUCHI --- Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yam= l b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml index 89cebf7841a..b9b6d7e7c87 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -17,6 +17,7 @@ properties: - items: - const: allwinner,sun50i-r329-pwm - const: allwinner,sun20i-d1-pwm + - const: allwinner,sun50i-h616-pwm =20 reg: maxItems: 1 --=20 2.45.1 From nobody Fri Feb 13 06:07:12 2026 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA0E9178369; Fri, 31 May 2024 14:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 31 May 2024 07:12:31 -0700 (PDT) Received: from noel.flets-west.jp ([2405:6586:4480:a10:167:9818:d778:5c14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b057besm1418103b3a.162.2024.05.31.07.12.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 07:12:31 -0700 (PDT) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Aleksandr Shubin , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 4/5] pwm: sun20i: Delegating the clock source and DIV_M to the Device Tree Date: Fri, 31 May 2024 23:11:36 +0900 Message-ID: <20240531141152.327592-5-kikuchan98@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240531141152.327592-1-kikuchan98@gmail.com> References: <20240531141152.327592-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This patch removes the SUN20I_PWM_MAGIC macro by delegating the clock source and DIV_M selection to the Device Tree. This change addresses the issue of resolution discrepancies that arise from the enabling order of PWM channels which are coupled. Additionally, this patch clarifies and corrects the calculations for the period and duty cycle. By using DIV_ROUND_CLOSEST(), it minimizes the errors between the configured and actual values. Signed-off-by: Hironori KIKUCHI --- drivers/pwm/pwm-sun20i.c | 190 ++++++++++++++++----------------------- 1 file changed, 79 insertions(+), 111 deletions(-) diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c index d07ce0ebd2a..4bf8a67df38 100644 --- a/drivers/pwm/pwm-sun20i.c +++ b/drivers/pwm/pwm-sun20i.c @@ -52,53 +52,13 @@ =20 #define SUN20I_PWM_PCNTR_SIZE BIT(16) =20 -/* - * SUN20I_PWM_MAGIC is used to quickly compute the values of the clock div= iders - * div_m (SUN20I_PWM_CLK_CFG_DIV_M) & prescale_k (SUN20I_PWM_CTL_PRESCAL_K) - * without using a loop. These dividers limit the # of cycles in a period - * to SUN20I_PWM_PCNTR_SIZE by applying a scaling factor of - * 1/(div_m * (prescale_k + 1)) to the clock source. - * - * SUN20I_PWM_MAGIC is derived by solving for div_m and prescale_k - * such that for a given requested period, - * - * i) div_m is minimized for any prescale_k =E2=89=A4 SUN20I_PWM_CTL_PRESC= AL_K_MAX, - * ii) prescale_k is minimized. - * - * The derivation proceeds as follows, with val =3D # of cycles for reques= ted - * period: - * - * for a given value of div_m we want the smallest prescale_k such that - * - * (val >> div_m) // (prescale_k + 1) =E2=89=A4 65536 (SUN20I_PWM_PCNTR_SI= ZE) - * - * This is equivalent to: - * - * (val >> div_m) =E2=89=A4 65536 * (prescale_k + 1) + prescale_k - * =E2=9F=BA (val >> div_m) =E2=89=A4 65537 * prescale_k + 65536 - * =E2=9F=BA (val >> div_m) - 65536 =E2=89=A4 65537 * prescale_k - * =E2=9F=BA ((val >> div_m) - 65536) / 65537 =E2=89=A4 prescale_k - * - * As prescale_k is integer, this becomes - * - * ((val >> div_m) - 65536) // 65537 =E2=89=A4 prescale_k - * - * And is minimized at - * - * ((val >> div_m) - 65536) // 65537 - * - * Now we pick the smallest div_m that satifies prescale_k =E2=89=A4 255 - * (i.e SUN20I_PWM_CTL_PRESCAL_K_MAX), - * - * ((val >> div_m) - 65536) // 65537 =E2=89=A4 255 - * =E2=9F=BA (val >> div_m) - 65536 =E2=89=A4 255 * 65537 + 65536 - * =E2=9F=BA val >> div_m =E2=89=A4 255 * 65537 + 2 * 65536 - * =E2=9F=BA val >> div_m < (255 * 65537 + 2 * 65536 + 1) - * =E2=9F=BA div_m =3D fls((val) / (255 * 65537 + 2 * 65536 + 1)) - * - * Suggested by Uwe Kleine-K=C3=B6nig - */ -#define SUN20I_PWM_MAGIC (255 * 65537 + 2 * 65536 + 1) +#define SUN20I_PWM_CLOCK_SRC_HOSC (0) +#define SUN20I_PWM_CLOCK_SRC_APB (1) +#define SUN20I_PWM_CLOCK_SRC_DEFAULT SUN20I_PWM_CLOCK_SRC_HOSC +#define SUN20I_PWM_DIV_M_SHIFT_DEFAULT (0) + +#define SUN20I_PWM_CHANNELS_MAX (16) +#define SUN20I_PWM_ENTIRE_CYCLE_MAX (0xffff) =20 struct sun20i_pwm_data { unsigned long reg_per; @@ -115,6 +75,9 @@ struct sun20i_pwm_chip { /* Mutex to protect pwm apply state */ struct mutex mutex; const struct sun20i_pwm_data *data; + + u32 clk_src_reg[(SUN20I_PWM_CHANNELS_MAX + 1) / 2]; + u32 div_m_shift_reg[(SUN20I_PWM_CHANNELS_MAX + 1) / 2]; }; =20 static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *= chip) @@ -139,7 +102,8 @@ static int sun20i_pwm_get_state(struct pwm_chip *chip, struct pwm_state *state) { struct sun20i_pwm_chip *sun20i_chip =3D to_sun20i_pwm_chip(chip); - u16 ent_cycle, act_cycle, prescale_k; + u32 ent_cycle, act_cycle; + u16 prescale_k; u64 clk_rate, tmp; u8 div_m; u32 val; @@ -170,7 +134,7 @@ static int sun20i_pwm_get_state(struct pwm_chip *chip, mutex_unlock(&sun20i_chip->mutex); =20 act_cycle =3D FIELD_GET(SUN20I_PWM_PERIOD_ACT_CYCLE, val); - ent_cycle =3D FIELD_GET(SUN20I_PWM_PERIOD_ENTIRE_CYCLE, val); + ent_cycle =3D FIELD_GET(SUN20I_PWM_PERIOD_ENTIRE_CYCLE, val) + 1; =20 /* * The duration of the active phase should not be longer @@ -196,9 +160,9 @@ static int sun20i_pwm_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, const struct pwm_state *state) { struct sun20i_pwm_chip *sun20i_chip =3D to_sun20i_pwm_chip(chip); - u64 bus_rate, hosc_rate, val, ent_cycle, act_cycle; - u32 clk_gate, clk_cfg, pwm_en, ctl, reg_period; - u32 prescale_k, div_m; + u64 bus_rate, hosc_rate, ent_cycle, act_cycle; + u32 clk_gate, clk_cfg, pwm_en, ctl, reg_period, clk_rate; + u32 prescale_k, div_m, div_m_shift; bool use_bus_clk; int ret =3D 0; =20 @@ -229,76 +193,49 @@ static int sun20i_pwm_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, if (state->polarity !=3D pwm->state.polarity || state->duty_cycle !=3D pwm->state.duty_cycle || state->period !=3D pwm->state.period) { - ctl =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(sun20i_chip, pwm->h= wpwm)); - clk_cfg =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm)= ); + int idx =3D pwm->hwpwm / 2; + hosc_rate =3D clk_get_rate(sun20i_chip->clk_hosc); bus_rate =3D clk_get_rate(sun20i_chip->clk_apb); - if (pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1)) { - /* if the neighbor channel is enable, check period only */ - use_bus_clk =3D FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, clk_cfg) !=3D 0; - val =3D mul_u64_u64_div_u64(state->period, - (use_bus_clk ? bus_rate : hosc_rate), - NSEC_PER_SEC); =20 - div_m =3D FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, clk_cfg); - } else { - /* check period and select clock source */ - use_bus_clk =3D false; - val =3D mul_u64_u64_div_u64(state->period, hosc_rate, NSEC_PER_SEC); - if (val <=3D 1) { - use_bus_clk =3D true; - val =3D mul_u64_u64_div_u64(state->period, bus_rate, NSEC_PER_SEC); - if (val <=3D 1) { - ret =3D -EINVAL; - goto unlock_mutex; - } - } - div_m =3D fls(DIV_ROUND_DOWN_ULL(val, SUN20I_PWM_MAGIC)); - if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) { - ret =3D -EINVAL; - goto unlock_mutex; - } + use_bus_clk =3D sun20i_chip->clk_src_reg[idx] =3D=3D SUN20I_PWM_CLOCK_SR= C_APB; + clk_rate =3D use_bus_clk ? bus_rate : hosc_rate; + div_m_shift =3D sun20i_chip->div_m_shift_reg[idx]; + div_m =3D 1 << div_m_shift; =20 - /* set up the CLK_DIV_M and clock CLK_SRC */ - clk_cfg &=3D ~(SUN20I_PWM_CLK_CFG_DIV_M | SUN20I_PWM_CLK_CFG_SRC); - clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); - clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); - - sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); + if (state->period > U64_MAX / clk_rate || state->duty_cycle > state->per= iod) { + ret =3D -EINVAL; + goto unlock_mutex; } + ent_cycle =3D DIV_ROUND_CLOSEST(state->period * clk_rate, NSEC_PER_SEC *= div_m); + act_cycle =3D + min(DIV_ROUND_CLOSEST(state->duty_cycle * clk_rate, NSEC_PER_SEC * div_= m), + ent_cycle); + if (ent_cycle =3D=3D 0 || + ent_cycle > SUN20I_PWM_ENTIRE_CYCLE_MAX * SUN20I_PWM_CTL_PRESCAL_K_M= AX) { + ret =3D -EINVAL; + goto unlock_mutex; + } + prescale_k =3D clamp(DIV_ROUND_UP_ULL(ent_cycle, SUN20I_PWM_ENTIRE_CYCLE= _MAX), 1, + SUN20I_PWM_CTL_PRESCAL_K_MAX); + ent_cycle =3D clamp(DIV_ROUND_CLOSEST_ULL(ent_cycle, prescale_k), 1, + SUN20I_PWM_ENTIRE_CYCLE_MAX); + act_cycle =3D clamp(DIV_ROUND_CLOSEST_ULL(act_cycle, prescale_k), 0, ent= _cycle); =20 - /* calculate prescale_k, PWM entire cycle */ - ent_cycle =3D val >> div_m; - prescale_k =3D DIV_ROUND_DOWN_ULL(ent_cycle, 65537); - if (prescale_k > SUN20I_PWM_CTL_PRESCAL_K_MAX) - prescale_k =3D SUN20I_PWM_CTL_PRESCAL_K_MAX; + clk_cfg =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm)= ); + clk_cfg &=3D ~(SUN20I_PWM_CLK_CFG_DIV_M | SUN20I_PWM_CLK_CFG_SRC); + clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m_shift); + clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); =20 - do_div(ent_cycle, prescale_k + 1); - - /* for N cycles, PPRx.PWM_ENTIRE_CYCLE =3D (N-1) */ reg_period =3D FIELD_PREP(SUN20I_PWM_PERIOD_ENTIRE_CYCLE, ent_cycle - 1); - - /* set duty cycle */ - val =3D mul_u64_u64_div_u64(state->duty_cycle, - (use_bus_clk ? bus_rate : hosc_rate), - NSEC_PER_SEC); - act_cycle =3D val >> div_m; - do_div(act_cycle, prescale_k + 1); - - /* - * The formula of the output period and the duty-cycle for PWM are as fo= llows. - * T period =3D (PWM01_CLK / PWM0_PRESCALE_K)^-1 * (PPR0.PWM_ENTIRE_CYCL= E + 1) - * T high-level =3D (PWM01_CLK / PWM0_PRESCALE_K)^-1 * PPR0.PWM_ACT_CYCLE - * Duty-cycle =3D T high-level / T period - */ reg_period |=3D FIELD_PREP(SUN20I_PWM_PERIOD_ACT_CYCLE, act_cycle); sun20i_pwm_writel(sun20i_chip, reg_period, SUN20I_PWM_PERIOD(sun20i_chip, pwm->hwpwm)); =20 - ctl =3D FIELD_PREP(SUN20I_PWM_CTL_PRESCAL_K, prescale_k); + ctl =3D FIELD_PREP(SUN20I_PWM_CTL_PRESCAL_K, prescale_k - 1); if (state->polarity =3D=3D PWM_POLARITY_NORMAL) ctl |=3D SUN20I_PWM_CTL_ACT_STA; - sun20i_pwm_writel(sun20i_chip, ctl, SUN20I_PWM_CTL(sun20i_chip, pwm->hwp= wm)); } =20 @@ -382,9 +319,10 @@ static int sun20i_pwm_probe(struct platform_device *pd= ev) if (ret) npwm =3D 8; =20 - if (npwm > 16) { - dev_info(&pdev->dev, "Limiting number of PWM lines from %u to 16", npwm); - npwm =3D 16; + if (npwm > SUN20I_PWM_CHANNELS_MAX) { + dev_info(&pdev->dev, "Limiting number of PWM lines from %u to %u", npwm, + SUN20I_PWM_CHANNELS_MAX); + npwm =3D SUN20I_PWM_CHANNELS_MAX; } =20 chip =3D devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*sun20i_chip)); @@ -420,6 +358,36 @@ static int sun20i_pwm_probe(struct platform_device *pd= ev) return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->rst), "failed to get bus reset\n"); =20 + for (int i =3D 0; i < (npwm + 1) / 2; i++) { + const char *source; + u32 div_m; + + sun20i_chip->clk_src_reg[i] =3D SUN20I_PWM_CLOCK_SRC_DEFAULT; + sun20i_chip->div_m_shift_reg[i] =3D SUN20I_PWM_DIV_M_SHIFT_DEFAULT; + + ret =3D of_property_read_string_index(pdev->dev.of_node, + "allwinner,pwm-pair-clock-sources", i, &source); + if (!ret) { + if (!strcasecmp(source, "hosc")) + sun20i_chip->clk_src_reg[i] =3D SUN20I_PWM_CLOCK_SRC_HOSC; + else if (!strcasecmp(source, "apb")) + sun20i_chip->clk_src_reg[i] =3D SUN20I_PWM_CLOCK_SRC_APB; + else + return dev_err_probe(&pdev->dev, -EINVAL, + "Unknown clock source: %s\n", source); + } + + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "allwinner,pwm-pair-clock-prescales", i, &div_m); + if (!ret) { + if (div_m <=3D SUN20I_PWM_CLK_DIV_M_MAX) + sun20i_chip->div_m_shift_reg[i] =3D div_m; + else + return dev_err_probe(&pdev->dev, -EINVAL, + "Invalid prescale value: %u\n", div_m); + } + } + /* Deassert reset */ ret =3D reset_control_deassert(sun20i_chip->rst); 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charset="utf-8" This patch adds new options to select a clock source and DIV_M register value for each coupled PWM channels. Signed-off-by: Hironori KIKUCHI --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yam= l b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml index b9b6d7e7c87..436a1d344ab 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -45,6 +45,25 @@ properties: description: The number of PWM channels configured for this instance enum: [6, 9] =20 + allwinner,pwm-pair-clock-sources: + description: The clock source names for each PWM pair + items: + enum: [hosc, apb] + minItems: 1 + maxItems: 8 + + allwinner,pwm-pair-clock-prescales: + description: The prescale (DIV_M register) values for each PWM pair + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + minimum: 0 + maximum: 8 + minItems: 1 + maxItems: 1 + minItems: 1 + maxItems: 8 + allOf: - $ref: pwm.yaml# =20 --=20 2.45.1