From nobody Mon Feb 9 12:34:25 2026 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3840712E1C1 for ; Fri, 31 May 2024 06:58:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717138684; cv=none; b=ob6OZWac6za9/zwwV1BR9wQtacJxCQGbNG6Az8S8B1HnWDbVfmOTPyzi+TqPj06huRkSIjGeIODQTeV56Omhx2paxrQ8wuLKlsM3eoX4sQgMXMKdwQwsuebIyBi/tk/9uZS5cIT5PZX1S2ykuRtFKPWO0X+k/WMcSp54h8icdyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717138684; c=relaxed/simple; bh=P/Nh/oo/uWjDFwH5OIXq+nZf5Rwf9DCbobbRc0hNR4Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KAU14p6hEdJFb6RDhYeOvnVW1LEoFHRxNa1Y6SYAFFvW5qgH459Hno2yaLrMRBTyyz4Iv4G9a3X+HpfvPgzdkxF1DNOg/1Bu7itJ/38mV8AL2uuSJ2JVr8QHlPMg8K1YZDmx1jZwaKQa1V/x+i28ke5ZG8nWngVgNvS0Ue7Wk5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=qLFZL8Oa; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="qLFZL8Oa" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-52b840cfecdso961600e87.3 for ; Thu, 30 May 2024 23:58:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717138680; x=1717743480; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Aj2UABYkbAgBpbHbr7DMq3bJIVwbBa4OlR1Ztoek3y0=; b=qLFZL8OaEYfWJzw1hhVFCGTaS9XJnTpP/kfNkcdwke2DzQ/xK6UO+M/drY8v6jTuTs 420ph9xdSSwrM29zMj0+8dmVDkJK476BleKH4ONPQCjqaWrjWFO7jg1GNDZY6epWgp8Y y5nAaIH/3un3zqp92AmuU5PXedM5oUlmUWc63xR3ZT31BwjAWylP6npi8GOX99/MtvRI yD6Td9qFErln7KrcMppYpgX0fqaIAj044pMjbnv20NpSj3lWbHCTtZwvHLERVqPtsRzy rFLjzp9RRUD5elUpyf5Q757/QF/2ciWCku8sKgfAx5HCuqRAIjStxxswRiYF/2G727A3 GALA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717138680; x=1717743480; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Aj2UABYkbAgBpbHbr7DMq3bJIVwbBa4OlR1Ztoek3y0=; b=bmEnA7F1v3FBTFQfhbSWwMMRkmYmVtljHbWns0jjJZgO6RrSZPnHLrOHjj/Q2FPBP5 6Rn+IwDf9kcmyBhk0iUvsZYKCmy9WWNq09aD6mjR4NLMQ5jb4V0+nkUj8n7gtnVa/ZGJ 03IKpBRlbmNFA3suo2uYbsFtMr22fM/GHEHlslLLe8oJJKJuDTuv71CFGu/+ED4hJgPF ymf8DInlb5DdkzstylxAO4/apXQaPB7VR/WDoPt2D6dpSYvXj6f5Bl0dfI9guLlTwtSX FB+5DVw//nCsrKgUJmVTwY7I3SLJMzYWBRNFazC1vW06eeOUdaohElyGB39eYtr6urIx fdbA== X-Forwarded-Encrypted: i=1; AJvYcCUEfKu9tX9F4QVx5zMHAaMhxX34mZCPosSQ6tDT8HHkv20zu2kCZKPrhGLEzZ8zwFs6z0MSSDVKboG+EyICod5JfJYyTLtrg798TEjL X-Gm-Message-State: AOJu0Yx0RrUnWa3sW7nQON0AZisapgl9YbFRm4n2RVCI5PKejCqpdH63 vwTb6D3AJdF5Q4ysnLFUSIJmd6jUsbaVWU78GQSHsPjlYtrumippLW+ZsjMxnDE= X-Google-Smtp-Source: AGHT+IEqTQ1CoXHVdILVikoDJEE4QrnRUwB4YwEvkNHAV0G0a99ZA1sEqFbBm+11Xk8uIfDtFIyPKg== X-Received: by 2002:ac2:599a:0:b0:52b:6921:4fd9 with SMTP id 2adb3069b0e04-52b896c7ab6mr508765e87.50.1717138680288; Thu, 30 May 2024 23:58:00 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.157]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a67e73fc1a5sm54205566b.53.2024.05.30.23.57.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 23:57:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: wim@linux-watchdog.org, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com Cc: biju.das.jz@bp.renesas.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, claudiu.beznea.uj@bp.renesas.com Subject: [PATCH v9 7/9] watchdog: rzg2l_wdt: Rely on the reset driver for doing proper reset Date: Fri, 31 May 2024 09:57:21 +0300 Message-Id: <20240531065723.1085423-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240531065723.1085423-1-claudiu.beznea.uj@bp.renesas.com> References: <20240531065723.1085423-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The reset driver has been adapted in commit da235d2fac21 ("clk: renesas: rzg2l: Check reset monitor registers") to check the reset monitor bits before declaring reset asserts/de-asserts as successful/failure operations. With that, there is no need to keep the reset workaround for RZ/V2M in place in the watchdog driver. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel Reviewed-by: Guenter Roeck --- Changes in v9: - collected Guenter's Rb tag Changes in v8: - none Changes in v7: - none Changes in v6: - none Changes in v5: - none Changes in v4: - collected tag Changes in v3: - none Changes in v2: - none drivers/watchdog/rzg2l_wdt.c | 39 ++++-------------------------------- 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c index 1f013dfd3c97..d77290f7fdea 100644 --- a/drivers/watchdog/rzg2l_wdt.c +++ b/drivers/watchdog/rzg2l_wdt.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -54,35 +53,11 @@ struct rzg2l_wdt_priv { struct reset_control *rstc; unsigned long osc_clk_rate; unsigned long delay; - unsigned long minimum_assertion_period; struct clk *pclk; struct clk *osc_clk; enum rz_wdt_type devtype; }; =20 -static int rzg2l_wdt_reset(struct rzg2l_wdt_priv *priv) -{ - int err, status; - - if (priv->devtype =3D=3D WDT_RZV2M) { - /* WDT needs TYPE-B reset control */ - err =3D reset_control_assert(priv->rstc); - if (err) - return err; - ndelay(priv->minimum_assertion_period); - err =3D reset_control_deassert(priv->rstc); - if (err) - return err; - err =3D read_poll_timeout(reset_control_status, status, - status !=3D 1, 0, 1000, false, - priv->rstc); - } else { - err =3D reset_control_reset(priv->rstc); - } - - return err; -} - static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv) { /* delay timer when change the setting register */ @@ -189,13 +164,12 @@ static int rzg2l_wdt_restart(struct watchdog_device *= wdev, unsigned long action, void *data) { struct rzg2l_wdt_priv *priv =3D watchdog_get_drvdata(wdev); + int ret; =20 clk_prepare_enable(priv->pclk); clk_prepare_enable(priv->osc_clk); =20 if (priv->devtype =3D=3D WDT_RZG2L) { - int ret; - ret =3D reset_control_deassert(priv->rstc); if (ret) return ret; @@ -207,7 +181,9 @@ static int rzg2l_wdt_restart(struct watchdog_device *wd= ev, rzg2l_wdt_write(priv, PEEN_FORCE, PEEN); } else { /* RZ/V2M doesn't have parity error registers */ - rzg2l_wdt_reset(priv); + ret =3D reset_control_reset(priv->rstc); + if (ret) + return ret; =20 wdev->timeout =3D 0; =20 @@ -299,13 +275,6 @@ static int rzg2l_wdt_probe(struct platform_device *pde= v) =20 priv->devtype =3D (uintptr_t)of_device_get_match_data(dev); =20 - if (priv->devtype =3D=3D WDT_RZV2M) { - priv->minimum_assertion_period =3D RZV2M_A_NSEC + - 3 * F2CYCLE_NSEC(pclk_rate) + 5 * - max(F2CYCLE_NSEC(priv->osc_clk_rate), - F2CYCLE_NSEC(pclk_rate)); - } - pm_runtime_enable(&pdev->dev); =20 priv->wdev.info =3D &rzg2l_wdt_ident; --=20 2.39.2