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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240531-x1e80100-dts-fixes-pcie6a-v1-1-1573ebcae1e8@linaro.org> References: <20240531-x1e80100-dts-fixes-pcie6a-v1-0-1573ebcae1e8@linaro.org> In-Reply-To: <20240531-x1e80100-dts-fixes-pcie6a-v1-0-1573ebcae1e8@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1335; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=5jcWigQIeXCdf4Gov9gW8hB/yw2QeIeOgRPM6wsehtQ=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBmWgI0OZvnhzv8jJBrne721q2q+1gqSu6+ylkFB udHFy+JlLWJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZloCNAAKCRAbX0TJAJUV VtO7D/9Y6mlTgcMvIDRrrO4vcsqGtYzCHmA7EYdWVFtriqKJp7eW4fI9jVkHRQuyJlqJkdRzM6q pcoOeqvGH7G5SBxobQTIX/9ZO447qNgE9jSN4teUHndp6w2XTHNoXTbp41WuKA3Wtwkk25PLoEJ 5tGWso7MX6Ahxz1CvC6g+kOdZ3m24Nzngjot3rQmrmlarata5rgD3L1WGAm+mE5bkrAu5nJT4Uz V8pDGhBpJReeq5/0DUWkUUyyxDMhIYVqY0G+Vxun2pQnB/v62NKIpIkcl+/CioxXVSTk4jRdTkK 3fCqOb9OKG6xK3RU4hyAKMlMF1GnPMVWFLN/kHc9ApSi7XvfxjPHFWUugAhkzgWZAjBtBA2AelU LThVZVAE7fT45glPqZgp5XzURDe/nlVmEy2PVExKsbBoi0zrCCiSDWMJBddAQgomh9rO3qhFryd N2vgd9z9yn7BemZSQGaJGaCPO9FwdOrrtPgs7Btz09BBI2kxPb2CO9Wr/U9GHOT2U85kxguU1ZE Q1x1LIu/77WJLfiXGVwy7p9UW8bcl1BnRm72u9XDP14VKBbNMks9cYdU067L5mqeYYzwb/lphNy SA6ge6VW+cIF6HR9DcPga+Y1UqjcpVejWPt/FPbaJTM9ZIgrRZlod5XjJOkMe0khrriIe0/PVmP pO5rEoh65Cv0c1Q== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The actual size of the DBI region is 0xf20 and the start of the ELBI region is 0xf40, according to the documentation. So fix them. While at it, add the MHI region as well. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index cf8d8d5b1870..fe7ca2a73f9d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2818,15 +2818,17 @@ pcie6a: pci@1bf8000 { device_type =3D "pci"; compatible =3D "qcom,pcie-x1e80100"; reg =3D <0 0x01bf8000 0 0x3000>, - <0 0x70000000 0 0xf1d>, - <0 0x70000f20 0 0xa8>, + <0 0x70000000 0 0xf20>, + <0 0x70000f40 0 0xa8>, <0 0x70001000 0 0x1000>, - <0 0x70100000 0 0x100000>; + <0 0x70100000 0 0x100000>, + <0 0x01bfb000 0 0x1000>; reg-names =3D "parf", "dbi", "elbi", "atu", - "config"; + "config", + "mhi"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, --=20 2.34.1 From nobody Fri Feb 13 06:09:24 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F63D171E4D for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE So the PCIe 6 can be configured in 4-lane mode or 2-lane mode. For 4-lane mode, it fetches the lanes provided by PCIe 6b. For 2-lane mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. Configure it in 4-lane mode and then each board can configure it depending on the design. Both the QCP and CRD boards, currently upstream, use the 6a for NVMe in 4-lane mode. Also, mark the controller as 4-lane as well. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index fe7ca2a73f9d..17e4c5cda22d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2838,7 +2838,7 @@ pcie6a: pci@1bf8000 { dma-coherent; =20 linux,pci-domain =3D <7>; - num-lanes =3D <2>; + num-lanes =3D <4>; =20 interrupts =3D , , @@ -2903,19 +2903,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, }; =20 pcie6a_phy: phy@1bfc000 { - compatible =3D "qcom,x1e80100-qmp-gen4x2-pcie-phy"; - reg =3D <0 0x01bfc000 0 0x2000>; + compatible =3D "qcom,x1e80100-qmp-gen4x4-pcie-phy"; + reg =3D <0 0x01bfc000 0 0x2000>, + <0 0x01bfe000 0 0x2000>; =20 clocks =3D <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_6A_PIPE_CLK>; + <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; clock-names =3D "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + "pipe", + "pipediv2"; =20 resets =3D <&gcc GCC_PCIE_6A_PHY_BCR>, <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; @@ -2927,6 +2929,8 @@ pcie6a_phy: phy@1bfc000 { =20 power-domains =3D <&gcc GCC_PCIE_6_PHY_GDSC>; =20 + qcom,4ln-config-sel =3D <&tcsr 0x1a000 0>; + #clock-cells =3D <0>; clock-output-names =3D "pcie6a_pipe_clk"; =20 --=20 2.34.1