From nobody Sun Feb 8 19:11:53 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20B1F20EB for ; Thu, 30 May 2024 00:17:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717028258; cv=none; b=EwL6l22nmnVIx1JGPCjwxi2tyLbhThLA9QQW6pwCqMAIFNF/CCUciqYOIbRR/ccpqFo/tb1rBFOIQJoWw2Y1VlrpfL/+4QGzks/Y0LVfIOU+Egtqg1KKx5lOijkaaiy3zlQeNi7W8La6kFne9yph6vHtuH6VY2Z5YDCEKfD28uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717028258; c=relaxed/simple; bh=5Kwe/U7PxVluGsCYFpMPZL03B/JZXYv8/BfkMbqTtoU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WbVi4ekjaIMcx9zUCSTQMQzo4b8iRNiARNOctAmQdEG5tHowHotHj4kG7BZNJXzycUCUlRW47ez6Yt3JdSr6AxY11ptSPpEmWjHZwtpaNxWvKc8L2wzF6dFmrr+pPC2AY7oLwN5KnlEMCFKetjuNA8TRCxNrWY4nEOJojAm5ydA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=IoyQ5TPv; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="IoyQ5TPv" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6f8e9878514so283188b3a.1 for ; Wed, 29 May 2024 17:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717028256; x=1717633056; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iGEn7Dcpmrkm/qCwkDxBmXXDS+7v8jGlOPv5lWfc4rI=; b=IoyQ5TPvCb2/+BRu/01JNWfp9xi1CPdxlLw11h1BkrDhdDcPXptoxr81kvyBNrr+bV yCSFVdQWkml8f2/QBjgz5CSiZl6jwJWOvDfUzTnJKyNEgwZUEiJBfJ6iYijEFiSCvCQA A7merkOUVk4MEN14gjdXuxf9xORlT/rgzHVzo09AtOky6n/R2wx1hb198pHqxj4/mBA2 w0Iu54ahOnvnUlSIp8Un9vecUEn9fOdflf8xrMwZV9LtSrBvt8/AL3rNE/mheaCtDeps RLKC2A0dTxpGMWoqMGtaqQpgKl7gXGVEQeiKSL4JiYn6S2OLyy9lUnXl3LLfKQTp4QPv Hedg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717028256; x=1717633056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iGEn7Dcpmrkm/qCwkDxBmXXDS+7v8jGlOPv5lWfc4rI=; b=fH1HfG4TdThKVCjnmZvq2aQ1YSy3w4CWYUBnVA+S+XQ3bX6nd4W+/pJwFEC2MtJwvL u3ZvtBKtA/GkQC/JXuTwxdobzvc55hixYe4BLadVugaDssF97lvY6CfwZCf1XxPJE+Z/ GNnVe0mRhSotQ7asoG7/YkjJaZKiqtR4y1oYW69m7lqxyly48JekVX7aPac3vHlWnmld jYurK7yLMLC1LuM41XABVGdO5OEYglXJGTQxLq4D69SyHz0vlWRLLAL24PxjDu6jfFt7 Q+7Wubg3hc5eLgMPzAYkcUVW2UU7bBJmOUU3awajumBTXF6/80Esgy2y2hXh5dJIH+So ZI9A== X-Gm-Message-State: AOJu0YwWglj72WcIPQm+TTQ5NIdTBGuqJ5W6ti5Ibdrk6qbmrK6y3yEP rgtKGqdIWZ3qBcS8z8UeuDlhU5VFx5Y3tIHEHOis1+kHZdGrqvhL7BiX5F5jQY8= X-Google-Smtp-Source: AGHT+IE028Zs3GXZwzDr0NEuUh/9Ff7JfEC5B6eJ6oSGemUdfJZybhS0OU9JqpK9c78Xe9tkO4uwlA== X-Received: by 2002:a05:6a20:158f:b0:1af:cd4a:1e1d with SMTP id adf61e73a8af0-1b26470f21bmr645349637.40.1717028256348; Wed, 29 May 2024 17:17:36 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1a776e206sm432171a91.20.2024.05.29.17.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 17:17:35 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt Cc: linux-kernel@vger.kernel.org, Andy Chiu , linux-riscv@lists.infradead.org, Matthew Bystrin , Sami Tolvanen , Samuel Holland Subject: [PATCH 1/4] riscv: Fix 32-bit call_on_irq_stack() frame pointer ABI Date: Wed, 29 May 2024 17:15:56 -0700 Message-ID: <20240530001733.1407654-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240530001733.1407654-1-samuel.holland@sifive.com> References: <20240530001733.1407654-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" call_on_irq_stack() uses struct member offsets to set up its link in the frame record list. On riscv32, `struct stackframe` is the wrong size to maintain stack pointer alignment, so STACKFRAME_SIZE_ON_STACK includes padding. However, the ABI requires the frame record to be placed immediately below the address stored in s0, so the padding must come before the struct members. Fix the layout by making STACKFRAME_FP and STACKFRAME_RA the negative offsets from s0, instead of the positive offsets from sp. Fixes: 82982fdd5133 ("riscv: Deduplicate IRQ stack switching") Signed-off-by: Samuel Holland --- arch/riscv/kernel/asm-offsets.c | 4 ++-- arch/riscv/kernel/entry.S | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index b09ca5f944f7..84c056f5ee09 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -487,8 +487,8 @@ void asm_offsets(void) OFFSET(SBI_HART_BOOT_STACK_PTR_OFFSET, sbi_hart_boot_data, stack_ptr); =20 DEFINE(STACKFRAME_SIZE_ON_STACK, ALIGN(sizeof(struct stackframe), STACK_A= LIGN)); - OFFSET(STACKFRAME_FP, stackframe, fp); - OFFSET(STACKFRAME_RA, stackframe, ra); + DEFINE(STACKFRAME_FP, offsetof(struct stackframe, fp) - sizeof(struct sta= ckframe)); + DEFINE(STACKFRAME_RA, offsetof(struct stackframe, ra) - sizeof(struct sta= ckframe)); =20 #ifdef CONFIG_DYNAMIC_FTRACE_WITH_ARGS DEFINE(FREGS_SIZE_ON_STACK, ALIGN(sizeof(struct ftrace_regs), STACK_ALIGN= )); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 68a24cf9481a..4c5b22cb7381 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -246,8 +246,8 @@ SYM_CODE_END(ret_from_fork) SYM_FUNC_START(call_on_irq_stack) /* Create a frame record to save ra and s0 (fp) */ addi sp, sp, -STACKFRAME_SIZE_ON_STACK - REG_S ra, STACKFRAME_RA(sp) - REG_S s0, STACKFRAME_FP(sp) + REG_S ra, (STACKFRAME_SIZE_ON_STACK + STACKFRAME_RA)(sp) + REG_S s0, (STACKFRAME_SIZE_ON_STACK + STACKFRAME_FP)(sp) addi s0, sp, STACKFRAME_SIZE_ON_STACK =20 /* Switch to the per-CPU shadow call stack */ @@ -265,8 +265,8 @@ SYM_FUNC_START(call_on_irq_stack) =20 /* Switch back to the thread stack and restore ra and s0 */ addi sp, s0, -STACKFRAME_SIZE_ON_STACK - REG_L ra, STACKFRAME_RA(sp) - REG_L s0, STACKFRAME_FP(sp) + REG_L ra, (STACKFRAME_SIZE_ON_STACK + STACKFRAME_RA)(sp) + REG_L s0, (STACKFRAME_SIZE_ON_STACK + STACKFRAME_FP)(sp) addi sp, sp, STACKFRAME_SIZE_ON_STACK =20 ret --=20 2.44.1 From nobody Sun Feb 8 19:11:53 2026 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D3654C66 for ; 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Wed, 29 May 2024 17:17:37 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1a776e206sm432171a91.20.2024.05.29.17.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 17:17:37 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt Cc: linux-kernel@vger.kernel.org, Andy Chiu , linux-riscv@lists.infradead.org, Matthew Bystrin , Sami Tolvanen , Samuel Holland Subject: [PATCH 2/4] riscv: entry: Balance vector context nesting Date: Wed, 29 May 2024 17:15:57 -0700 Message-ID: <20240530001733.1407654-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240530001733.1407654-1-samuel.holland@sifive.com> References: <20240530001733.1407654-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Vector context management is the last thing done before jumping to C code, so it should be the first thing done after returning from C code. This also improves efficiency: riscv_v_context_nesting_end() clobbers the saved value of the status CSR, so currently ret_from_exception() must reload it. This is not necessary if riscv_v_context_nesting_end() is called first. Signed-off-by: Samuel Holland --- arch/riscv/kernel/entry.S | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 4c5b22cb7381..d13d1aad7649 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -120,6 +120,11 @@ ASM_NOKPROBE(handle_exception) * - ret_from_fork */ SYM_CODE_START_NOALIGN(ret_from_exception) +#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE + move a0, sp + call riscv_v_context_nesting_end +#endif + REG_L s0, PT_STATUS(sp) #ifdef CONFIG_RISCV_M_MODE /* the MPP value is too large to be used as an immediate arg for addi */ @@ -143,10 +148,6 @@ SYM_CODE_START_NOALIGN(ret_from_exception) */ csrw CSR_SCRATCH, tp 1: -#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE - move a0, sp - call riscv_v_context_nesting_end -#endif REG_L a0, PT_STATUS(sp) /* * The current load reservation is effectively part of the processor's --=20 2.44.1 From nobody Sun Feb 8 19:11:53 2026 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0A85B65A for ; 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Wed, 29 May 2024 17:17:38 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1a776e206sm432171a91.20.2024.05.29.17.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 17:17:38 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt Cc: linux-kernel@vger.kernel.org, Andy Chiu , linux-riscv@lists.infradead.org, Matthew Bystrin , Sami Tolvanen , Samuel Holland Subject: [PATCH 3/4] riscv: entry: Do not clobber the frame pointer Date: Wed, 29 May 2024 17:15:58 -0700 Message-ID: <20240530001733.1407654-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240530001733.1407654-1-samuel.holland@sifive.com> References: <20240530001733.1407654-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" s0 is reserved for the frame pointer, so it should not be used as a temporary register. Clobbering the frame pointer breaks stack traces. - In handle_exception() and ret_from_exception(), use a2 for the saved stack pointer. a2 is chosen because r2 is the stack pointer register. - In ret_from_exception(), use s1 for the saved status CSR value. Avoid clobbering s1 in the privilege mode check so it does not need to be reloaded later in the function. - Use s1 and s2 in ret_from_fork() instead of s0 and s1. The entire p->thread.s array is zeroed at the beginning of copy_thread(), so the registers do not need to be zeroed separately for kernel threads. Signed-off-by: Samuel Holland Reviewed-by: Andy Chiu --- arch/riscv/kernel/entry.S | 29 ++++++++++++++--------------- arch/riscv/kernel/process.c | 5 ++--- 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index d13d1aad7649..bd1c5621df45 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -58,13 +58,13 @@ SYM_CODE_START(handle_exception) */ li t0, SR_SUM | SR_FS_VS =20 - REG_L s0, TASK_TI_USER_SP(tp) + REG_L a2, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 csrr s2, CSR_EPC csrr s3, CSR_TVAL csrr s4, CSR_CAUSE csrr s5, CSR_SCRATCH - REG_S s0, PT_SP(sp) + REG_S a2, PT_SP(sp) REG_S s1, PT_STATUS(sp) REG_S s2, PT_EPC(sp) REG_S s3, PT_BADADDR(sp) @@ -125,19 +125,19 @@ SYM_CODE_START_NOALIGN(ret_from_exception) call riscv_v_context_nesting_end #endif =20 - REG_L s0, PT_STATUS(sp) + REG_L s1, PT_STATUS(sp) #ifdef CONFIG_RISCV_M_MODE /* the MPP value is too large to be used as an immediate arg for addi */ li t0, SR_MPP - and s0, s0, t0 + and t0, s1, t0 #else - andi s0, s0, SR_SPP + andi t0, s1, SR_SPP #endif - bnez s0, 1f + bnez t0, 1f =20 /* Save unwound kernel stack pointer in thread_info */ - addi s0, sp, PT_SIZE_ON_STACK - REG_S s0, TASK_TI_KERNEL_SP(tp) + addi t0, sp, PT_SIZE_ON_STACK + REG_S t0, TASK_TI_KERNEL_SP(tp) =20 /* Save the kernel shadow call stack pointer */ scs_save_current @@ -148,7 +148,6 @@ SYM_CODE_START_NOALIGN(ret_from_exception) */ csrw CSR_SCRATCH, tp 1: - REG_L a0, PT_STATUS(sp) /* * The current load reservation is effectively part of the processor's * state, in the sense that load reservations cannot be shared between @@ -169,7 +168,7 @@ SYM_CODE_START_NOALIGN(ret_from_exception) REG_L a2, PT_EPC(sp) REG_SC x0, a2, PT_EPC(sp) =20 - csrw CSR_STATUS, a0 + csrw CSR_STATUS, s1 csrw CSR_EPC, a2 =20 REG_L x1, PT_RA(sp) @@ -207,13 +206,13 @@ SYM_CODE_START_LOCAL(handle_kernel_stack_overflow) REG_S x5, PT_T0(sp) save_from_x6_to_x31 =20 - REG_L s0, TASK_TI_KERNEL_SP(tp) + REG_L a2, TASK_TI_KERNEL_SP(tp) csrr s1, CSR_STATUS csrr s2, CSR_EPC csrr s3, CSR_TVAL csrr s4, CSR_CAUSE csrr s5, CSR_SCRATCH - REG_S s0, PT_SP(sp) + REG_S a2, PT_SP(sp) REG_S s1, PT_STATUS(sp) REG_S s2, PT_EPC(sp) REG_S s3, PT_BADADDR(sp) @@ -227,10 +226,10 @@ ASM_NOKPROBE(handle_kernel_stack_overflow) =20 SYM_CODE_START(ret_from_fork) call schedule_tail - beqz s0, 1f /* not from kernel thread */ + beqz s1, 1f /* not from kernel thread */ /* Call fn(arg) */ - move a0, s1 - jalr s0 + move a0, s2 + jalr s1 1: move a0, sp /* pt_regs */ la ra, ret_from_exception diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e4bc61c4e58a..5512c31e1256 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -208,8 +208,8 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) /* Supervisor/Machine, irqs on: */ childregs->status =3D SR_PP | SR_PIE; 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Wed, 29 May 2024 17:17:40 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1a776e206sm432171a91.20.2024.05.29.17.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 17:17:39 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt Cc: linux-kernel@vger.kernel.org, Andy Chiu , linux-riscv@lists.infradead.org, Matthew Bystrin , Sami Tolvanen , Samuel Holland Subject: [PATCH 4/4] riscv: entry: Save a frame record for exceptions Date: Wed, 29 May 2024 17:15:59 -0700 Message-ID: <20240530001733.1407654-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240530001733.1407654-1-samuel.holland@sifive.com> References: <20240530001733.1407654-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This follows the frame pointer ABI and allows stack traces to cross exception boundaries without a special case in the stack walking code. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/processor.h | 9 +++++++-- arch/riscv/include/asm/ptrace.h | 5 +++++ arch/riscv/include/asm/stacktrace.h | 5 ----- arch/riscv/kernel/asm-offsets.c | 6 +++--- arch/riscv/kernel/entry.S | 16 ++++++++++------ arch/riscv/kernel/head.S | 6 ++---- arch/riscv/kernel/stacktrace.c | 9 --------- 7 files changed, 27 insertions(+), 29 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 68c3432dc6ea..ccbb1e363c7f 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -144,9 +144,14 @@ static inline void arch_thread_struct_whitelist(unsign= ed long *offset, .align_ctl =3D PR_UNALIGN_NOPRINT, \ } =20 +#ifdef CONFIG_FRAME_POINTER +#define EXCEPTION_FRAME_SIZE ALIGN(sizeof(struct pt_regs) + sizeof(struct = stackframe), STACK_ALIGN) +#else +#define EXCEPTION_FRAME_SIZE ALIGN(sizeof(struct pt_regs), STACK_ALIGN) +#endif + #define task_pt_regs(tsk) \ - ((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \ - - ALIGN(sizeof(struct pt_regs), STACK_ALIGN))) + ((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE - EXCEPTION_FRAME_= SIZE)) =20 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrac= e.h index b5b0adcc85c1..f475f6acec49 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -12,6 +12,11 @@ =20 #ifndef __ASSEMBLY__ =20 +struct stackframe { + unsigned long fp; + unsigned long ra; +}; + struct pt_regs { unsigned long epc; unsigned long ra; diff --git a/arch/riscv/include/asm/stacktrace.h b/arch/riscv/include/asm/s= tacktrace.h index b1495a7e06ce..3019558f747c 100644 --- a/arch/riscv/include/asm/stacktrace.h +++ b/arch/riscv/include/asm/stacktrace.h @@ -6,11 +6,6 @@ #include #include =20 -struct stackframe { - unsigned long fp; - unsigned long ra; -}; - extern void notrace walk_stackframe(struct task_struct *task, struct pt_re= gs *regs, bool (*fn)(void *, unsigned long), void *arg); extern void dump_backtrace(struct pt_regs *regs, struct task_struct *task, diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index 84c056f5ee09..582b52713e93 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -477,10 +477,10 @@ void asm_offsets(void) ); =20 /* - * We allocate a pt_regs on the stack when entering the kernel. This - * ensures the alignment is sane. + * We allocate a pt_regs and possibly a stackframe on the stack when + * entering the kernel. This ensures the alignment is sane. */ - DEFINE(PT_SIZE_ON_STACK, ALIGN(sizeof(struct pt_regs), STACK_ALIGN)); + DEFINE(EXCEPTION_FRAME_SIZE, EXCEPTION_FRAME_SIZE); =20 OFFSET(KERNEL_MAP_VIRT_ADDR, kernel_mapping, virt_addr); OFFSET(SBI_HART_BOOT_TASK_PTR_OFFSET, sbi_hart_boot_data, task_ptr); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index bd1c5621df45..cdb58ce32cbb 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -33,7 +33,7 @@ SYM_CODE_START(handle_exception) REG_S sp, TASK_TI_KERNEL_SP(tp) =20 #ifdef CONFIG_VMAP_STACK - addi sp, sp, -(PT_SIZE_ON_STACK) + addi sp, sp, -EXCEPTION_FRAME_SIZE srli sp, sp, THREAD_SHIFT andi sp, sp, 0x1 bnez sp, handle_kernel_stack_overflow @@ -43,7 +43,7 @@ SYM_CODE_START(handle_exception) .Lsave_context: REG_S sp, TASK_TI_USER_SP(tp) REG_L sp, TASK_TI_KERNEL_SP(tp) - addi sp, sp, -(PT_SIZE_ON_STACK) + addi sp, sp, -EXCEPTION_FRAME_SIZE REG_S x1, PT_RA(sp) REG_S x3, PT_GP(sp) REG_S x5, PT_T0(sp) @@ -83,6 +83,12 @@ SYM_CODE_START(handle_exception) /* Load the kernel shadow call stack pointer if coming from userspace */ scs_load_current_if_task_changed s5 =20 +#ifdef CONFIG_FRAME_POINTER + REG_S ra, (EXCEPTION_FRAME_SIZE + STACKFRAME_RA)(sp) + REG_S s0, (EXCEPTION_FRAME_SIZE + STACKFRAME_FP)(sp) + addi s0, sp, EXCEPTION_FRAME_SIZE +#endif + #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE move a0, sp call riscv_v_context_nesting_start @@ -136,7 +142,7 @@ SYM_CODE_START_NOALIGN(ret_from_exception) bnez t0, 1f =20 /* Save unwound kernel stack pointer in thread_info */ - addi t0, sp, PT_SIZE_ON_STACK + addi t0, sp, EXCEPTION_FRAME_SIZE REG_S t0, TASK_TI_KERNEL_SP(tp) =20 /* Save the kernel shadow call stack pointer */ @@ -192,14 +198,12 @@ SYM_CODE_START_LOCAL(handle_kernel_stack_overflow) /* we reach here from kernel context, sscratch must be 0 */ csrrw x31, CSR_SCRATCH, x31 asm_per_cpu sp, overflow_stack, x31 - li x31, OVERFLOW_STACK_SIZE + li x31, OVERFLOW_STACK_SIZE - EXCEPTION_FRAME_SIZE add sp, sp, x31 /* zero out x31 again and restore x31 */ xor x31, x31, x31 csrrw x31, CSR_SCRATCH, x31 =20 - addi sp, sp, -(PT_SIZE_ON_STACK) - //save context to overflow stack REG_S x1, PT_RA(sp) REG_S x3, PT_GP(sp) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..09ee5e6c2a98 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -290,9 +290,8 @@ SYM_CODE_START(_start_kernel) =20 /* Initialize page tables and relocate to virtual addresses */ la tp, init_task - la sp, init_thread_union + THREAD_SIZE + la sp, init_thread_union + THREAD_SIZE - EXCEPTION_FRAME_SIZE XIP_FIXUP_OFFSET sp - addi sp, sp, -PT_SIZE_ON_STACK scs_load_init_stack #ifdef CONFIG_BUILTIN_DTB la a0, __dtb_start @@ -310,8 +309,7 @@ SYM_CODE_START(_start_kernel) call .Lsetup_trap_vector /* Restore C environment */ la tp, init_task - la sp, init_thread_union + THREAD_SIZE - addi sp, sp, -PT_SIZE_ON_STACK + la sp, init_thread_union + THREAD_SIZE - EXCEPTION_FRAME_SIZE scs_load_current =20 #ifdef CONFIG_KASAN diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c index 528ec7cc9a62..6be8f8942f6b 100644 --- a/arch/riscv/kernel/stacktrace.c +++ b/arch/riscv/kernel/stacktrace.c @@ -16,8 +16,6 @@ =20 #ifdef CONFIG_FRAME_POINTER =20 -extern asmlinkage void ret_from_exception(void); - static inline int fp_is_valid(unsigned long fp, unsigned long sp) { unsigned long low, high; @@ -70,13 +68,6 @@ void notrace walk_stackframe(struct task_struct *task, s= truct pt_regs *regs, fp =3D frame->fp; pc =3D ftrace_graph_ret_addr(current, NULL, frame->ra, &frame->ra); - if (pc =3D=3D (unsigned long)ret_from_exception) { - if (unlikely(!__kernel_text_address(pc) || !fn(arg, pc))) - break; - - pc =3D ((struct pt_regs *)sp)->epc; - fp =3D ((struct pt_regs *)sp)->s0; - } } =20 } --=20 2.44.1