From nobody Wed Dec 17 04:16:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12FF317A938; Wed, 29 May 2024 10:01:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716976878; cv=none; b=pSox/dwK0HXeoeVMg1C/3OB0rAzOHGHnkjFs35m6wxKUpukEVL9QZHb8rJE9x28OQtzbEWciAyOn3QxNUH9HWiiT13JAaVf85M5w9i/mCKlLxOep026c9wZALmDSVMOED3eHgxVa/rDvjJhYXoC7XU4cLB+3UBzl1sgPg3HWRzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716976878; c=relaxed/simple; bh=8ZKgQ6HDURS9lZbhYYRP1FlK44swQk44vF9iL4f8vjg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iSr3eSyVuVNGL8OZHx3M59c5hGxXno0SXhG/uWJ5vp7CkzaJp6TKdOzCuS/1csGcUBZky29f6jE/5pKdJW2O5so24ZTKOXgVZ01/ubEYBQ11/OZC6yQOGtjS3xYizZ9JY5kDDILIcSZDEqeOKWgQMVJs421fK0dMKt1pz2WjWZ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=omxfpRCS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="omxfpRCS" Received: by smtp.kernel.org (Postfix) with ESMTPS id B57EBC32786; Wed, 29 May 2024 10:01:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716976877; bh=8ZKgQ6HDURS9lZbhYYRP1FlK44swQk44vF9iL4f8vjg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=omxfpRCS+BoYU6p579+U4qWBBrimrfNMcdYqj6k0zG8ZD4dZiNo7tckkZrS6wqQs0 ZnBOVPh8hsXqB3hwX/mMzNliZyTNIG9nQ53fn+Xjw3BGfWeQol8DeKtBpc3/rEzu8P V6EQe0oVeD8PZwjz17lIqvK36Eeg2s3Ykr2lwxghLhpEfROmg24at2q+VkEhbWl0fp zIUBDGmTd4GnHRM0vuvLMCLg7Uaxn3WvzN72LWzQKw5DV3zyOsvUbgAojredWDHiGt 0JM2arRfjgerXzUFSfYNnRtv5yK3keQ+NYqJJhi3kouXZDWOviFkej2yL9KXLDQ1Gb TEUJuZPB74R2A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F917C27C44; Wed, 29 May 2024 10:01:17 +0000 (UTC) From: Kelvin Zhang via B4 Relay Date: Wed, 29 May 2024 18:00:56 +0800 Subject: [PATCH v6 1/2] pwm: meson: Add support for Amlogic S4 PWM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240529-s4-pwm-v6-1-270f63049f20@amlogic.com> References: <20240529-s4-pwm-v6-0-270f63049f20@amlogic.com> In-Reply-To: <20240529-s4-pwm-v6-0-270f63049f20@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kelvin Zhang , Junyi Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716976876; l=2415; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=8sG15QArjOg32TnDx5atK6muQxwE/8zIMoEGBdYsNU0=; b=xckEUtXiz+UAPnFeNXgRskIwNtR3eYtZJMf1R5mGYu+oGQ25XoliidjORSerGwmAPGCZKySzh QUO2Eb4P9uqAfJg4F3jzq1qCFNq4Zqd7I+034OIQKrlVHJB1c27Jb/b X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang Reply-To: kelvin.zhang@amlogic.com From: Junyi Zhao Add support for Amlogic S4 PWM. Signed-off-by: Junyi Zhao Signed-off-by: Kelvin Zhang --- drivers/pwm/pwm-meson.c | 49 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index b2f97dfb01bb..a513ebbb5666 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -460,6 +460,47 @@ static int meson_pwm_init_channels_meson8b_v2(struct p= wm_chip *chip) return meson_pwm_init_clocks_meson8b(chip, mux_parent_data); } =20 +static void meson_pwm_s4_put_clk(void *data) +{ + struct meson_pwm *meson =3D (struct meson_pwm *)data; + int i; + + for (i =3D 0; i < MESON_NUM_PWMS; i++) + clk_put(meson->channels[i].clk); +} + +static int meson_pwm_init_channels_s4(struct pwm_chip *chip) +{ + struct device *dev =3D pwmchip_parent(chip); + struct device_node *np =3D dev->of_node; + struct meson_pwm *meson =3D to_meson_pwm(chip); + struct meson_pwm_channel *channel; + int i, ret; + + for (i =3D 0; i < MESON_NUM_PWMS; i++) { + channel =3D &meson->channels[i]; + channel->clk =3D of_clk_get(np, i); + if (IS_ERR(channel->clk)) { + ret =3D PTR_ERR(channel->clk); + dev_err_probe(dev, ret, "Failed to get clk\n"); + goto err; + } + } + ret =3D devm_add_action_or_reset(dev, meson_pwm_s4_put_clk, meson); + if (ret) + return ret; + + return 0; + +err: + while (--i >=3D 0) { + channel =3D &meson->channels[i]; + clk_put(channel->clk); + } + + return ret; +} + static const struct meson_pwm_data pwm_meson8b_data =3D { .parent_names =3D { "xtal", NULL, "fclk_div4", "fclk_div3" }, .channels_init =3D meson_pwm_init_channels_meson8b_legacy, @@ -498,6 +539,10 @@ static const struct meson_pwm_data pwm_meson8_v2_data = =3D { .channels_init =3D meson_pwm_init_channels_meson8b_v2, }; =20 +static const struct meson_pwm_data pwm_s4_data =3D { + .channels_init =3D meson_pwm_init_channels_s4, +}; + static const struct of_device_id meson_pwm_matches[] =3D { { .compatible =3D "amlogic,meson8-pwm-v2", @@ -536,6 +581,10 @@ static const struct of_device_id meson_pwm_matches[] = =3D { .compatible =3D "amlogic,meson-g12a-ao-pwm-cd", .data =3D &pwm_g12a_ao_cd_data }, + { + .compatible =3D "amlogic,meson-s4-pwm", + .data =3D &pwm_s4_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); --=20 2.37.1 From nobody Wed Dec 17 04:16:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 499FB17B43A; Wed, 29 May 2024 10:01:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716976878; cv=none; b=OqarpbaoQYArpYBerCVe395kpyBAcVL/lDXY39sDmvFzOu+AqjM12h6laWAkyV0Nv/lLfuwoFzhRN0GIKm+M+7U47LWdNiBJ+v69vG7B2c5qgfCwW0QiXnEDwM5Io+3zBBWHZWuf+xgwHVYpCfUUfcmnOtK+/8ERCosEGvz+A8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716976878; c=relaxed/simple; bh=DbSfj2AuXO8/xPseQuTpefTqS6ELr7H0u4EGEdY+1/0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 29 May 2024 10:01:17 +0000 (UTC) From: Kelvin Zhang via B4 Relay Date: Wed, 29 May 2024 18:00:57 +0800 Subject: [PATCH v6 2/2] arm64: dts: amlogic: Add Amlogic S4 PWM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240529-s4-pwm-v6-2-270f63049f20@amlogic.com> References: <20240529-s4-pwm-v6-0-270f63049f20@amlogic.com> In-Reply-To: <20240529-s4-pwm-v6-0-270f63049f20@amlogic.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kelvin Zhang , Junyi Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716976876; l=5081; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=RZgRRkkZrEuNbz37RVEud8NVXA4UvtxkJIzerJ/86lo=; b=xA9Jcfkz9OaK0o7FzoBlFuR9bh3RN4pR/Q7QCDMFd+LQG5R6Di11LrtXUIh6+alLiioBi3N5M u1/h7PU97Z/BJvN2un2gzkOJuTMbb+eEkOLl5G+UZEmMKJbqQYsUfOD X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang Reply-To: kelvin.zhang@amlogic.com From: Junyi Zhao Add device nodes for PWM_AB, PWM_CD, PWM_EF, PWM_GH and PWM_IJ along with GPIO PIN configs of each channel. Signed-off-by: Junyi Zhao Signed-off-by: Kelvin Zhang --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 207 ++++++++++++++++++++++++++= ++++ 1 file changed, 207 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-s4.dtsi index 10896f9df682..98f554577bae 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -312,6 +312,168 @@ mux { }; }; =20 + pwm_a_pins1: pwm-a-pins1 { + mux { + groups =3D "pwm_a_d"; + function =3D "pwm_a"; + }; + }; + + pwm_a_pins2: pwm-a-pins2 { + mux { + groups =3D "pwm_a_x"; + function =3D "pwm_a"; + }; + }; + + pwm_a_pins: pwm-a-pins { + mux { + groups =3D "pwm_a_d"; + function =3D "pwm_a"; + }; + }; + + pwm_b_pins1: pwm-b-pins1 { + mux { + groups =3D "pwm_b_d"; + function =3D "pwm_b"; + }; + }; + + pwm_b_pins2: pwm-b-pins2 { + mux { + groups =3D "pwm_b_x"; + function =3D "pwm_b"; + }; + }; + + pwm_c_pins1: pwm-c-pins1 { + mux { + groups =3D "pwm_c_d"; + function =3D "pwm_c"; + }; + }; + + pwm_c_pins2: pwm-c-pins2 { + mux { + groups =3D "pwm_c_x"; + function =3D "pwm_c"; + }; + }; + + pwm_d_pins1: pwm-d-pins1 { + mux { + groups =3D "pwm_d_d"; + function =3D "pwm_d"; + }; + }; + + pwm_d_pins2: pwm-d-pins2 { + mux { + groups =3D "pwm_d_h"; + function =3D "pwm_d"; + }; + }; + + pwm_e_pins1: pwm-e-pins1 { + mux { + groups =3D "pwm_e_x"; + function =3D "pwm_e"; + drive-strength-microamp =3D <500>; + }; + }; + + pwm_e_pins2: pwm-e-pins2 { + mux { + groups =3D "pwm_e_z"; + function =3D "pwm_e"; + }; + }; + + pwm_f_pins1: pwm-f-pins1 { + mux { + groups =3D "pwm_f_x"; + function =3D "pwm_f"; + }; + }; + + pwm_f_pins2: pwm-f-pins2 { + mux { + groups =3D "pwm_f_z"; + function =3D "pwm_f"; + }; + }; + + pwm_g_pins1: pwm-g-pins1 { + mux { + groups =3D "pwm_g_d"; + function =3D "pwm_g"; + }; + }; + + pwm_g_pins2: pwm-g-pins2 { + mux { + groups =3D "pwm_g_z"; + function =3D "pwm_g"; + }; + }; + + pwm_h_pins: pwm-h-pins { + mux { + groups =3D "pwm_h"; + function =3D "pwm_h"; + }; + }; + + pwm_i_pins1: pwm-i-pins1 { + mux { + groups =3D "pwm_i_d"; + function =3D "pwm_i"; + }; + }; + + pwm_i_pins2: pwm-i-pins2 { + mux { + groups =3D "pwm_i_h"; + function =3D "pwm_i"; + }; + }; + + pwm_j_pins: pwm-j-pins { + mux { + groups =3D "pwm_j"; + function =3D "pwm_j"; + }; + }; + + pwm_a_hiz_pins: pwm-a-hiz-pins { + mux { + groups =3D "pwm_a_hiz"; + function =3D "pwm_a_hiz"; + }; + }; + + pwm_b_hiz_pins: pwm-b-hiz-pins { + mux { + groups =3D "pwm_b_hiz"; + function =3D "pwm_b_hiz"; + }; + }; + + pwm_c_hiz_pins: pwm-c-hiz-pins { + mux { + groups =3D "pwm_c_hiz"; + function =3D "pwm_b_hiz"; + }; + }; + + pwm_g_hiz_pins: pwm-g-hiz-pins { + mux { + groups =3D "pwm_g_hiz"; + function =3D "pwm_g_hiz"; + }; + }; + spicc0_pins_x: spicc0-pins_x { mux { groups =3D "spi_a_mosi_x", @@ -399,6 +561,51 @@ spicc0: spi@50000 { status =3D "disabled"; }; =20 + pwm_ab: pwm@58000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x58000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_A>, + <&clkc_periphs CLKID_PWM_B>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_cd: pwm@5a000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x5a000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_C>, + <&clkc_periphs CLKID_PWM_D>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_ef: pwm@5c000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x5c000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_E>, + <&clkc_periphs CLKID_PWM_F>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_gh: pwm@5e000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x5e000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_G>, + <&clkc_periphs CLKID_PWM_H>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm_ij: pwm@60000 { + compatible =3D "amlogic,meson-s4-pwm"; + reg =3D <0x0 0x60000 0x0 0x24>; + clocks =3D <&clkc_periphs CLKID_PWM_I>, + <&clkc_periphs CLKID_PWM_J>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + i2c0: i2c@66000 { compatible =3D "amlogic,meson-axg-i2c"; reg =3D <0x0 0x66000 0x0 0x20>; --=20 2.37.1