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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=2943; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=a+N8mpao7+QeANDnMFXYaOS/6MVQmW9fHDWrXbASce8=; b=oJuNvvc75KFtnVqOakvIcFJySZhl3GRFOsEwG9SQWUSfhhwM7G3A13Oj4W8Uz/ymTnQFDxFC8 K6AHaPrYivcClMPXvWfgkF74RG5wHhY1u6HVxiF4XekFmUGkdgZUUKv X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Various values extracted from the vendor's kernel driver. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-14-nico@fluxnic.net [Angelo: Fixed wrong nvmem-cell-names] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 35 ++++++++++++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 29d012d28edb..02786fe9891b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8188"; @@ -464,6 +465,7 @@ infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8188-infracfg-ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 pericfg: syscon@10003000 { @@ -937,6 +939,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8188-lvts-ap"; + reg =3D <0 0x1100b000 0 0xc00>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells =3D <1>; @@ -1050,6 +1063,17 @@ mmc1: mmc@11240000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8188-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + i2c0: i2c@11280000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11280000 0 0x1000>, @@ -1273,6 +1297,17 @@ imp_iic_wrap_en: clock-controller@11ec2000 { #clock-cells =3D <1>; }; =20 + efuse: efuse@11f20000 { + compatible =3D "mediatek,mt8188-efuse", "mediatek,efuse"; + reg =3D <0 0x11f20000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_efuse_data1: lvts1-calib@1ac { + reg =3D <0x1ac 0x40>; + }; + }; + gpu: gpu@13000000 { compatible =3D "mediatek,mt8188-mali", "arm,mali-valhall-jm"; reg =3D <0 0x13000000 0 0x4000>; --=20 2.37.3