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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=1871; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=7TWp6ZYqTnWbqyJ5Cw7vRGWMMiL4bndT4gl1LDFj+mw=; b=fNpJGdF1e6oIhg16Qw3yuccxDifJLORx4N3h7feO2qRv4t5zX5kGrg92RNMGZjYaq0FJMoxzr kn93J44LFi/ClblQAuQP6CjaErOlZbnOjF2/u1vbrtp9LVgiaEPecsf X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= Fix a thermal zone name for consistency with the other SoCs: MFG contains GPU, the latter is more specific and must be used here. The naming must be fixed "atomically" so compilation does not break. As a result, the change is made in the dt-bindings and in the LVTS driver within a single commit, despite the checkpatch warning. The definition can be modified safely here because it is used only in the LVTS driver, which is modified accordingly. Fixes: a2ca202350f9 ("dt-bindings: thermal: mediatek: Add LVTS thermal cont= roller definition for MT8186") Signed-off-by: Julien Panis Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/mediatek/lvts_thermal.c | 2 +- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 0bb3a495b56e..506eed52db1e 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1436,7 +1436,7 @@ static const struct lvts_ctrl_data mt8186_lvts_data_c= trl[] =3D { .cal_offsets =3D { 29, 30, 31 } }, { .dt_id =3D MT8186_ADSP, .cal_offsets =3D { 34, 35, 28 } }, - { .dt_id =3D MT8186_MFG, + { .dt_id =3D MT8186_GPU, .cal_offsets =3D { 39, 32, 33 } } }, VALID_SENSOR_MAP(1, 1, 1, 0), diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index bf95309d2525..85d25b4d726d 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -24,7 +24,7 @@ #define MT8186_BIG_CPU1 5 #define MT8186_NNA 6 #define MT8186_ADSP 7 -#define MT8186_MFG 8 +#define MT8186_GPU 8 =20 #define MT8188_MCU_LITTLE_CPU0 0 #define MT8188_MCU_LITTLE_CPU1 1 --=20 2.37.3 From nobody Thu Sep 19 23:08:02 2024 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68BD715D5A2 for ; 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Tue, 28 May 2024 22:58:05 -0700 (PDT) Received: from [127.0.1.1] ([84.102.31.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4210896676bsm169075435e9.4.2024.05.28.22.58.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 22:58:05 -0700 (PDT) From: Julien Panis Date: Wed, 29 May 2024 07:57:57 +0200 Subject: [PATCH v6 2/6] dt-bindings: thermal: mediatek: Fix thermal zone definitions for MT8188 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240529-mtk-thermal-mt818x-dtsi-v6-2-0c71478a9c37@baylibre.com> References: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> In-Reply-To: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=2646; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=0zA4K5GlKKb8X4MA0dH7F7aTDharqePLUmZ645uCgXs=; b=VpFSdaZV2QCLWhCBlT9NHY2sMDqmWzooPYogLUmvRpVxbKfVfoDy0RtLffVktFo/UV/nRLG9Q QmnS56V+dd+BYblBogVCdMLv5w82LxelJgXNlLFk5s4k5yWRFeNR4Ki X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= Fix thermal zone names for consistency with the other SoCs: - GPU0 must be used as the first GPU item. - SOCx deal with audio DSP, video, and infra subsystems. The naming must be fixed "atomically" so compilation does not break. As a result, the change is made in the dt-bindings and in the LVTS driver within a single commit, despite the checkpatch warning. The definitions can be modified safely here because they are used only in the LVTS driver, which is modified accordingly. Fixes: 78c88534e5e1 ("dt-bindings: thermal: mediatek: Add LVTS thermal cont= roller definition for MT8188") Signed-off-by: Julien Panis Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/mediatek/lvts_thermal.c | 10 +++++----- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 506eed52db1e..89fb92666b81 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1487,11 +1487,11 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_d= ata_ctrl[] =3D { }, { .lvts_sensor =3D { - { .dt_id =3D MT8188_AP_GPU1, + { .dt_id =3D MT8188_AP_GPU0, .cal_offsets =3D { 43, 44, 45 } }, - { .dt_id =3D MT8188_AP_GPU2, + { .dt_id =3D MT8188_AP_GPU1, .cal_offsets =3D { 46, 47, 48 } }, - { .dt_id =3D MT8188_AP_SOC1, + { .dt_id =3D MT8188_AP_ADSP, .cal_offsets =3D { 49, 50, 51 } }, }, VALID_SENSOR_MAP(1, 1, 1, 0), @@ -1500,9 +1500,9 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_dat= a_ctrl[] =3D { }, { .lvts_sensor =3D { - { .dt_id =3D MT8188_AP_SOC2, + { .dt_id =3D MT8188_AP_VDO, .cal_offsets =3D { 52, 53, 54 } }, - { .dt_id =3D MT8188_AP_SOC3, + { .dt_id =3D MT8188_AP_INFRA, .cal_offsets =3D { 55, 56, 57 } }, }, VALID_SENSOR_MAP(1, 1, 0, 0), diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index 85d25b4d726d..ddc7302a510a 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -34,11 +34,11 @@ #define MT8188_MCU_BIG_CPU1 5 =20 #define MT8188_AP_APU 0 -#define MT8188_AP_GPU1 1 -#define MT8188_AP_GPU2 2 -#define MT8188_AP_SOC1 3 -#define MT8188_AP_SOC2 4 -#define MT8188_AP_SOC3 5 +#define MT8188_AP_GPU0 1 +#define MT8188_AP_GPU1 2 +#define MT8188_AP_ADSP 3 +#define MT8188_AP_VDO 4 +#define MT8188_AP_INFRA 5 #define MT8188_AP_CAM1 6 #define MT8188_AP_CAM2 7 =20 --=20 2.37.3 From nobody Thu Sep 19 23:08:02 2024 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45D5E15E5D1 for ; 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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=1717; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=ZXPmUPXXFa1JCVfBMk9FrptEjzZlcdWN0z1cSMSnOwA=; b=OK85Uj3rrGZKhM3JHH4HH37bvvdgaZPlri/dH9Ot2gzRF2PTxp3xVfjp4zaOTnBta+MXzcw1t V4Oh/qlSE9oCfjLLpHptTWE7PqNg4Q/NHo5lMhCIc5HTvkEf+y35Bto X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Values extracted from vendor source tree. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-8-nico@fluxnic.net [Angelo: Fixed validation and quality issues] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 4763ed5dc86c..caec83f5eece 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1361,6 +1361,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8186-lvts"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells =3D <1>; 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Tue, 28 May 2024 22:58:09 -0700 (PDT) From: Julien Panis Date: Wed, 29 May 2024 07:57:59 +0200 Subject: [PATCH v6 4/6] arm64: dts: mediatek: mt8186: add default thermal zones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240529-mtk-thermal-mt818x-dtsi-v6-4-0c71478a9c37@baylibre.com> References: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> In-Reply-To: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=7777; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=sG5Ze//7RlqRD8XfjGttbCgM09mHkLhEkzGoVC5Po1o=; b=wVQnyGHe1Ma8jwdKe2e2HxTlRKjrpLCLCtxc0O/kxW+HBvskAOmmztbqtkorg9PPckRQrLWRI JbVGuQhbKDCA97bWkDQSka5YMLTbrTCZM+ukjWJrvCmHZJXubKU0q0u X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Inspired by the vendor kernel but adapted to the upstream thermal driver version. Signed-off-by: Nicolas Pitre Signed-off-by: Julien Panis Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 297 +++++++++++++++++++++++++++= ++++ 1 file changed, 297 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index caec83f5eece..95fe5a05f0d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "mediatek,mt8186"; @@ -2197,4 +2199,299 @@ larb19: smi@1c10f000 { power-domains =3D <&spm MT8186_POWER_DOMAIN_IPE>; }; }; + + thermal_zones: thermal-zones { + cpu-little0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts MT8186_LITTLE_CPU0>; + + trips { + cpu_little0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little0_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts MT8186_LITTLE_CPU1>; + + trips { + cpu_little1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little1_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts MT8186_LITTLE_CPU2>; + + trips { + cpu_little2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little2_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cam-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_CAM>; + + trips { + cam_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cam_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nna-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_NNA>; + + trips { + nna_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + nna_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + nna_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + adsp-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_ADSP>; + + trips { + adsp_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + adsp_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + adsp_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_GPU>; + + trips { + gpu_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + gpu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_alert0>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts MT8186_BIG_CPU0>; + + trips { + cpu_big0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_big0_alert0>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts MT8186_BIG_CPU1>; + + trips { + cpu_big1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big1_crit: trip-crit { + temperature =3D <100000>; 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Tue, 28 May 2024 22:58:11 -0700 (PDT) From: Julien Panis Date: Wed, 29 May 2024 07:58:00 +0200 Subject: [PATCH v6 5/6] arm64: dts: mediatek: mt8188: add lvts definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240529-mtk-thermal-mt818x-dtsi-v6-5-0c71478a9c37@baylibre.com> References: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> In-Reply-To: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=2943; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=a+N8mpao7+QeANDnMFXYaOS/6MVQmW9fHDWrXbASce8=; b=oJuNvvc75KFtnVqOakvIcFJySZhl3GRFOsEwG9SQWUSfhhwM7G3A13Oj4W8Uz/ymTnQFDxFC8 K6AHaPrYivcClMPXvWfgkF74RG5wHhY1u6HVxiF4XekFmUGkdgZUUKv X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Various values extracted from the vendor's kernel driver. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-14-nico@fluxnic.net [Angelo: Fixed wrong nvmem-cell-names] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 35 ++++++++++++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 29d012d28edb..02786fe9891b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8188"; @@ -464,6 +465,7 @@ infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8188-infracfg-ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 pericfg: syscon@10003000 { @@ -937,6 +939,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8188-lvts-ap"; + reg =3D <0 0x1100b000 0 0xc00>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells =3D <1>; @@ -1050,6 +1063,17 @@ mmc1: mmc@11240000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8188-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + i2c0: i2c@11280000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11280000 0 0x1000>, @@ -1273,6 +1297,17 @@ imp_iic_wrap_en: clock-controller@11ec2000 { #clock-cells =3D <1>; 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Tue, 28 May 2024 22:58:13 -0700 (PDT) From: Julien Panis Date: Wed, 29 May 2024 07:58:01 +0200 Subject: [PATCH v6 6/6] arm64: dts: mediatek: mt8188: add default thermal zones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240529-mtk-thermal-mt818x-dtsi-v6-6-0c71478a9c37@baylibre.com> References: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> In-Reply-To: <20240529-mtk-thermal-mt818x-dtsi-v6-0-0c71478a9c37@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Krzysztof Kozlowski , Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716962279; l=11449; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=6HvcJw/GiUMGA5QgSQkB+3ZEuSp1mJLMjRQtbGjzMsU=; b=mvxaIs4kZQBuy1OCGzgeNIRqej7H1QiOg2k9FUBBJsIaH1ixK53E4fYwlMxmoXPZSJNl6SAki 47bOhw5Ha/rCCBztqz5Wq6GHU8UZJ+49wBPJOVNqFcaGM+kJ3iHnuFt X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Inspired by the vendor kernel but adapted to the upstream thermal driver version. Signed-off-by: Nicolas Pitre Signed-off-by: Julien Panis Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 447 +++++++++++++++++++++++++++= ++++ 1 file changed, 447 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 02786fe9891b..cd27966d2e3c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "mediatek,mt8188"; @@ -418,6 +420,450 @@ psci { method =3D "smc"; }; =20 + thermal_zones: thermal-zones { + cpu-little0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; + + trips { + cpu_little0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little0_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; + + trips { + cpu_little1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little1_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; + + trips { + cpu_little2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little2_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little3-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; + + trips { + cpu_little3_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little3_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little3_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little3_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_BIG_CPU0>; + + trips { + cpu_big0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_big0_alert0>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_BIG_CPU1>; + + trips { + cpu_big1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_big1_alert0>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + apu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_APU>; + + trips { + apu_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + apu_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + apu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_GPU0>; + + trips { + gpu_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + gpu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_alert0>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_GPU1>; + + trips { + gpu1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + gpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu1_alert0>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + adsp-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_ADSP>; + + trips { + soc_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + soc_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + soc_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + vdo-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_VDO>; + + trips { + soc1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + soc1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + soc1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + infra-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_INFRA>; + + trips { + soc2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + soc2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + soc2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cam1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_CAM1>; + + trips { + cam1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cam1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cam2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_CAM2>; + + trips { + cam2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cam2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + timer: timer { compatible =3D "arm,armv8-timer"; interrupt-parent =3D <&gic>; @@ -1322,6 +1768,7 @@ gpu: gpu@13000000 { <&spm MT8188_POWER_DOMAIN_MFG3>, <&spm MT8188_POWER_DOMAIN_MFG4>; power-domain-names =3D "core0", "core1", "core2"; + #cooling-cells =3D <2>; status =3D "disabled"; }; =20 --=20 2.37.3