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Wed, 29 May 2024 11:47:50 +0200 Received: from lnxamnaw.se.axis.com (unknown [10.92.129.190]) by se-intmail01x.se.axis.com (Postfix) with ESMTP id 690F1AF6; Wed, 29 May 2024 11:47:50 +0200 (CEST) Received: by lnxamnaw.se.axis.com (Postfix, from userid 12778) id 5F2E32066B0; Wed, 29 May 2024 11:47:45 +0200 (CEST) From: Amna Waseem Date: Wed, 29 May 2024 11:47:44 +0200 Subject: [PATCH v2 1/2] dt-bindings: hwmon: ti,ina2xx: Add ti,alert-polarity property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240529-apol-ina2xx-fix-v2-1-ee2d76142de2@axis.com> References: <20240529-apol-ina2xx-fix-v2-0-ee2d76142de2@axis.com> In-Reply-To: <20240529-apol-ina2xx-fix-v2-0-ee2d76142de2@axis.com> To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" CC: Krzysztof Kozlowski , , , , Amna Waseem , X-Mailer: b4 0.13.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A5D:EE_|AS2PR02MB10374:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e2725f1-ad43-49de-7abb-08dc7fc46814 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|82310400017|1800799015; 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X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2024 09:47:51.5945 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e2725f1-ad43-49de-7abb-08dc7fc46814 X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A5D.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR02MB10374 Add a property to the binding to configure the Alert Polarity. Alert pin is asserted based on the value of Alert Polarity bit of Mask/Enable register. It is by default 0 which means Alert pin is configured to be active low open collector. Value of 1 maps to Inverted (active high open collector). Signed-off-by: Amna Waseem --- Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Docum= entation/devicetree/bindings/hwmon/ti,ina2xx.yaml index df86c2c92037..5a16d2d94587 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -66,6 +66,14 @@ properties: description: phandle to the regulator that provides the VS supply typi= cally in range from 2.7 V to 5.5 V. =20 + ti,alert-polarity: + description: Alert polarity bit value of Mask/Enable register. Alert p= in is + asserted based on the value of Alert polarity Bit. Default value is = Normal + (0 which maps to active-low open collector). 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Wed, 29 May 2024 11:47:50 +0200 Received: from lnxamnaw.se.axis.com (unknown [10.92.129.190]) by se-intmail01x.se.axis.com (Postfix) with ESMTP id 682E02243; Wed, 29 May 2024 11:47:50 +0200 (CEST) Received: by lnxamnaw.se.axis.com (Postfix, from userid 12778) id 638AD2069D6; Wed, 29 May 2024 11:47:45 +0200 (CEST) From: Amna Waseem Date: Wed, 29 May 2024 11:47:45 +0200 Subject: [PATCH v2 2/2] hwmon: (ina2xx) Add device tree support to pass alert polarity Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240529-apol-ina2xx-fix-v2-2-ee2d76142de2@axis.com> References: <20240529-apol-ina2xx-fix-v2-0-ee2d76142de2@axis.com> In-Reply-To: <20240529-apol-ina2xx-fix-v2-0-ee2d76142de2@axis.com> To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" CC: Krzysztof Kozlowski , , , , Amna Waseem , X-Mailer: b4 0.13.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A5D:EE_|PA4PR02MB6702:EE_ X-MS-Office365-Filtering-Correlation-Id: 62cdfb0d-0253-4518-43d0-08dc7fc467bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|82310400017|1800799015|36860700004; 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X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2024 09:47:50.9539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62cdfb0d-0253-4518-43d0-08dc7fc467bc X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A5D.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR02MB6702 The INA230 has an Alert pin which is asserted when the alert function selected in the Mask/Enable register exceeds the value programmed into the Alert Limit register. Assertion is based on the Alert Polarity Bit (APOL, bit 1 of the Mask/Enable register). It is default set to value 0 i.e Normal (active-low open collector). However, hardware can be designed in such a way that expects Alert pin to become active high if a user-defined threshold in Alert limit register has been exceeded. This patch adds a way to pass alert polarity value to the driver via device tree. Signed-off-by: Amna Waseem --- drivers/hwmon/ina2xx.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index d8415d1f21fc..9afaabdc367d 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -73,6 +73,9 @@ #define INA226_READ_AVG(reg) (((reg) & INA226_AVG_RD_MASK) >> 9) #define INA226_SHIFT_AVG(val) ((val) << 9) =20 +#define INA226_ALERT_POLARITY_MASK 0x0002 +#define INA226_SHIFT_ALERT_POLARITY(val) ((val) << 1) + /* bit number of alert functions in Mask/Enable Register */ #define INA226_SHUNT_OVER_VOLTAGE_BIT 15 #define INA226_SHUNT_UNDER_VOLTAGE_BIT 14 @@ -178,6 +181,21 @@ static u16 ina226_interval_to_reg(int interval) return INA226_SHIFT_AVG(avg_bits); } =20 +static int ina2xx_set_alert_polarity(struct ina2xx_data *data, + unsigned long val) +{ + int ret; + + if (val > INT_MAX || !(val =3D=3D 0 || val =3D=3D 1)) + return -EINVAL; + + ret =3D regmap_update_bits(data->regmap, INA226_MASK_ENABLE, + INA226_ALERT_POLARITY_MASK, + INA226_SHIFT_ALERT_POLARITY(val)); + + return ret; +} + /* * Calibration register is set to the best value, which eliminates * truncation errors on calculating current register in hardware. @@ -659,6 +677,15 @@ static int ina2xx_probe(struct i2c_client *client) if (ret) return dev_err_probe(dev, ret, "failed to enable vs regulator\n"); =20 + if (!of_property_read_u32(dev->of_node, "ti,alert-polarity", &val)) { + ret =3D ina2xx_set_alert_polarity(data, val); + if (ret < 0) { + return dev_err_probe( + dev, ret, + "failed to set APOL bit of Enable/Mask register\n"); + } + } + ret =3D ina2xx_init(data); if (ret < 0) { dev_err(dev, "error configuring the device: %d\n", ret); --=20 2.30.2