From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9213416F84F for ; Tue, 28 May 2024 14:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906041; cv=none; b=LtAJkdP9JayaMPbvRQQJXFborrUKMcWDDjFXhLsj5sEEgueeaej3VNAUTzZi1xT2Krwjuzl4xWXf1i5AJSMKyqoKo5xhK0FHEjPL0GcilQdvIYyer6R1aw+lkFzWqeTsbzccrnmj6t77DAEdBpTHgPPi4/mGlNz6pAVtX8/PshU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906041; c=relaxed/simple; bh=683ZTRUzgOFpnsYMQxwIT3dRKS4VdbeBjXmV0/zmGIw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dUK/lfNoIT1r9UBlbi1+96ZXUNo4VgMZ1YyZWrOnPDE5UoDZCs/YOVpi6byqruUz8OEQIonW0uQzcUCL8XU5FcD8K8lMoPFetHZS0SzaHzMRgp/c6KdDc/mt+tuGeXf3LX4rtm4GALYP1mO92bCYjJB5qg8rNPidMsPAGp2omQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=A/JoJJPe; arc=none smtp.client-ip=209.85.221.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="A/JoJJPe" Received: by mail-wr1-f67.google.com with SMTP id ffacd0b85a97d-354c5b7fafaso675410f8f.3 for ; Tue, 28 May 2024 07:20:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906038; x=1717510838; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lJIq545QK9y8AX4JlRGPouvkbkoDYm+eR9amBtMPUNM=; b=A/JoJJPejPsOxwB8IuiucbI6ezfVIjX/17Q/nvLzQWRHqxYRShm8ihE1HLxkfdzhzI nbPs623yHIs92fW+pquLICyr0TyCNqnsVs4i4FYXm2LChdBSa6sDQNwx6XMCM1AgCwRB Evp0MoQNd9wvJs5hhUfuRghMZnHQhfAWati1lI4w/FxbCLbqlE8Rxby8h6Krl1bgNkuM bCGcc/lBDxkIyahSA0aCO1ERKcb9fwI/iK7KUVU2e2UH+RXfeyYGL1RuNpw4Kevyu+VV 1TDrp45/+L/cS+Hn1v/wy5jRFl72rYO0EyNiiD4UKEtCd1ADFgfRJ7Cb5D/0UUmNGIEi abpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906038; x=1717510838; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lJIq545QK9y8AX4JlRGPouvkbkoDYm+eR9amBtMPUNM=; b=daCBevazADqlzd6L2bjbRhKZrog4whPhjKpWIN2U4wdgPUwgqmiZAyWKoT98MpPxm6 oJI5ThPPODUJk1PwHJonLtuarThGvTOat0gk4bjqS7TG65wOAFb8t1BWtDsV3IUBXAvh htVpRwqYnlRyQKckNn9mndRgVjz5jYrX8y7Oy0bFbedVhXPIPT5G3vnEI81QTwKR5y8F 0gpyJ0oZE23bbdqcicjV3zM/ny3IqwL0jZ158srURlKW0huylqRYMmAdqgTJxhRHg5FR 8gCuQt8edmbtKkVHY/Od7eHKgEmz4vgX2+VGnnP8DMb442xrtB2xX9qwrwAC/aq+QlEl ZEfg== X-Forwarded-Encrypted: i=1; AJvYcCU7r/RHOqjiAxPu4ntVptzRnqYEFVSsqAEedqc0URukJo6Sm2IYo/Gth+sajcqDuKAMHfIsaWy2VA7rOoFTRIaZpaGXBuMsaFmvoXjz X-Gm-Message-State: AOJu0Yx8HVbk8Uo8HTrvPX9CGl74AT6Fa5SlIqJ+tPSqN68K/eazr6eG BK0heXN7Km6BfKb9QPkdFUz6EvxLjl0ZTv3FgIzJMgKkS4l1uJJWKdnK053FgnQ= X-Google-Smtp-Source: AGHT+IF3FvDi4jMOALZ3OiK9MgNpFVAhQ84sNI68o78zApuPB0dqYxkHxn+M0cNd9xu6BiJS20mTsg== X-Received: by 2002:adf:f585:0:b0:355:361:5672 with SMTP id ffacd0b85a97d-3552fdfa501mr8561849f8f.66.1716906037880; Tue, 28 May 2024 07:20:37 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:37 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:28 +0200 Subject: [PATCH v7 1/7] dt-bindings: iio: adc: Add binding for AD7380 ADCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-1-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan , Conor Dooley X-Mailer: b4 0.13.0 From: David Lechner This adds a binding specification for the Analog Devices Inc. AD7380 family of ADCs. Signed-off-by: David Lechner Signed-off-by: Julien Stephan Reviewed-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 82 ++++++++++++++++++= ++++ MAINTAINERS | 9 +++ 2 files changed, 91 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml new file mode 100644 index 000000000000..5e1ee0ebe0a2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7380.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices Simultaneous Sampling Analog to Digital Converters + +maintainers: + - Michael Hennerich + - Nuno S=C3=A1 + +description: | + * https://www.analog.com/en/products/ad7380.html + * https://www.analog.com/en/products/ad7381.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 80000000 + spi-cpol: true + spi-cpha: true + + vcc-supply: + description: A 3V to 3.6V supply that powers the chip. + + vlogic-supply: + description: + A 1.65V to 3.6V supply for the logic pins. + + refio-supply: + description: + A 2.5V to 3.3V supply for the external reference voltage. When omitt= ed, + the internal 2.5V reference is used. + + interrupts: + description: + When the device is using 1-wire mode, this property is used to optio= nally + specify the ALERT interrupt. + maxItems: 1 + +required: + - compatible + - reg + - vcc-supply + - vlogic-supply + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7380"; + reg =3D <0>; + + spi-cpol; + spi-cpha; + spi-max-frequency =3D <80000000>; + + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpio0>; + + vcc-supply =3D <&supply_3_3V>; + vlogic-supply =3D <&supply_3_3V>; + refio-supply =3D <&supply_2_5V>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 758c202ec712..4f162600e982 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -427,6 +427,15 @@ W: http://wiki.analog.com/AD7142 W: https://ez.analog.com/linux-software-drivers F: drivers/input/misc/ad714x.c =20 +AD738X ADC DRIVER (AD7380/1/2/4) +M: Michael Hennerich +M: Nuno S=C3=A1 +R: David Lechner +S: Supported +W: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/= ad738x +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml + AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich S: Supported --=20 2.44.0 From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28F8616E895 for ; Tue, 28 May 2024 14:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.68 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906043; cv=none; b=n5dZFdslwl+jIOHOd31jqVQqzBKXyXCTvqnqSK7vbKXUWrJCKre7M9oKC3qyFq/1UR0snI7gzf+JFeK2HqTcv8ger07sqLZQLtfLP1rwvmNS1CSWMAt8wDU8CR4OdZQjubynn7AMLGn0fZa4P2aSp9BIOdbWqDjnW8PzMysPZVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906043; c=relaxed/simple; bh=0+eT89saMS4Y0sggsTElWNXdwkYg6QkyeONV+G5bPjA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DHpDx2vl8I48BRNxUDSu+KPCuWUrHkPujrpyXN1XgYbwADsa8eJe/+nZ1b0/K3SBTZtZIHGmH65rut03/BZJS7s+SMXarSUJxrKHPDpCCSeDqUks51nBbhalyLl5rJgCPIqp9M3uD9a11O2d4xK9Ul15jNIOflJWBWmHICSJt5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=dof7YV+r; arc=none smtp.client-ip=209.85.221.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="dof7YV+r" Received: by mail-wr1-f68.google.com with SMTP id ffacd0b85a97d-35507fc2600so804477f8f.0 for ; Tue, 28 May 2024 07:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906039; x=1717510839; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kA96oc/kl3sYd8WdlE3Ax8TpqvioyNc0mC+dpMmE3GE=; b=dof7YV+rVqYYPCOI74KDM3BckoE5nTTfPeggizgh0qZ3GVamoeW0nvc5uX+p8R7+nA g4Cdm6W8HmwhvOnKBI9lvAE4e9A7/M5AeRmYh1SFEB6mymStyydCadWOv9KeothyzY4Z iA+rktaD29IipFnB++W4KfwzSTq4LSvJHwJ31YroFs22QnLPK7J9iTV/bz/cc0j4nue7 2HLf0yjSZ/BxCkj5yBmMtKas54+5to8u8OiZ9KfpJacAXA+6lYHbXpEcLMIsoOpAD6vI 8NjcDPeRgApYp2FKBy/afFidxIYk6VsO7Mal+EU1MNJyV2avDBBfqd4PzlVxuL19TfDI YPzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906039; x=1717510839; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kA96oc/kl3sYd8WdlE3Ax8TpqvioyNc0mC+dpMmE3GE=; b=MPdQfuwbjMD5uRluRjncm5QR9LI27dAuTpPZnJUT+DXZeRNN3/pQiwMvgMbHiZfwWF IeLT6FoaU4wm6hEjVbZoVdyMN1a8INcq5+BIWqhI/kmIiXVUYm3G2KRQW8JTkMoytVXW VUwAnBqmykS8RRrdZC3PP8/5vpsZxiPG+kmo/srvq4rPj9Z0DDmalEDEq0xXVQQESW+T ey/MxoNt2IHdIEihjxPU7DYoA8whIQsZ9sxhO2FkskOdUOl9ksN1i2V680yyq16hDfxu Kaf8fllma4l6/D+btJu3tA70cPaZgfmloun8tPIwMGEpkCkstOdyGWArbD/EDiZm94Bh oI5Q== X-Forwarded-Encrypted: i=1; AJvYcCVyihHSljMYX/aDiPB4KW5u/D++cC+TUKpO+4UmxHk8Xd1uyrmZpDRDAW9PAxalhJZnHTOrlLkJODGGB22Ff0hkJ2w7hjEgqkjapzvf X-Gm-Message-State: AOJu0Yz30epSYaEu8D8SBHkkRy/mPZm67UxfOG3fArmDCIDMZTmWmc+a sqfLOcAIJ5TKJzxi2Dngf6ZXzailn3/36x5S7JH/6Qf7auyEvtqrVSei1DQOduU= X-Google-Smtp-Source: AGHT+IGuQwMLzdoy3JvonybMKiytZ6Xf7sE0EVy4nEWFlNaSQbwGqE+Fma3/9rr0X61F+fvQWBJhuQ== X-Received: by 2002:adf:a18d:0:b0:346:47d6:5d17 with SMTP id ffacd0b85a97d-3552fe01f0emr9222025f8f.57.1716906039202; Tue, 28 May 2024 07:20:39 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:38 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:29 +0200 Subject: [PATCH v7 2/7] iio: adc: ad7380: new driver for AD7380 ADCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-2-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan , Stefan Popa X-Mailer: b4 0.13.0 From: David Lechner This adds a new driver for the AD7380 family ADCs. The driver currently implements basic support for the AD7380, AD7381, 2-channel differential ADCs. Support for additional single-ended, pseudo-differential and 4-channel chips that use the same register map as well as additional features of the chip will be added in future patches. Co-developed-by: Stefan Popa Signed-off-by: Stefan Popa Reviewed-by: Nuno Sa Signed-off-by: David Lechner [Julien Stephan: add datasheet links of supported parts] [Julien Stephan: fix rx/tx buffer for regmap access] [Julien Stephan: fix scale issue] [Julien Stephan: use the new iio_device_claim_direct_scoped instead of iio_device_claim_direct_mode] Signed-off-by: Julien Stephan --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 16 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7380.c | 438 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 456 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4f162600e982..315b3060946f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -435,6 +435,7 @@ S: Supported W: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/= ad738x W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +F: drivers/iio/adc/ad7380.c =20 AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 8db68b80b391..631386b037ae 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -155,6 +155,22 @@ config AD7298 To compile this driver as a module, choose M here: the module will be called ad7298. =20 +config AD7380 + tristate "Analog Devices AD7380 ADC driver" + depends on SPI_MASTER + select IIO_BUFFER + select IIO_TRIGGER + select IIO_TRIGGERED_BUFFER + help + AD7380 is a family of simultaneous sampling ADCs that share the same + SPI register map and have similar pinouts. + + Say yes here to build support for Analog Devices AD7380 ADC and + similar chips. + + To compile this driver as a module, choose M here: the module will be + called ad7380. + config AD7476 tristate "Analog Devices AD7476 1-channel ADCs driver and other similar d= evices from AD and TI" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index edb32ce2af02..bd3cbbb178fa 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_AD7291) +=3D ad7291.o obj-$(CONFIG_AD7292) +=3D ad7292.o obj-$(CONFIG_AD7298) +=3D ad7298.o obj-$(CONFIG_AD7923) +=3D ad7923.o +obj-$(CONFIG_AD7380) +=3D ad7380.o obj-$(CONFIG_AD7476) +=3D ad7476.o obj-$(CONFIG_AD7606_IFACE_PARALLEL) +=3D ad7606_par.o obj-$(CONFIG_AD7606_IFACE_SPI) +=3D ad7606_spi.o diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c new file mode 100644 index 000000000000..dac7e11755ff --- /dev/null +++ b/drivers/iio/adc/ad7380.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD738x Simultaneous Sampling SAR ADCs + * + * Copyright 2017 Analog Devices Inc. + * Copyright 2024 BayLibre, SAS + * + * Datasheets of supported parts: + * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* 2.5V internal reference voltage */ +#define AD7380_INTERNAL_REF_MV 2500 + +/* reading and writing registers is more reliable at lower than max speed = */ +#define AD7380_REG_WR_SPEED_HZ 10000000 + +#define AD7380_REG_WR BIT(15) +#define AD7380_REG_REGADDR GENMASK(14, 12) +#define AD7380_REG_DATA GENMASK(11, 0) + +#define AD7380_REG_ADDR_NOP 0x0 +#define AD7380_REG_ADDR_CONFIG1 0x1 +#define AD7380_REG_ADDR_CONFIG2 0x2 +#define AD7380_REG_ADDR_ALERT 0x3 +#define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 +#define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 + +#define AD7380_CONFIG1_OS_MODE BIT(9) +#define AD7380_CONFIG1_OSR GENMASK(8, 6) +#define AD7380_CONFIG1_CRC_W BIT(5) +#define AD7380_CONFIG1_CRC_R BIT(4) +#define AD7380_CONFIG1_ALERTEN BIT(3) +#define AD7380_CONFIG1_RES BIT(2) +#define AD7380_CONFIG1_REFSEL BIT(1) +#define AD7380_CONFIG1_PMODE BIT(0) + +#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) +#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_RESET GENMASK(7, 0) + +#define AD7380_CONFIG2_RESET_SOFT 0x3C +#define AD7380_CONFIG2_RESET_HARD 0xFF + +#define AD7380_ALERT_LOW_TH GENMASK(11, 0) +#define AD7380_ALERT_HIGH_TH GENMASK(11, 0) + +struct ad7380_chip_info { + const char *name; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +#define AD7380_CHANNEL(index, bits) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .indexed =3D 1, \ + .differential =3D 1, \ + .channel =3D 2 * (index), \ + .channel2 =3D 2 * (index) + 1, \ + .scan_index =3D (index), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D (bits), \ + .storagebits =3D 16, \ + .endianness =3D IIO_CPU, \ + }, \ +} + +#define DEFINE_AD7380_2_CHANNEL(name, bits) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits), \ + AD7380_CHANNEL(1, bits), \ + IIO_CHAN_SOFT_TIMESTAMP(2), \ +} + +DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16); +DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14); + +/* Since this is simultaneous sampling, we don't allow individual channels= . */ +static const unsigned long ad7380_2_channel_scan_masks[] =3D { + GENMASK(1, 0), + 0 +}; + +static const struct ad7380_chip_info ad7380_chip_info =3D { + .name =3D "ad7380", + .channels =3D ad7380_channels, + .num_channels =3D ARRAY_SIZE(ad7380_channels), +}; + +static const struct ad7380_chip_info ad7381_chip_info =3D { + .name =3D "ad7381", + .channels =3D ad7381_channels, + .num_channels =3D ARRAY_SIZE(ad7381_channels), +}; + +struct ad7380_state { + const struct ad7380_chip_info *chip_info; + struct spi_device *spi; + struct regmap *regmap; + unsigned int vref_mv; + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + * Make the buffer large enough for 2 16-bit samples and one 64-bit + * aligned 64 bit timestamp. + */ + struct { + u16 raw[2]; + + s64 ts __aligned(8); + } scan_data __aligned(IIO_DMA_MINALIGN); + u16 tx; + u16 rx; +}; + +static int ad7380_regmap_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ad7380_state *st =3D context; + struct spi_transfer xfer =3D { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .tx_buf =3D &st->tx, + }; + + st->tx =3D FIELD_PREP(AD7380_REG_WR, 1) | + FIELD_PREP(AD7380_REG_REGADDR, reg) | + FIELD_PREP(AD7380_REG_DATA, val); + + return spi_sync_transfer(st->spi, &xfer, 1); +} + +static int ad7380_regmap_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ad7380_state *st =3D context; + struct spi_transfer xfers[] =3D { + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .tx_buf =3D &st->tx, + .cs_change =3D 1, + .cs_change_delay =3D { + .value =3D 10, /* t[CSH] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + }, { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .rx_buf =3D &st->rx, + }, + }; + int ret; + + st->tx =3D FIELD_PREP(AD7380_REG_WR, 0) | + FIELD_PREP(AD7380_REG_REGADDR, reg) | + FIELD_PREP(AD7380_REG_DATA, 0); + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret < 0) + return ret; + + *val =3D FIELD_GET(AD7380_REG_DATA, st->rx); + + return 0; +} + +static const struct regmap_config ad7380_regmap_config =3D { + .reg_bits =3D 3, + .val_bits =3D 12, + .reg_read =3D ad7380_regmap_reg_read, + .reg_write =3D ad7380_regmap_reg_write, + .max_register =3D AD7380_REG_ADDR_ALERT_HIGH_TH, + .can_sleep =3D true, +}; + +static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, + u32 writeval, u32 *readval) +{ + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + struct ad7380_state *st =3D iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + else + return regmap_write(st->regmap, reg, writeval); + } + unreachable(); +} + +static irqreturn_t ad7380_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_transfer xfer =3D { + .bits_per_word =3D st->chip_info->channels[0].scan_type.realbits, + .len =3D 4, + .rx_buf =3D st->scan_data.raw, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + goto out; + + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data, + pf->timestamp); + +out: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int ad7380_read_direct(struct ad7380_state *st, + struct iio_chan_spec const *chan, int *val) +{ + struct spi_transfer xfers[] =3D { + /* toggle CS (no data xfer) to trigger a conversion */ + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D chan->scan_type.realbits, + .delay =3D { + .value =3D 190, /* t[CONVERT] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + .cs_change =3D 1, + .cs_change_delay =3D { + .value =3D 10, /* t[CSH] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + }, + /* then read both channels */ + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D chan->scan_type.realbits, + .rx_buf =3D st->scan_data.raw, + .len =3D 4, + }, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret < 0) + return ret; + + *val =3D sign_extend32(st->scan_data.raw[chan->scan_index], + chan->scan_type.realbits - 1); + + return IIO_VAL_INT; +} + +static int ad7380_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_RAW: + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + return ad7380_read_direct(st, chan, val); + } + unreachable(); + case IIO_CHAN_INFO_SCALE: + /* + * According to the datasheet, the LSB size for fully differential ADC is + * (2 =C3=97 VREF) / 2^N, where N is the ADC resolution (i.e realbits) + */ + *val =3D st->vref_mv; + *val2 =3D chan->scan_type.realbits - 1; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info ad7380_info =3D { + .read_raw =3D &ad7380_read_raw, + .debugfs_reg_access =3D &ad7380_debugfs_reg_access, +}; + +static int ad7380_init(struct ad7380_state *st, struct regulator *vref) +{ + int ret; + + /* perform hard reset */ + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_RESET, + FIELD_PREP(AD7380_CONFIG2_RESET, + AD7380_CONFIG2_RESET_HARD)); + if (ret < 0) + return ret; + + /* select internal or external reference voltage */ + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_REFSEL, + FIELD_PREP(AD7380_CONFIG1_REFSEL, + vref ? 1 : 0)); + if (ret < 0) + return ret; + + /* SPI 1-wire mode */ + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_SDO, + FIELD_PREP(AD7380_CONFIG2_SDO, 1)); +} + +static void ad7380_regulator_disable(void *p) +{ + regulator_disable(p); +} + +static int ad7380_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct ad7380_state *st; + struct regulator *vref; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return dev_err_probe(&spi->dev, -EINVAL, "missing match data\n"); + + vref =3D devm_regulator_get_optional(&spi->dev, "refio"); + if (IS_ERR(vref)) { + if (PTR_ERR(vref) !=3D -ENODEV) + return dev_err_probe(&spi->dev, PTR_ERR(vref), + "Failed to get refio regulator\n"); + + vref =3D NULL; + } + + /* + * If there is no REFIO supply, then it means that we are using + * the internal 2.5V reference, otherwise REFIO is reference voltage. + */ + if (vref) { + ret =3D regulator_enable(vref); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&spi->dev, + ad7380_regulator_disable, vref); + if (ret) + return ret; + + ret =3D regulator_get_voltage(vref); + if (ret < 0) + return ret; + + st->vref_mv =3D ret / 1000; + } else { + st->vref_mv =3D AD7380_INTERNAL_REF_MV; + } + + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); + if (IS_ERR(st->regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), + "failed to allocate register map\n"); + + indio_dev->channels =3D st->chip_info->channels; + indio_dev->num_channels =3D st->chip_info->num_channels; + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad7380_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->available_scan_masks =3D ad7380_2_channel_scan_masks; + + ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + iio_pollfunc_store_time, + ad7380_trigger_handler, NULL); + if (ret) + return ret; + + ret =3D ad7380_init(st, vref); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct of_device_id ad7380_of_match_table[] =3D { + { .compatible =3D "adi,ad7380", .data =3D &ad7380_chip_info }, + { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, + { } +}; + +static const struct spi_device_id ad7380_id_table[] =3D { + { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, + { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad7380_id_table); + +static struct spi_driver ad7380_driver =3D { + .driver =3D { + .name =3D "ad7380", + .of_match_table =3D ad7380_of_match_table, + }, + .probe =3D ad7380_probe, + .id_table =3D ad7380_id_table, +}; +module_spi_driver(ad7380_driver); + +MODULE_AUTHOR("Stefan Popa "); +MODULE_DESCRIPTION("Analog Devices AD738x ADC driver"); +MODULE_LICENSE("GPL"); --=20 2.44.0 From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 600F916F85C for ; Tue, 28 May 2024 14:20:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906043; cv=none; b=ok2GMFypzP4sRuU3cAQDi5SYLoKWrNwkxZlkGp33ik14/7K3tdBmr+GiiaMr/2rW4Ic2Z9OGIrAatKOIt9/xybTSF+J6uENbidRugvkMCBe7pWmjDp66SVet5SZZaOX8doJhCwE9+9DoW+tKwsf+Tu22BtqFlb7xoTr/ZRACRi8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906043; c=relaxed/simple; bh=OB8tgBWPkNRhkYwIg+R2Ji0Wb3SGKEyVa27sOqMTYcs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QPUUOrjWTh8DHRQT/KmK71/diMlTuaDQY/z7E+dIJBQ1Xy34AGT5O/xnVivfqbeDS60Cvl27X9rOkEXcCSz6SetaRlpZCYul+PH1bKz7vto8JgRpamAbcLpshX/In7tUvmj3ov2zEEm3HfpnET14twwKoOypDJrv4B2zTx8Ykxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=UhPH2/vQ; arc=none smtp.client-ip=209.85.221.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="UhPH2/vQ" Received: by mail-wr1-f65.google.com with SMTP id ffacd0b85a97d-35a264cb831so661430f8f.2 for ; Tue, 28 May 2024 07:20:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906040; x=1717510840; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kJ8CU1KsZdsOI/zOnwTeILM7ZuUE9hyEpMnwtAluPZE=; b=UhPH2/vQp+mzJVOuIJ33iOT2zdFUCVU3TqxIu95+RkE9nuh+IBQAaMnF2AEvsRMCwu sCf7qmeF+NnuKADuY9xUK1oPq++Q3FSR1L1hunl+5GPCunikHHHmF42sEUQhiaqaCnyk hol4W5pH1Tir1xZ5rRieb5os8v/ThlREy9fGY73u3h4EOCGLdoi09Tqvmw6P7NbCW42a QO8Cf2Tf+Afxl1Bnv9jzgXQ6CmeyAu9d2MFx6YB/nbuLSpUDe+duJLtKLgc3NSNUshdu BKia69aH643yX4/7yJffsQgLONknlaqmvaGS7JrCtRFNG5oDYrYQBkizspBstqpOcDcQ HeTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906040; x=1717510840; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kJ8CU1KsZdsOI/zOnwTeILM7ZuUE9hyEpMnwtAluPZE=; b=fHsXrxAgMLAFmphtOeXMD/HQWLZCjLiAjxcfoWMoJrtF0hX6cLYQ3ehLzzHOm/ON4C 8kRc/czh/RujCwsexH5kkzMRVr0SSoQD8KRWiu7D2E22f4cMbTsAJ2wS/QpNywe0aEnB cKUg5ZEyHNg98vYdYUS1Vv8LbefAabTB2By0qA2WcmbmMakhn8jAs5NU3UdNWrFvtN5r mcFT7zEyC/cQr3+EH96JBM44gblqNCZJ8Ta+r9UI06ueUTWbrrUMi9fICxv/0bTTU0FS LxqBDSQrZ2G+Atjk/lkJh11dWju3QAfdPGkzQOtJDe9UT8dptcxyY16gC5+MZGTL85yk 1tdw== X-Forwarded-Encrypted: i=1; AJvYcCWIOcRRdSYucz5p0jH4syt3du1enCPNFeq0cyECeeHla9ujKnCK7BkbeplbjRLY5I+ApdVUMmEMu6IHKsMJsg0+C+C+6zojDPvGC6l3 X-Gm-Message-State: AOJu0YwIQE/DpXXPOaqWC9h7OaK83Wf2DBc4XeFCzqmbNCB+BKqi2pEG XB7foot1p+nfdjl5WeFeuQx+lV8xLaHRn15m2Lyl5sTfsXcjigCHK1sYdawOhVM= X-Google-Smtp-Source: AGHT+IFQYAZ2c7lzfDXVd6AmpmI0ICuN9BqtJxijv8ZHyENpbP62R1LSn0FAhBPpQ2Y9D2RZBK10Ug== X-Received: by 2002:a05:6000:248:b0:34d:b605:ec68 with SMTP id ffacd0b85a97d-35526c37d2emr9720315f8f.17.1716906039881; Tue, 28 May 2024 07:20:39 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:39 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:30 +0200 Subject: [PATCH v7 3/7] dt-bindings: iio: adc: ad7380: add pseudo-differential parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-3-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan , Conor Dooley X-Mailer: b4 0.13.0 From: David Lechner Adding AD7383 and AD7384 compatible parts that are pseudo-differential. Pseudo-differential require common mode voltage supplies, so add them conditionally Signed-off-by: David Lechner Signed-off-by: Julien Stephan Acked-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 32 ++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index 5e1ee0ebe0a2..de3d28a021ae 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -13,6 +13,8 @@ maintainers: description: | * https://www.analog.com/en/products/ad7380.html * https://www.analog.com/en/products/ad7381.html + * https://www.analog.com/en/products/ad7383.html + * https://www.analog.com/en/products/ad7384.html =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -21,6 +23,8 @@ properties: enum: - adi,ad7380 - adi,ad7381 + - adi,ad7383 + - adi,ad7384 =20 reg: maxItems: 1 @@ -42,6 +46,16 @@ properties: A 2.5V to 3.3V supply for the external reference voltage. When omitt= ed, the internal 2.5V reference is used. =20 + aina-supply: + description: + The common mode voltage supply for the AINA- pin on pseudo-different= ial + chips. + + ainb-supply: + description: + The common mode voltage supply for the AINB- pin on pseudo-different= ial + chips. + interrupts: description: When the device is using 1-wire mode, this property is used to optio= nally @@ -56,6 +70,24 @@ required: =20 unevaluatedProperties: false =20 +allOf: + # pseudo-differential chips require common mode voltage supplies, + # true differential chips don't use them + - if: + properties: + compatible: + enum: + - adi,ad7383 + - adi,ad7384 + then: + required: + - aina-supply + - ainb-supply + else: + properties: + aina-supply: false + ainb-supply: false + examples: - | #include --=20 2.44.0 From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 811E516F85A for ; Tue, 28 May 2024 14:20:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906044; cv=none; b=lhRWWpxgRwH6wqlJbCrAn9Kg6F6hW6UUXqEbqzG7D67v9661Zi8mYYgyiajVmCZGBFEtjug1o0i6k54nYx+nhAynw3lFyYqxcbr+pcglR9Ocx3UAo13YA9vizdEluVn+bmlvXjvmL5JOno5gBKNZCmH32upMFLKKYTisHCZkzkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906044; c=relaxed/simple; bh=GyOt6fap9XtxKOu2kTSLmUnNL+xLHReYGC7Mcyovo7g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WhUdTno56D66EcFUdDdQzCC+WDv63j441O8hWitHOP/GZrjJoZw6Bh2qG9e/8c+q7x+JlHgKWp75AEX7wQ1DjTm9Phw2fide6f00xi/xzK83RKFOUdbUltoE0aY4Uf4djD2bH0PPjAekYFxyy3oxXXvyEYY0YwIspUJ8qt2UUw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=QfLXupUr; arc=none smtp.client-ip=209.85.221.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="QfLXupUr" Received: by mail-wr1-f65.google.com with SMTP id ffacd0b85a97d-35bf77ba951so229257f8f.3 for ; Tue, 28 May 2024 07:20:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906041; x=1717510841; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yckqe26W9iPZGQmV4Ijp5QzBcbOV6EvrsiuvLN1du88=; b=QfLXupUr78Y/usbUWypTZ/Nh/H5BXST4qPEMsXlhEbumFfwv1w5BrDTbcCwq2sydpw oTuqOGfOeIP4uzfr9iLPrU49AEjzPxbAcMiLm+BtxoGWZfRr/17784ZMzr8gTEiRVETo eacZtj79tASTYvlegjVWCvwT3MplFudf8z40TP7EoWZSjOHW88m+GmCTk/QluAIo6F4A ZXsoff3ZSbCPHKrdzo1qd1zNbFAcUP7Dt9Uy612i30DjXn/ctLiabvQ9OGnm5yn3pLo5 jJQchpqJTtiDXDu7U79iIb6hlz5JtKTHyWYNn9BXSECTrc2NcH8hV97/3X2p/oIqfscA Se8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906041; x=1717510841; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yckqe26W9iPZGQmV4Ijp5QzBcbOV6EvrsiuvLN1du88=; b=nOBB3ktILGe3bYsNZ2pzXie/YKEJWacw6k9sXLBHe0C26qX5S5BJNYh1vzi/glRgDR A6RKCCsmpfd7I7sDifSwUsqSr5hGUFBvwgtZuoEqVSI7+ChmrHdw8cifjgDyJavm2Bv8 CwGxzr5RuuIc3LBpV2oZXtL72wbMKwz/GEKbkN5fs/K2qcN+4tVsN0uJDzkV/41StChO izpuFBBrqMUK2qIou83HbxBVCcLDbXx5U5JdNshu90ZAUfP7y7fYewBWgAVm2ehGbVjE QjfnWJfmcmNMKEijz8loi6sFtI784xLm59LNbz93BAp7PawGrOWHzHFl83mOO/Sh2SDw WCCA== X-Forwarded-Encrypted: i=1; AJvYcCUXK0krZEYFMUzBrE/HfN2+Q32LWwsVn9IbY3A1KvUxCreZ1tbyMVkFcA2NkQEMsq321khQefcTMoA3QCRz84EX9M7jOwre1Cmt6esx X-Gm-Message-State: AOJu0YzJi7KxsPoZfCK/uaG0Zc/TtekpAAqn1nKPjD0cIsx/2F82+lvT Rl1uGxwRa1WzuBAuDWl4vteu1YYVxQwD/j+1B5T8yApOzc4liUlN81CIiu9EGb4= X-Google-Smtp-Source: AGHT+IHTyeQ5Em7hPe0HI1+coYtjY8PTddP96gBSMgaHxibz5eMPdMm3Jbj/NqYdo2vPYRu5wkiorA== X-Received: by 2002:a5d:4684:0:b0:354:fc65:39d6 with SMTP id ffacd0b85a97d-35526c70f51mr8614510f8f.26.1716906040857; Tue, 28 May 2024 07:20:40 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:40 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:31 +0200 Subject: [PATCH v7 4/7] iio: adc: ad7380: add support for pseudo-differential parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-4-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 From: David Lechner Add support for AD7383, AD7384 pseudo-differential compatible parts. Pseudo differential parts require common mode voltage supplies so add the support for them and add the support of IIO_CHAN_INFO_OFFSET to retrieve the offset Signed-off-by: David Lechner Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 110 ++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 94 insertions(+), 16 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index dac7e11755ff..4ad283cf970d 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -7,6 +7,7 @@ * * Datasheets of supported parts: * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf + * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7383-7384.pdf */ =20 #include @@ -66,16 +67,19 @@ struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; + const char * const *vcm_supplies; + unsigned int num_vcm_supplies; }; =20 -#define AD7380_CHANNEL(index, bits) { \ +#define AD7380_CHANNEL(index, bits, diff) { \ .type =3D IIO_VOLTAGE, \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ .indexed =3D 1, \ - .differential =3D 1, \ - .channel =3D 2 * (index), \ - .channel2 =3D 2 * (index) + 1, \ + .differential =3D (diff), \ + .channel =3D (diff) ? (2 * (index)) : (index), \ + .channel2 =3D (diff) ? (2 * (index) + 1) : 0, \ .scan_index =3D (index), \ .scan_type =3D { \ .sign =3D 's', \ @@ -85,15 +89,23 @@ struct ad7380_chip_info { }, \ } =20 -#define DEFINE_AD7380_2_CHANNEL(name, bits) \ -static const struct iio_chan_spec name[] =3D { \ - AD7380_CHANNEL(0, bits), \ - AD7380_CHANNEL(1, bits), \ - IIO_CHAN_SOFT_TIMESTAMP(2), \ +#define DEFINE_AD7380_2_CHANNEL(name, bits, diff) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits, diff), \ + AD7380_CHANNEL(1, bits, diff), \ + IIO_CHAN_SOFT_TIMESTAMP(2), \ } =20 -DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16); -DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14); +/* fully differential */ +DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); +DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); +/* pseudo differential */ +DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); +DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); + +static const char * const ad7380_2_channel_vcm_supplies[] =3D { + "aina", "ainb", +}; =20 /* Since this is simultaneous sampling, we don't allow individual channels= . */ static const unsigned long ad7380_2_channel_scan_masks[] =3D { @@ -113,11 +125,28 @@ static const struct ad7380_chip_info ad7381_chip_info= =3D { .num_channels =3D ARRAY_SIZE(ad7381_channels), }; =20 +static const struct ad7380_chip_info ad7383_chip_info =3D { + .name =3D "ad7383", + .channels =3D ad7383_channels, + .num_channels =3D ARRAY_SIZE(ad7383_channels), + .vcm_supplies =3D ad7380_2_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), +}; + +static const struct ad7380_chip_info ad7384_chip_info =3D { + .name =3D "ad7384", + .channels =3D ad7384_channels, + .num_channels =3D ARRAY_SIZE(ad7384_channels), + .vcm_supplies =3D ad7380_2_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; struct regmap *regmap; unsigned int vref_mv; + unsigned int vcm_mv[2]; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. @@ -288,13 +317,24 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, unreachable(); case IIO_CHAN_INFO_SCALE: /* - * According to the datasheet, the LSB size for fully differential ADC is - * (2 =C3=97 VREF) / 2^N, where N is the ADC resolution (i.e realbits) + * According to the datasheet, the LSB size is: + * * (2 =C3=97 VREF) / 2^N, for differential chips + * * VREF / 2^N, for pseudo-differential chips + * where N is the ADC resolution (i.e realbits) */ *val =3D st->vref_mv; - *val2 =3D chan->scan_type.realbits - 1; + *val2 =3D chan->scan_type.realbits - chan->differential; =20 return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_OFFSET: + /* + * According to IIO ABI, offset is applied before scale, + * so offset is: vcm_mv / scale + */ + *val =3D st->vcm_mv[chan->channel] * (1 << chan->scan_type.realbits) + / st->vref_mv; + + return IIO_VAL_INT; default: return -EINVAL; } @@ -341,7 +381,7 @@ static int ad7380_probe(struct spi_device *spi) struct iio_dev *indio_dev; struct ad7380_state *st; struct regulator *vref; - int ret; + int ret, i; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); if (!indio_dev) @@ -385,6 +425,40 @@ static int ad7380_probe(struct spi_device *spi) st->vref_mv =3D AD7380_INTERNAL_REF_MV; } =20 + if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) + return dev_err_probe(&spi->dev, -EINVAL, + "invalid number of VCM supplies\n"); + + /* + * pseudo-differential chips have common mode supplies for the negative + * input pin. + */ + for (i =3D 0; i < st->chip_info->num_vcm_supplies; i++) { + struct regulator *vcm; + + vcm =3D devm_regulator_get(&spi->dev, + st->chip_info->vcm_supplies[i]); + if (IS_ERR(vcm)) + return dev_err_probe(&spi->dev, PTR_ERR(vcm), + "Failed to get %s regulator\n", + st->chip_info->vcm_supplies[i]); + + ret =3D regulator_enable(vcm); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&spi->dev, + ad7380_regulator_disable, vcm); + if (ret) + return ret; + + ret =3D regulator_get_voltage(vcm); + if (ret < 0) + return ret; + + st->vcm_mv[i] =3D ret / 1000; + } + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); if (IS_ERR(st->regmap)) return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), @@ -413,12 +487,16 @@ static int ad7380_probe(struct spi_device *spi) static const struct of_device_id ad7380_of_match_table[] =3D { { .compatible =3D "adi,ad7380", .data =3D &ad7380_chip_info }, { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, + { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, + { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, { } }; =20 static const struct spi_device_id ad7380_id_table[] =3D { { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, + { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, + { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7380_id_table); --=20 2.44.0 From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FB3316FF36 for ; Tue, 28 May 2024 14:20:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906048; cv=none; b=fEv3lvyZYXeVUf0/F2cnn4ue4s5DtlrfRWrfAmG+operY4XimMmd/wGszQN6pzVOT5zwrJv0Q7nZl62Si7ai9D4djoH0K/KcSkvlyMExUnFyTGsYwWCL+kXdWvZEE7HTc73K62j5SVwF0WTd36D3w6S27rJnuMW9xxN59tHnGOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906048; c=relaxed/simple; bh=QF68x+vMZHjMq9zYLgUVSZ+b3LIpttZDV0zyyy/wbQU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gFUgY4FK3z28JaD4o7KtHdqtr57t3o5AwOBdFcga/j0CzUG90kOvF6fQsAddKvZRGV0B5LQa4Oz33sfJByR/99K1wl7sx8fDRZsE58mh5XkWN9ehFEjddkXsb60wlMYhYXyOwRSBYhO7ZLxdMKn/MlAy9vL9d8sW3tmVgAdiH/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=qLafSer+; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="qLafSer+" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-42101a2ac2cso7092245e9.0 for ; Tue, 28 May 2024 07:20:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906042; x=1717510842; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dZh5j2uCvXBtaNyL3cov+Xu0A8wLUMvvdwWCENNHfqE=; b=qLafSer+PR7Q/A7HSmKK+UZMfpeEjtQDMMIF1OWU5jI6XJggDNZJoTmiB0nhDsSbZP u832eM9Vj+weTF/UauxJD8REMBrr+EwuQuqd+dn7X9oRIwmolIUgY+xqsoSDq2H1fgvZ +Y4epO8lw7QFKG+DwgFN7Rpybu1p7ddpVyUyKgBM6iEndooZgfwEJ/OdyP1gcrNrGl+Z wlIjAmv6HtC8xL8ykIC4WYXkw9y35yMNf+ffu3al8oZm5zsXWalpeg/YhNwPxVkLaZj/ /rdnDde2SYIgvQ0j71a+esiDdEmi2ri02gAL4/taggBnHa6Ajw1FOy+aXpFH7W+cHcMN yZng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906042; x=1717510842; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dZh5j2uCvXBtaNyL3cov+Xu0A8wLUMvvdwWCENNHfqE=; b=YEvg7ZBNS/50Bi2BLcF5LGBJ9dYuncwXDBLKpckWI2IVmN3O1oCFtxEz19mnHzqdHI NDHhei0PRkbAcV008MaB4iESTieqXvkWBGUBPomCxdcGEco7EDVagBv8EKX6TYa/2xeJ zltqtCFm/8vRV+3Lj4rHpRXwpr9gXlKkQ11+S8lqpPcdgAbNhTBI0qNGjnkHVcJNMIx2 nRp8EYCwA09mqKlK8c5jp8og8UOfT61mSoCLqA5RR2uENq+LTfEjL62tssve/Y9L3EfA UYdwG1yAALSH2Vm5fSbj+PZ/yadb2h5LbSJmj/OcDNN1Y7Og0GmUdB1jO2QF0Za5oS4d mfIA== X-Forwarded-Encrypted: i=1; AJvYcCVcd6M4E1cyoeAX1GQiGeQcplBJnRbfQDvcMFu9q7BsQWEj3VarT6L9jBzRyErVm8vlXOmqdBQof8i18EEpqV4GdYKh+CdS2X/0eG6J X-Gm-Message-State: AOJu0Yyj5E0ydDNRwZRCXPnLzXH6Lw1GgV3d/YESfsC3JHoHsw9Z+He8 zlhaVbH6WVNVQa6892bSplgCYMWJNnXUGRWzbkSCx73t2elY4tpIGEWw0h2d3Ws= X-Google-Smtp-Source: AGHT+IGnnuc64zTUf2E/L2uG0lvJ7iB0PRLj/xKheGG/foJ6wTIRxnf1Dapre87VE1Tlaab0q8TSIQ== X-Received: by 2002:a05:6000:1188:b0:356:50e7:e942 with SMTP id ffacd0b85a97d-35650e7eda5mr7250240f8f.61.1716906041995; Tue, 28 May 2024 07:20:41 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:41 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:32 +0200 Subject: [PATCH v7 5/7] iio: adc: ad7380: prepare for parts with more channels Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-5-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 The current driver supports only parts with 2 channels. In order to prepare the support of new compatible ADCs with more channels, this commit: - defines MAX_NUM_CHANNEL to specify the maximum number of channels currently supported by the driver - adds available_scan_mask member in ad7380_chip_info structure - fixes spi xfer struct len depending on number of channels - fixes scan_data.raw buffer size to handle more channels - adds a timing specifications structure in ad7380_chip_info structure Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 4ad283cf970d..790d08c90ad0 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -27,6 +27,7 @@ #include #include =20 +#define MAX_NUM_CHANNELS 2 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -63,12 +64,19 @@ #define AD7380_ALERT_LOW_TH GENMASK(11, 0) #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) =20 +#define T_CONVERT_NS 190 /* conversion time */ +struct ad7380_timing_specs { + const unsigned int t_csh_ns; /* CS minimum high time */ +}; + struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; const char * const *vcm_supplies; unsigned int num_vcm_supplies; + const unsigned long *available_scan_masks; + const struct ad7380_timing_specs *timing_specs; }; =20 #define AD7380_CHANNEL(index, bits, diff) { \ @@ -113,16 +121,24 @@ static const unsigned long ad7380_2_channel_scan_mask= s[] =3D { 0 }; =20 +static const struct ad7380_timing_specs ad7380_timing =3D { + .t_csh_ns =3D 10, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, .num_channels =3D ARRAY_SIZE(ad7380_channels), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7381_chip_info =3D { .name =3D "ad7381", .channels =3D ad7381_channels, .num_channels =3D ARRAY_SIZE(ad7381_channels), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7383_chip_info =3D { @@ -131,6 +147,8 @@ static const struct ad7380_chip_info ad7383_chip_info = =3D { .num_channels =3D ARRAY_SIZE(ad7383_channels), .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7384_chip_info =3D { @@ -139,6 +157,8 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .num_channels =3D ARRAY_SIZE(ad7384_channels), .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 struct ad7380_state { @@ -146,15 +166,16 @@ struct ad7380_state { struct spi_device *spi; struct regmap *regmap; unsigned int vref_mv; - unsigned int vcm_mv[2]; + unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. - * Make the buffer large enough for 2 16-bit samples and one 64-bit + * Make the buffer large enough for MAX_NUM_CHANNELS 16-bit samples and o= ne 64-bit * aligned 64 bit timestamp. + * As MAX_NUM_CHANNELS is 2 the layout of the structure is the same for a= ll parts */ struct { - u16 raw[2]; + u16 raw[MAX_NUM_CHANNELS]; =20 s64 ts __aligned(8); } scan_data __aligned(IIO_DMA_MINALIGN); @@ -192,7 +213,7 @@ static int ad7380_regmap_reg_read(void *context, unsign= ed int reg, .tx_buf =3D &st->tx, .cs_change =3D 1, .cs_change_delay =3D { - .value =3D 10, /* t[CSH] */ + .value =3D st->chip_info->timing_specs->t_csh_ns, .unit =3D SPI_DELAY_UNIT_NSECS, }, }, { @@ -247,7 +268,8 @@ static irqreturn_t ad7380_trigger_handler(int irq, void= *p) struct ad7380_state *st =3D iio_priv(indio_dev); struct spi_transfer xfer =3D { .bits_per_word =3D st->chip_info->channels[0].scan_type.realbits, - .len =3D 4, + .len =3D (st->chip_info->num_channels - 1) * + BITS_TO_BYTES(st->chip_info->channels->scan_type.storagebits), .rx_buf =3D st->scan_data.raw, }; int ret; @@ -274,21 +296,22 @@ static int ad7380_read_direct(struct ad7380_state *st, .speed_hz =3D AD7380_REG_WR_SPEED_HZ, .bits_per_word =3D chan->scan_type.realbits, .delay =3D { - .value =3D 190, /* t[CONVERT] */ + .value =3D T_CONVERT_NS, .unit =3D SPI_DELAY_UNIT_NSECS, }, .cs_change =3D 1, .cs_change_delay =3D { - .value =3D 10, /* t[CSH] */ + .value =3D st->chip_info->timing_specs->t_csh_ns, .unit =3D SPI_DELAY_UNIT_NSECS, }, }, - /* then read both channels */ + /* then read all channels */ { .speed_hz =3D AD7380_REG_WR_SPEED_HZ, .bits_per_word =3D chan->scan_type.realbits, .rx_buf =3D st->scan_data.raw, - .len =3D 4, + .len =3D (st->chip_info->num_channels - 1) * + ((chan->scan_type.storagebits > 16) ? 4 : 2), }, }; int ret; @@ -469,7 +492,7 @@ static int ad7380_probe(struct spi_device *spi) indio_dev->name =3D st->chip_info->name; indio_dev->info =3D &ad7380_info; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->available_scan_masks =3D ad7380_2_channel_scan_masks; + indio_dev->available_scan_masks =3D st->chip_info->available_scan_masks; =20 ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, iio_pollfunc_store_time, --=20 2.44.0 From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B49116FF59 for ; Tue, 28 May 2024 14:20:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906047; cv=none; b=WRq97DpU5o8ioCroKl1mGKn+sit+MvyoCqoJi5e/jPowq4OTg9B94BZN2ck1hkbyFWe78/Qm37DRxxyS+Ol9JpIQas0VzP4ucUQDAes8N37t1zJbG6dcgRxfqOPU4z6Cc+Gtu8+IO13f7zdzOBrJFetewQj29xIwdS6m7lUgCSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906047; c=relaxed/simple; bh=VQ4RPFjraeg9QG+WtxUK0LxObNrAlrRgeIFZywlwUq0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ldqRqWA0RBFgjBbHveUch35DsN4W3wgwGaOztPM9caAypSDGy28ooY/FXNRtaRQeM6mKU1uldjS/R8osnt0azsDPsLVkrHK5dewV9KqxAq+FCbCtzzNXk0Zq2Zb5lhDi95jYqNlTEzSsIsjx31u2B4fSCubRPqsLi3gRlJ1BDNA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=wFwd0Maw; arc=none smtp.client-ip=209.85.221.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="wFwd0Maw" Received: by mail-wr1-f65.google.com with SMTP id ffacd0b85a97d-354de97586cso1079431f8f.0 for ; Tue, 28 May 2024 07:20:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906043; x=1717510843; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7kVmMiAww/1MNzSxxAk2mzn+IJ9yIpCfeirFaQBWWao=; b=wFwd0Maw8rJdEgBMSEk7MsgOfZsAd3dGyixE4aEcmnTLXRfXGfuwQ3MBvl3Gms+Es+ ifETO1YlnDHSS4qNA7DMf1uxP/VkOxN4UJpOi4GQZtaCAn7DjnjKLsWFnYP1RD2Zud0t 1bfoYrW+W9WgxFjitMGTgunioGs7FdO4WLwY3TgWcDqDOekMAUP5tCxiBlwvZcFgzR9z Gql8XZfJmyR3QCmGlUWWY12j+48RWqT+umTsBykDM6ZPMx/9MTnErU6JiypyUtH0sIRi 6xqex9hnWek1IPfrfE4w4EfMMTUO9Zf8RjZYOnF/gqomt/64+yrR3zPoeTwpBLPBS5Fr bR/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906043; x=1717510843; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7kVmMiAww/1MNzSxxAk2mzn+IJ9yIpCfeirFaQBWWao=; b=nvC1Ifw3IcRU7yR7lVHbzf4NmIxw6zj1Pnrk7DgTiRKeysgzOAsMdaLROM3TRUOKP6 XSHVVEom3XgZofxrz5KkSo6KeQDU1a1SkEH1LRcgHqxV4tL097Y81rPTiaWXFtOUAdWg YmnAGYMzV/0PdGvRId6RKaJNmUdUfyw0dWTXjSBVbTtprgFp3Nse1dGf5oj0F0N/njMC tyGTD1ZqV29a7T28MEHQSFV3t8VBitWo8shgEPRHiv4fbnUniKCiuNkdlP/Th+DW/44h QSuLr03T1yeBVX8oS6+LOpcH1ZW3Snmf4fJJYljznfpQm0tVizrzGODAGaOY8qZjXsNx al2Q== X-Forwarded-Encrypted: i=1; AJvYcCWBpXj1eBkMVmeh7SNnjwfnBDQ5g7QDLSa0XSweAfki8LCgHRZt6LdcSiUVd7hYHymCL74GoOq0lndngWI6Ex7pMpJVVAeyCt6tW9cx X-Gm-Message-State: AOJu0YywNB/M69lw8MvrNLNxniB/PaBnbeKoHC2bvipjIpZeaUVoHNLD wdHIbm4G28m3CV110H27NfCPdwcGaIjH2sxwXm9bbpKGMJs5U/W+06rnWIE8cjQ= X-Google-Smtp-Source: AGHT+IFP31QoKYFXOEzwlSrrEb3FVw4HSZ2x5WtfZZWQ7ssD6CTt6H9FKMLjuILaLjqwIF9nhUApUA== X-Received: by 2002:a5d:49cc:0:b0:354:db85:3039 with SMTP id ffacd0b85a97d-3552fe19407mr8128986f8f.44.1716906042936; Tue, 28 May 2024 07:20:42 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:42 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:33 +0200 Subject: [PATCH v7 6/7] dt-bindings: iio: adc: ad7380: add support for ad738x-4 4 channels variants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-6-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan , Conor Dooley X-Mailer: b4 0.13.0 Add compatible support for ad7380/1/3/4-4 parts which are 4 channels variants from ad7380/1/3/4 Signed-off-by: Julien Stephan Acked-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index de3d28a021ae..899b777017ce 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -15,6 +15,10 @@ description: | * https://www.analog.com/en/products/ad7381.html * https://www.analog.com/en/products/ad7383.html * https://www.analog.com/en/products/ad7384.html + * https://www.analog.com/en/products/ad7380-4.html + * https://www.analog.com/en/products/ad7381-4.html + * https://www.analog.com/en/products/ad7383-4.html + * https://www.analog.com/en/products/ad7384-4.html =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -25,6 +29,10 @@ properties: - adi,ad7381 - adi,ad7383 - adi,ad7384 + - adi,ad7380-4 + - adi,ad7381-4 + - adi,ad7383-4 + - adi,ad7384-4 =20 reg: maxItems: 1 @@ -56,6 +64,16 @@ properties: The common mode voltage supply for the AINB- pin on pseudo-different= ial chips. =20 + ainc-supply: + description: + The common mode voltage supply for the AINC- pin on pseudo-different= ial + chips. + + aind-supply: + description: + The common mode voltage supply for the AIND- pin on pseudo-different= ial + chips. + interrupts: description: When the device is using 1-wire mode, this property is used to optio= nally @@ -79,6 +97,8 @@ allOf: enum: - adi,ad7383 - adi,ad7384 + - adi,ad7383-4 + - adi,ad7384-4 then: required: - aina-supply @@ -87,6 +107,20 @@ allOf: properties: aina-supply: false ainb-supply: false + - if: + properties: + compatible: + enum: + - adi,ad7383-4 + - adi,ad7384-4 + then: + required: + - ainc-supply + - aind-supply + else: + properties: + ainc-supply: false + aind-supply: false =20 examples: - | --=20 2.44.0 From nobody Tue Dec 16 16:39:14 2025 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 200ED170839 for ; Tue, 28 May 2024 14:20:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906047; cv=none; b=dYoqkYG0iceo8XUzw/TFXjqbDR0vCMjLyIzHZH1IVmebL2Fi4ZUqXaHytLSXpUDDYs0mWvJJDGiLT0VF+7NOmefOkwkRnlpOJjjCU5HtA7pu3vcmSJZJUY0LYD4bdhAl1PGpXf2SQI0K9m+Svc74Y+0IDt62+i3e6NHKfWLDkho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716906047; c=relaxed/simple; bh=Zzso1sxK6Q/UMw8mWkOfuHFaXKWw5NzczerMMf94Meg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hq5CCidlewSvLbWJD1aPA+ruyQ1UA35Lrvbfd9gLfYkfqNKZBskACs+zEvmZr7iuIETnUvn5M5/42Ws1NlJZaPbFeVaNNoFBAf6wE03l5/guOr5ySvyrGc6XmNz2cS+R8zCKbr0jAIgkfNMdwy4Po/NelphFS0FeO0vqVaMVfEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=mmXpWCkw; arc=none smtp.client-ip=209.85.128.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="mmXpWCkw" Received: by mail-wm1-f67.google.com with SMTP id 5b1f17b1804b1-42108822e3cso23616565e9.0 for ; Tue, 28 May 2024 07:20:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1716906043; x=1717510843; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZKaoQYw7yNqBcZbbeNBd7Up3BviKXiLpwv87L7N/DuE=; b=mmXpWCkwckaAuF5+yQbdbs9VoAn5xZt7feFWYTzCi+uUHjQ17EJ01ve7CXY1lpkqkF sp5cr+kgcXZ47D5z+HzOxY61d/1lHiiVOTuSvGkX4Wg94u/MY1haG+LP+hDP7EJIpsL6 8YZqHNXV6GhyX0CQVFMMMNYGztLZgN0LCsVL8+HRQhuAuk5SxZwUjIjMaZLv+CUd0v02 fDue385iIRMHbZFA0w5J5nhxsIhrmWYA4u1nLOjkw85e3CFfGvxTlOY0UF0k4OcvmHtn EInodbUwc9txIV7mam9hPvA/pSEUMB6Tq0927uC88p5K1cx/950rjHszn3IRhPLplCe/ Dt9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716906043; x=1717510843; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZKaoQYw7yNqBcZbbeNBd7Up3BviKXiLpwv87L7N/DuE=; b=ISuahZ/NU372bMhw1jNkLVYXvAq9kSRIHxPKCABy7nZGYRHL0blpCIY76nHesRLtuA VI+1qQt+Hp0oryVi9dQYyJNcO5PRPZs70FVrJaguyAMfkt91IojaC9tCRmL8mQpzabZE wAxMvJCHqESfot3dVB8TOzJzKoAMeX7B+xSMnHXUYZR77WzatLfPso5WewogPzbBP5fL O8hLTMkt2vHZtDnziGlmucWYCcaCxh+ndk9RayXkIcXxGmU6qHKBG5a8YMMtAp1pJOpd 0c/idQ8LQdnJeYuATEC9T/OuNOqbtUtDl321zZ4r/x8CQRbajLI4OwJWz/t4agybk97z kyiQ== X-Forwarded-Encrypted: i=1; AJvYcCXkAnytLKJVx4UwvdF/lBBfJ5/g90MyF345P2IGUKu3+9KApTdm1qKGgcTcrt7J1r6nECP0wb6D8aTiPOsc7JueEaOfHfSQ6Z42GhXG X-Gm-Message-State: AOJu0YxY5FvideaSB2QQnv+ccDwCngWtsM3V521h9Ig+kl0fivTw5kJZ ef0U0PlQF23k14WKdjttWTVxu5yNuwG7cdLWS5UIwyq+teJ6fKlA5FCW/2JISDrjfA1yYXIjxlW ZRI0Wyq7q X-Google-Smtp-Source: AGHT+IEQX+B45eG3mvmnIMj7QY5BU8cvy92fKruQUXncFnMv/tK/TI5wgfM30c4k5cgHa+jpjJTStg== X-Received: by 2002:a05:6000:1942:b0:358:d9d4:1026 with SMTP id ffacd0b85a97d-358d9d411a5mr6053075f8f.17.1716906043624; Tue, 28 May 2024 07:20:43 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35579d7db5esm11999275f8f.15.2024.05.28.07.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 07:20:43 -0700 (PDT) From: Julien Stephan Date: Tue, 28 May 2024 16:20:34 +0200 Subject: [PATCH v7 7/7] iio: adc: ad7380: add support for ad738x-4 4 channels variants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240528-adding-new-ad738x-driver-v7-7-4cd70a4c12c8@baylibre.com> References: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> In-Reply-To: <20240528-adding-new-ad738x-driver-v7-0-4cd70a4c12c8@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: kernel test robot , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Stephan X-Mailer: b4 0.13.0 Add support for ad7380/1/2/3-4 parts which are 4 channels variants from ad7380/1/2/3 Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 77 ++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 790d08c90ad0..6b0b1b0be363 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -8,6 +8,9 @@ * Datasheets of supported parts: * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7383-7384.pdf + * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7380-4.pdf + * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf + * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf */ =20 #include @@ -27,7 +30,7 @@ #include #include =20 -#define MAX_NUM_CHANNELS 2 +#define MAX_NUM_CHANNELS 4 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -104,27 +107,53 @@ static const struct iio_chan_spec name[] =3D { \ IIO_CHAN_SOFT_TIMESTAMP(2), \ } =20 +#define DEFINE_AD7380_4_CHANNEL(name, bits, diff) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits, diff), \ + AD7380_CHANNEL(1, bits, diff), \ + AD7380_CHANNEL(2, bits, diff), \ + AD7380_CHANNEL(3, bits, diff), \ + IIO_CHAN_SOFT_TIMESTAMP(4), \ +} + /* fully differential */ DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); +DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1); +DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1); /* pseudo differential */ DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); +DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0); +DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0); =20 static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", }; =20 +static const char * const ad7380_4_channel_vcm_supplies[] =3D { + "aina", "ainb", "ainc", "aind", +}; + /* Since this is simultaneous sampling, we don't allow individual channels= . */ static const unsigned long ad7380_2_channel_scan_masks[] =3D { GENMASK(1, 0), 0 }; =20 +static const unsigned long ad7380_4_channel_scan_masks[] =3D { + GENMASK(3, 0), + 0 +}; + static const struct ad7380_timing_specs ad7380_timing =3D { .t_csh_ns =3D 10, }; =20 +static const struct ad7380_timing_specs ad7380_4_timing =3D { + .t_csh_ns =3D 20, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, @@ -161,6 +190,42 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .timing_specs =3D &ad7380_timing, }; =20 +static const struct ad7380_chip_info ad7380_4_chip_info =3D { + .name =3D "ad7380-4", + .channels =3D ad7380_4_channels, + .num_channels =3D ARRAY_SIZE(ad7380_4_channels), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7381_4_chip_info =3D { + .name =3D "ad7381-4", + .channels =3D ad7381_4_channels, + .num_channels =3D ARRAY_SIZE(ad7381_4_channels), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7383_4_chip_info =3D { + .name =3D "ad7383-4", + .channels =3D ad7383_4_channels, + .num_channels =3D ARRAY_SIZE(ad7383_4_channels), + .vcm_supplies =3D ad7380_4_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7384_4_chip_info =3D { + .name =3D "ad7384-4", + .channels =3D ad7384_4_channels, + .num_channels =3D ARRAY_SIZE(ad7384_4_channels), + .vcm_supplies =3D ad7380_4_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; @@ -172,7 +237,7 @@ struct ad7380_state { * transfer buffers to live in their own cache lines. * Make the buffer large enough for MAX_NUM_CHANNELS 16-bit samples and o= ne 64-bit * aligned 64 bit timestamp. - * As MAX_NUM_CHANNELS is 2 the layout of the structure is the same for a= ll parts + * As MAX_NUM_CHANNELS is 4 the layout of the structure is the same for a= ll parts */ struct { u16 raw[MAX_NUM_CHANNELS]; @@ -512,6 +577,10 @@ static const struct of_device_id ad7380_of_match_table= [] =3D { { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, + { .compatible =3D "adi,ad7380-4", .data =3D &ad7380_4_chip_info }, + { .compatible =3D "adi,ad7381-4", .data =3D &ad7381_4_chip_info }, + { .compatible =3D "adi,ad7383-4", .data =3D &ad7383_4_chip_info }, + { .compatible =3D "adi,ad7384-4", .data =3D &ad7384_4_chip_info }, { } }; =20 @@ -520,6 +589,10 @@ static const struct spi_device_id ad7380_id_table[] = =3D { { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, + { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, + { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, + { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, + { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7380_id_table); --=20 2.44.0