From nobody Wed Feb 11 07:26:13 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77CD513AA5A; Mon, 27 May 2024 09:39:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802755; cv=none; b=AxA2O/f9UEh9AF0lQRO01qXPAEoDivAMm12r4gichjXeBsgsuwt1t6pHou3hC95SOtmyHpxXtnhDuYdz5CGvjqVn+pn/fjBa0oX+nmD/OjRluzmnzSBCAnIrEP/ITeimT/q9wmZreJ56vgFsACj7sWDnXrN/J3wQwFnSy/a080g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802755; c=relaxed/simple; bh=/Pi5oJU7aEoIDdHU8CS0oZMV/OUfjI2UVTwuZAZZZoU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ARk3fdVKQjadvp3fNt+iANaLXbw5bP+Ma93np6rzQd0p1NOSLFIAmnRwIyRirTiCrF6jWd1NAgcb8d9bgP2C3yJBxTVIqOsDQc/P7a+IHi93U8X/b4Nkugq1DT0qkFRpl3haapKU352iFMlgamntfUFPAwh6W0sP3+efcn3N/dk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=uDju4Zop; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="uDju4Zop" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1716802752; bh=/Pi5oJU7aEoIDdHU8CS0oZMV/OUfjI2UVTwuZAZZZoU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uDju4ZopbhFdpJxkuzKCxrtzDM/whBB0cpilfSHMcBV0UbANXRP1PZ+MUeTHO5cmC ZdLTy2m5HqdT7hcr0TrN0+vk6wpbJ15c8065nn4x8Rr9+imowysMod/LR84jjyL60H tLkJcz1eA6Yp1U9KwMT0r/N7oa3q/icUO91W8JdtR+zpPZzVZg+Dm6QflXq3IgRVm+ FaqyRXSEAIuTxy+Zi9q1eNP9WRgcX9RoBPwIp6YOyUaqaBg5gGL02JYyqFJA7m/bxX B7kPe3ArGKQbOauzIV1+XrlHbgk8CU8p77IGl0GCtlDTMv2WgaspNBMk9+T0I8pS4a Hqi/jP8jh6ftg== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id DDFC3378203F; Mon, 27 May 2024 09:39:11 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, mandyjh.liu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, jpanis@baylibre.com Subject: [PATCH 1/5] dt-bindings: mfd: mediatek,mt8195-scpsys: Add support for MT8188 Date: Mon, 27 May 2024 11:39:04 +0200 Message-ID: <20240527093908.97574-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> References: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for the scpsys block found in the MediaTek MT8188 SoC. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.y= aml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml index c8c4812fffe2..a0d646dfec42 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt8173-scpsys - mediatek,mt8183-scpsys - mediatek,mt8186-scpsys + - mediatek,mt8188-scpsys - mediatek,mt8192-scpsys - mediatek,mt8195-scpsys - const: syscon --=20 2.45.1 From nobody Wed Feb 11 07:26:13 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A69F13AD0D; Mon, 27 May 2024 09:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802757; cv=none; b=CPDUAVCYouT7byScGakOnZEzlrvaSld6PT6sQuyDRgSL2x17ZqVmG5VKCB4VL+6q075+fVkB1DmcMbcUycOHswgITMq+ZFH8WUDdQUNryUl6IJEOsF0+td3yqoMPUI5gch3jug2Tj8jHY7pQFc+7oBeK3uroPt1ZSnCeDzgIW1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802757; c=relaxed/simple; bh=Q2u/g27bjls/di+Or+gNHb/H3YwXTAj8oy8HXh0H9UE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DILHabnToGHH/Ok5gDQHuWFRvryHykiX+qbcyDvnWomrZiKoBoWnF6RxqX+siD9ErM7XoTTVnALJmJTeRQ+AWZHajuFGnNLLorLr60+Rn9CUkovN+ZfMUan+gpzpHgyE/OwY/ueXh0wIe3LQyFgW1FsQ0bnBxSllyB0EgZ268TQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ur6wXGsn; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ur6wXGsn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1716802753; bh=Q2u/g27bjls/di+Or+gNHb/H3YwXTAj8oy8HXh0H9UE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ur6wXGsn0VGcFITfHnFT9w6tExhutj/M+wRTnG0nmsRXNaBRKDDzB/oYD1kREnvGQ Ml0yjmKmIzQ/4adS0XKlkG2uLDADAe7IbwJqDCRtnQWPhMI5JkTvTi+Cu6R9KL/UTh 3+WLWJo0v2rSOXEVzI9ACsuIx02PywDf5dMLhuLYhkq3657tx0rI65DylIL5GJSUTq 7TmbpsaTyp+mxZEaX9QU5ekEDWMqMLGC3P2sL9PKu3eQhDOch6FZiRB3UPKndxMUl/ 82VIT2MVuAU0rFqvuYEuh/m46K63z1PyTIyHFib0fWfu6+zG7YYxk4LkdzEuD91p9D JbFSe2dZJuR2Q== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 079973782113; Mon, 27 May 2024 09:39:12 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, mandyjh.liu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, jpanis@baylibre.com Subject: [PATCH 2/5] arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes Date: Mon, 27 May 2024 11:39:05 +0200 Message-ID: <20240527093908.97574-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> References: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding multimedia nodes and power domains, add support for the two Global Command Engine (GCE) mailboxes found in this SoC. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index b4315c9214dc..06fa3b862c31 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -413,6 +414,22 @@ pwrap: pwrap@10024000 { clock-names =3D "spi", "wrap"; }; =20 + gce0: mailbox@10320000 { + compatible =3D "mediatek,mt8188-gce"; + reg =3D <0 0x10320000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <2>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible =3D "mediatek,mt8188-gce"; + reg =3D <0 0x10330000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <2>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp: scp@10500000 { compatible =3D "mediatek,mt8188-scp"; reg =3D <0 0x10500000 0 0x100000>, --=20 2.45.1 From nobody Wed Feb 11 07:26:13 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA82913AD3E; Mon, 27 May 2024 09:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802758; cv=none; b=gh4SjMjMQK/ImdGx/eQ9LLR4O8ocdpoOWZcXB3AxPop/ugRu4g167PtAECiCHEgTowdssGs259dYCyvbUC2pm970ViG2iZaduxf0+y2djw0vlBrqlNHIA0dj0qy4jPUN2y253ENL/INdISOaJZsNOPjahXmkIJcgFqMWSJPwvxA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802758; c=relaxed/simple; bh=OiPBAFsu0z+fLHyKUPGOZVRQqVDS03RDPW95gydTYUc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=svbUmmU/QmGRwDcggNcO9b6qC8P4GZh/0XkzNySu+4BxIbOhzVSnrQBP/j+ZuLUK/hD4BROSQxMsFVeIXK2j801Hl/G7oNHOeiCvkJRc4xYtR/oNs5W645YnSQjLg9aKX4FF/BDkn7gatvZEkw6MXpaorJS5gfrJuUAabq1TNDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qe8BeP9Z; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qe8BeP9Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1716802755; bh=OiPBAFsu0z+fLHyKUPGOZVRQqVDS03RDPW95gydTYUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qe8BeP9Z5JJLAQoxQykrmznc8aBQZesyg1HM/YgTqwUcst8/PhQ7I7odtQoXtMsj4 qDxi8Nk8jM+DkkrXIkbWRhKq1S9d2JhoeKidroGU9mEn956Y72uEEx7R8HaOYCEBaq oyShpxJ4xtqV4mmoCpA7Ougqcr4c23yXOYQANU52B/uTr+doxsLyAmvBvbu6nPgnA7 Ikc6qrv+uTQtBrCmFqze+iWJgxxXWC9Ne1fq08hd49+tldwGJo1d9LVE8qwD565Zcd Lyf5zhkBgCurLFWodNdus1+7UOVU1Mc9oiXIcCR+C3F9ZvmqhaDjWmEPCX6fV5zQAI 23fc0X3ySr5Ig== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 29CCA378212E; Mon, 27 May 2024 09:39:14 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, mandyjh.liu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, jpanis@baylibre.com Subject: [PATCH 3/5] arm64: dts: mediatek: mt8188: Add VDOSYS0/1 support for multimedia Date: Mon, 27 May 2024 11:39:06 +0200 Message-ID: <20240527093908.97574-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> References: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the two VDOSYS blocks in MT8188, later on used for various Multimedia related IP, including display and video codecs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 06fa3b862c31..84f2809eae7a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -969,5 +969,22 @@ vencsys: clock-controller@1a000000 { reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; }; + + vdosys0: syscon@1c01d000 { + compatible =3D "mediatek,mt8188-vdosys0", "syscon"; + reg =3D <0 0x1c01d000 0 0x1000>; + #clock-cells =3D <1>; + mboxes =3D <&gce0 0 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; + }; + + vdosys1: syscon@1c100000 { + compatible =3D "mediatek,mt8188-vdosys1", "syscon"; + reg =3D <0 0x1c100000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + mboxes =3D <&gce0 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0 0x1000>; + }; }; }; --=20 2.45.1 From nobody Wed Feb 11 07:26:13 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BACE913AA5C; Mon, 27 May 2024 09:39:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802759; cv=none; b=WZjaJLOl39yFqYigeqo2URcY+dgRAuNuQk1SDfRNP+FADgJiAq0JOeTMTFESADaqFnKotPyFkx4jO0Tcm7cs08D4/4dgQQl88guPqNcuQdiWmdQEnNKvFpkRvJq9oa441apoMM5I2ctRq4WwrxLhxXIPtkaMTxtz43dvrAML0fg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716802759; c=relaxed/simple; bh=Td33TX+uUVkJpO/PZzVilgGjh46whLu7yUwBuGLbx3M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hi4JX9jAVKlXQrRvHx1fzO9HnmDxhvXmyPUpkCZ0jBVERRDrJIh6Vji502J9UDCSLJ3iyAkNOnnup790gyle+xMZjrA4nWitvUFwNJEvaqAPAjwC0bLGXsG/MIvEZisK4Eo7DN2x4uQm/UR6WOtYPk/YiY9swSmI45r1CajE1q8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=kb/hu0AE; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="kb/hu0AE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1716802756; bh=Td33TX+uUVkJpO/PZzVilgGjh46whLu7yUwBuGLbx3M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kb/hu0AEnSsb/FXG4zqhv8U74gRCA9AGQ/BbefiDCmUlg6zY2geZX42TN3sVi/zuq dHtCDJ+ZK+Mlb16lG1V3lUMqtwLn3vVZbB2rJJWHvYs9JYTOp0ufTLusdRlvtwYWjq yblaH/gbAzFGCcbMRqGGe7Uocui321bOYA7AIq27jBnIM+dm7kIXkrgj4p0ICDa2Ur 4Oc/AGOgqns4JeWktpJelSKN/+7JgeuExdXNvBpHXgJA9+8R/fM0SXackrwShWLf7k 4I2pnL0UBsCw2dZVJK5SOVHBrIAHIDknVYiMGAXE4BtlxxQB8TKY7Cf/fUL9YjnxiG A0N/G8Tg0qlVg== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 4BADE3782146; Mon, 27 May 2024 09:39:15 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, mandyjh.liu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, jpanis@baylibre.com Subject: [PATCH 4/5] arm64: dts: mediatek: mt8188: Add support for SoC power domains Date: Mon, 27 May 2024 11:39:07 +0200 Message-ID: <20240527093908.97574-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> References: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for hardware IP that requires power switching, add the necessary power domains nodes for the MT8188 SoC. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 323 +++++++++++++++++++++++ 1 file changed, 323 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 84f2809eae7a..0bca6c9f15fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -384,6 +384,329 @@ pio: pinctrl@10005000 { #interrupt-cells =3D <2>; }; =20 + scpsys: syscon@10006000 { + compatible =3D "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; + reg =3D <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8188-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG1 { + reg =3D ; + clocks =3D <&topckgen CLK_APMIXED_MFGPLL>, + <&topckgen CLK_TOP_MFG_CORE_TMP>; + clock-names =3D "mfg", "alt"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG2 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG3 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG4 { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names =3D "top", "cam", "ccu", "img", "venc", + "vdec", "wpe", "cfgck", "cfgxo", + "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", + "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", + "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", + "ss-sram-rdr", "ss-iommu", "ss-imgcam", + "ss-emi", "ss-subcmn-rdr", "ss-rsi", + "ss-cmn-l4", "ss-vdec1", "ss-wpe", + "ss-cvdo-ve1"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>, + <&vdosys0 CLK_VDO0_APB_BUS>; + clock-names =3D "cfgck", "cfgxo", "ss-gals", + "ss-cmn", "ss-emi", "ss-iommu", + "ss-larb", "ss-rsi", "ss-bus"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, + <&vppsys1 CLK_VPP1_GALS5>, + <&vppsys1 CLK_VPP1_GALS6>, + <&vppsys1 CLK_VPP1_LARB5>, + <&vppsys1 CLK_VPP1_LARB6>; + clock-names =3D "cfgck", "cfgxo", + "ss-vpp1-g5", "ss-vpp1-g6", + "ss-vpp1-l5", "ss-vpp1-l6"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg =3D ; + clocks =3D <&vdecsys CLK_VDEC2_LARB1>; + clock-names =3D "ss-vdec"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC0 { + reg =3D ; + clocks =3D <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; + clock-names =3D "ss-vdec"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_CCU_AHB>, + <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; + clock-names =3D "cam", "ccu", "bus", "cfgck"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { + reg =3D ; + clocks =3D <&camsys CLK_CAM_MAIN_LARB13>, + <&camsys CLK_CAM_MAIN_LARB14>, + <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; + clock-names=3D "ss-cam-l13", "ss-cam-l14", + "ss-cam-mm0", "ss-cam-mm1", + "ss-camsys"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { + reg =3D ; + clocks =3D <&camsys CLK_CAM_MAIN_CAM_SUBB>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>; + clock-names =3D "ss-camb-sub", + "ss-camb-raw", + "ss-camb-yuv"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { + reg =3D; + clocks =3D <&camsys CLK_CAM_MAIN_CAM_SUBA>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>; + clock-names =3D "ss-cama-sub", + "ss-cama-raw", + "ss-cama-yuv"; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names =3D "cfgck", "cfgxo", "ss-larb2", + "ss-larb3", "ss-gals"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_HDMI_TX { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP_24M>; + clock-names =3D "bus", "hdcp"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_DP_TX { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_EDP_TX { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VENC { + reg =3D ; + clocks =3D <&vencsys CLK_VENC1_LARB>, + <&vencsys CLK_VENC1_VENC>, + <&vencsys CLK_VENC1_GALS>, + <&vencsys CLK_VENC1_GALS_SRAM>; + clock-names =3D "ss-ve1-larb", "ss-ve1-core", + "ss-ve1-gals", "ss-ve1-sram"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_WPE { + reg =3D ; + clocks =3D <&wpesys CLK_WPE_TOP_SMI_LARB7>, + <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; + clock-names =3D "ss-wpe-l7", "ss-wpe-l7pce"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + clocks =3D <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names =3D "ss-pextp-fmem"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names =3D "seninf0", "seninf1"; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP_AO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_ADSP>; + clock-names =3D "bus", "main"; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_ASM_H>; + clock-names =3D "asm"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; + clock-names =3D "a1sys", "intbus", "adspck"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP { + reg =3D ; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_ETHER { + reg =3D ; + clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names =3D "ethermac"; + mediatek,infracfg =3D <&infracfg_ao>; + #power-domain-cells =3D <0>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible =3D "mediatek,mt8188-wdt"; reg =3D <0 0x10007000 0 0x100>; --=20 2.45.1 From nobody Wed Feb 11 07:26:13 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0069013C822; 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Mon, 27 May 2024 09:39:16 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, mandyjh.liu@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, jpanis@baylibre.com Subject: [PATCH 5/5] arm64: dts: mediatek: mt8188: Add support for Mali GPU on Panfrost Date: Mon, 27 May 2024 11:39:08 +0200 Message-ID: <20240527093908.97574-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> References: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the necessary OPP table for the GPU and also add a GPU node to enable support for the Valhall-JM G57 MC3 found on this SoC, using the Panfrost driver. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 123 +++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 0bca6c9f15fe..29d012d28edb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -294,6 +294,112 @@ clk32k: oscillator-32k { clock-output-names =3D "clk32k"; }; =20 + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-390000000 { + opp-hz =3D /bits/ 64 <390000000>; + opp-microvolt =3D <575000>; + opp-supported-hw =3D <0xff>; + }; + opp-431000000 { + opp-hz =3D /bits/ 64 <431000000>; + opp-microvolt =3D <587500>; + opp-supported-hw =3D <0xff>; + }; + opp-473000000 { + opp-hz =3D /bits/ 64 <473000000>; + opp-microvolt =3D <600000>; + opp-supported-hw =3D <0xff>; + }; + opp-515000000 { + opp-hz =3D /bits/ 64 <515000000>; + opp-microvolt =3D <612500>; + opp-supported-hw =3D <0xff>; + }; + opp-556000000 { + opp-hz =3D /bits/ 64 <556000000>; + opp-microvolt =3D <625000>; + opp-supported-hw =3D <0xff>; + }; + opp-598000000 { + opp-hz =3D /bits/ 64 <598000000>; + opp-microvolt =3D <637500>; + opp-supported-hw =3D <0xff>; + }; + opp-640000000 { + opp-hz =3D /bits/ 64 <640000000>; + opp-microvolt =3D <650000>; + opp-supported-hw =3D <0xff>; + }; + opp-670000000 { + opp-hz =3D /bits/ 64 <670000000>; + opp-microvolt =3D <662500>; + opp-supported-hw =3D <0xff>; + }; + opp-700000000 { + opp-hz =3D /bits/ 64 <700000000>; + opp-microvolt =3D <675000>; + opp-supported-hw =3D <0xff>; + }; + opp-730000000 { + opp-hz =3D /bits/ 64 <730000000>; + opp-microvolt =3D <687500>; + opp-supported-hw =3D <0xff>; + }; + opp-760000000 { + opp-hz =3D /bits/ 64 <760000000>; + opp-microvolt =3D <700000>; + opp-supported-hw =3D <0xff>; + }; + opp-790000000 { + opp-hz =3D /bits/ 64 <790000000>; + opp-microvolt =3D <712500>; + opp-supported-hw =3D <0xff>; + }; + opp-835000000 { + opp-hz =3D /bits/ 64 <835000000>; + opp-microvolt =3D <731250>; + opp-supported-hw =3D <0xff>; + }; + opp-880000000 { + opp-hz =3D /bits/ 64 <880000000>; + opp-microvolt =3D <750000>; + opp-supported-hw =3D <0xff>; + }; + opp-915000000 { + opp-hz =3D /bits/ 64 <915000000>; + opp-microvolt =3D <775000>; + opp-supported-hw =3D <0x8f>; + }; + opp-915000000-5 { + opp-hz =3D /bits/ 64 <915000000>; + opp-microvolt =3D <762500>; + opp-supported-hw =3D <0x30>; + }; + opp-915000000-6 { + opp-hz =3D /bits/ 64 <915000000>; + opp-microvolt =3D <750000>; + opp-supported-hw =3D <0x70>; + }; + opp-950000000 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <800000>; + opp-supported-hw =3D <0x8f>; + }; + opp-950000000-5 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <775000>; + opp-supported-hw =3D <0x30>; + }; + opp-950000000-6 { + opp-hz =3D /bits/ 64 <950000000>; + opp-microvolt =3D <750000>; + opp-supported-hw =3D <0x70>; + }; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupt-parent =3D <&gic>; @@ -1167,6 +1273,23 @@ imp_iic_wrap_en: clock-controller@11ec2000 { #clock-cells =3D <1>; }; =20 + gpu: gpu@13000000 { + compatible =3D "mediatek,mt8188-mali", "arm,mali-valhall-jm"; + reg =3D <0 0x13000000 0 0x4000>; + + clocks =3D <&mfgcfg CLK_MFGCFG_BG3D>; + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_MFG2>, + <&spm MT8188_POWER_DOMAIN_MFG3>, + <&spm MT8188_POWER_DOMAIN_MFG4>; + power-domain-names =3D "core0", "core1", "core2"; + status =3D "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible =3D "mediatek,mt8188-mfgcfg"; reg =3D <0 0x13fbf000 0 0x1000>; --=20 2.45.1