From nobody Fri Feb 13 18:36:49 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CCB129A8D; Fri, 24 May 2024 09:05:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541556; cv=none; b=irY5twGXizBdLDYLlhIKl8/zviVYVBZ0Ei39MmSmyIldg3+l+Y9fdrSNKTWwdSlIx5o9yRx2Y7nNHO7RVvZLZaBjJI3E4Id9cs0wTxeOzSgIclOJ8j3bVoFgb3DOwsU27RMdqvFFE71/Y4jb9KOU8OSsoNOlQY4yf9Q7j9H4mwo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541556; c=relaxed/simple; bh=2EMoTno8eRkSxtl30K/XtKaFJYEClw4InngOtpk/x2I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dyNuzI1slDEA+UMhLuB8AzcVrsRZD8pE082HnZ7VDyURVPt1LJ3RGcrvPQQFXbP1SsP2JF28e6pW4GAZajWBKWr9Nw/53g6PZPyeCpGdeNPchuljU/nj1/sIBCuaH7GghUjH43rPUNTTus8jmERqd8WEVS/TSoYGtYdvLY4IOYY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=StT5hHcV; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="StT5hHcV" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44O95Xeg030052; Fri, 24 May 2024 04:05:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716541533; bh=7nPUZ0y+xEHt91JubFYtm2z9d4roGxqvsS9/LTZMSnY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=StT5hHcV4Aa5vzHX5iPNjAbJvh80vZFgv3+cYGChwhQ1jbxW5iBF88u17NrItasuk w+UNCp6IL3DsWBohrFOaAV3ZFsEI7XiQKj8sss759vK/R/UZ13j3l71hfMwXEUQN+e w4sDyI74ZW0OKtAX1Q/qe+YqAj0fZOuCP1yUhClY= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44O95XeN028836 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 May 2024 04:05:33 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:33 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:32 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7I017455; Fri, 24 May 2024 04:05:28 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 3/7] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 Date: Fri, 24 May 2024 14:35:10 +0530 Message-ID: <20240524090514.152727-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Ravi Gunasekaran The GPIO expander on the EVM allows the USB selection for Type-C port to either USB0 or USB1 via USB hub. By default, let the Type-C port select USB0 via the GPIO expander port P05. Enable super-speed on USB1 by updating SerDes0 lane configuration. Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli --- v2: https://lore.kernel.org/r/20240513114443.16350-4-r-gunasekaran@ti.com/ Changes since v2: - Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change made in patch 1. - Dropped Serdes1 idle-states since it has not yet been added in the serdes_ln_ctrl node. - Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h". - Added newline after /* J722S */ in "k3-serdes.h" following the file convention. v1: https://lore.kernel.org/r/20240429120932.11456-4-r-gunasekaran@ti.com/ Changes since v1: - Removed USB aliases, line-name property for p05 GPIO hog. - Included k3-j722s-main.dtsi. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 54 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-serdes.h | 5 +++ 3 files changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index bf3c246d13d1..a3bda39cc223 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -9,7 +9,9 @@ /dts-v1/; =20 #include +#include #include "k3-j722s.dtsi" +#include "k3-serdes.h" =20 / { compatible =3D "ti,j722s-evm", "ti,j722s"; @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TX= C */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; =20 &cpsw3g { @@ -301,6 +309,13 @@ exp1: gpio@23 { "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + + p05-hog { + /* P05 - USB2.0_MUX_SEL */ + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_LOW>; + output-high; + }; }; }; =20 @@ -384,3 +399,42 @@ &sdhci1 { status =3D "okay"; bootph-all; }; + +&serdes_ln_ctrl { + idle-states =3D ; +}; + +&serdes0 { + status =3D "okay"; + serdes0_usb_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + +&usbss0 { + ti,vbus-divider; + status =3D "okay"; +}; + +&usb0 { + dr_mode =3D "otg"; + usb-role-switch; +}; + +&usbss1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_usb1_pins_default>; + ti,vbus-divider; + status =3D "okay"; +}; + +&usb1 { + dr_mode =3D "host"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb_link>; + phy-names =3D "cdns3,usb3-phy"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c75744edb143..61b64fae1bf4 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -87,3 +87,8 @@ &oc_sram { reg =3D <0x00 0x70000000 0x00 0x40000>; ranges =3D <0x00 0x00 0x70000000 0x40000>; }; + +/* Include bus peripherals that are additionally + * present in J722S + */ + #include "k3-j722s-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3= -serdes.h index a011ad893b44..e6a036a4e70b 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,9 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 =20 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */ --=20 2.40.1