From nobody Fri Feb 13 16:38:51 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76A1112A16C; Fri, 24 May 2024 09:05:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541544; cv=none; b=YvfvK/+JWX53FKI1stKG/kuWJ1FAXWqnUGnB7bwKwAK81oASgC6/6w5Q40NlWgNHLXyGtwoVlWTAQ4trZFTiWAtCRncGsZOcUPILmiCI506MFk+aKTucBEQWBtfoDsUiESM8JF6dW1MHY9280IE751aduce9ReiQFg+lx9Muy1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541544; c=relaxed/simple; bh=Q/Uw6WEGSallc3jLEE3Dd1x41ZPtMdh5xBHsTVLNlF8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XBdItUfKlqI+swOMRunRgz5eFXBGjEDdDVm1xMRjk2GObsIK0rU4/GH3a1qDM5Q9NzeRT2k2xmRuNaRxHEFC0Hpd53Cw4GOa5bt9lfaoQ5VBbzc8oZr4GjJqLewr4Xu37c2uSogAQ4TUAGU8bqvOA0h2coSr7nMBxCDySs2bP/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=yKggM8Xt; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="yKggM8Xt" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44O95OUs054192; Fri, 24 May 2024 04:05:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716541524; bh=UTX6g2sDmelnKTRflKA1XZXjDb9sjp/VvCPo+/ywmQY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yKggM8XtpqZigSYQHEf1GjBal/vgrsiGSm9C8+BNmhj4ltg76//fXnj2XXpMYTAQL Vowb0oRdxmPfnXRDLXMeUpq0o38xvApWgo3/aUd6z2HodsOBmgzrE9hISc6QiXKwuI yKB78s1L+YSthHeEF7S0tWNI+RP4NpZTBMEZLMig= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44O95OI6028582 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 May 2024 04:05:24 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:24 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:23 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7G017455; Fri, 24 May 2024 04:05:20 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 1/7] arm64: dts: ti: k3-j722s-main: Add support for SERDES0 Date: Fri, 24 May 2024 14:35:08 +0530 Message-ID: <20240524090514.152727-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Ravi Gunasekaran AM62P's DT source files are reused for J722S inorder to avoid duplication of nodes. But J722S has additional peripherals that are not present in AM62P. Introduce a -main.dtsi to define such additional main domain peripherals and define the SERDES0 node. Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli --- v2: https://lore.kernel.org/r/20240513114443.16350-2-r-gunasekaran@ti.com/ Changes since v2: - Renamed serdes0_ln_ctrl to serdes_ln_ctrl to keep the format consistent across SoCs where a single node is sufficient to represent the Lane-Muxing for all instances of the Serdes. v1: https://lore.kernel.org/r/20240429120932.11456-2-r-gunasekaran@ti.com/ Changes since v1: - Newly introduced k3-j722s-main.dtsi to add main domain peripherals that are additionally present in J722S. - Used generic node names - renamed "clock-cmnrefclk" to "clk-0", "wiz@f000000" to "phy@f000000" arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi new file mode 100644 index 000000000000..0dac8f1e1291 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S main domain peripherals + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +#include + +/ { + serdes_refclk: clk-0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + }; +}; + +&cbass_main { + serdes_wiz0: phy@f000000 { + compatible =3D "ti,am64-wiz-10g"; + ranges =3D <0x0f000000 0x0 0x0f000000 0x00010000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <1>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + + assigned-clocks =3D <&k3_clks 279 1>; + assigned-clock-parents =3D <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x0f000000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; /* Needs lane config */ + }; + }; +}; + +&main_conf { + serdes_ln_ctrl: mux-controller@4080 { + compatible =3D "reg-mux"; + reg =3D <0x4080 0x4>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x3>; /* SERDES0 lane0 select */ + }; +}; --=20 2.40.1 From nobody Fri Feb 13 16:38:51 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBE3B129A7B; Fri, 24 May 2024 09:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541545; cv=none; b=bETuW+u5Kg7PWH7EHOtOe3ihDjZtXDmIFF0gWghC60tN+vm3HOaKHuzn/DnFF1qF6YV55qS14GnsClh3hJFNa4kgASOB/aAa7EYjwBYsUnBDRkpy00UYnd7uZOZJdoKhH2Z/1EZBccbr+j37f6mW/OJbnlYglGpIuKGGNapmbwE= ARC-Message-Signature: i=1; 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Fri, 24 May 2024 04:05:28 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7H017455; Fri, 24 May 2024 04:05:24 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 2/7] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description Date: Fri, 24 May 2024 14:35:09 +0530 Message-ID: <20240524090514.152727-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Ravi Gunasekaran USB1 controller on J722S and AM62P are from different vendors. Redefine the USB1 node description for J722S by deleting the node inherited from AM62P dtsi. Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli --- v2: https://lore.kernel.org/r/20240513114443.16350-3-r-gunasekaran@ti.com/ No changes since v2. v1: https://lore.kernel.org/r/20240429120932.11456-3-r-gunasekaran@ti.com/ Changes since v1: - The entire node which was added in k3-j722s.dtsi in v1 in now moved to k3-j722s-main.dtsi as USB is a main domain peripheral. - Used generic node names - renamed "cdns-usb@f920000" to "usb@f920000". arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 0dac8f1e1291..b069cecebfd9 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -6,6 +6,13 @@ =20 #include =20 +/* + * USB1 controller on AM62P and J722S are of different IP. + * Delete AM62P's USBSS1 node definition and redefine it for J722S. + */ + +/delete-node/ &usbss1; + / { serdes_refclk: clk-0 { compatible =3D "fixed-clock"; @@ -52,6 +59,38 @@ serdes0: serdes@f000000 { status =3D "disabled"; /* Needs lane config */ }; }; + + usbss1: usb@f920000 { + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x0f920000 0x00 0x100>; + power-domains =3D <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 278 3>, <&k3_clks 278 1>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 278 3>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 278 4>; /* HF0SC0 */ + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb1: usb@31200000{ + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x31200000 0x00 0x10000>, + <0x00 0x31210000 0x00 0x10000>, + <0x00 0x31220000 0x00 0x10000>; + reg-names =3D "otg", + "xhci", + "dev"; + interrupts =3D , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names =3D "host", + "peripheral", + "otg"; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + }; + }; }; =20 &main_conf { --=20 2.40.1 From nobody Fri Feb 13 16:38:51 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CCB129A8D; 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Fri, 24 May 2024 04:05:33 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:33 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:32 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7I017455; Fri, 24 May 2024 04:05:28 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 3/7] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 Date: Fri, 24 May 2024 14:35:10 +0530 Message-ID: <20240524090514.152727-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Ravi Gunasekaran The GPIO expander on the EVM allows the USB selection for Type-C port to either USB0 or USB1 via USB hub. By default, let the Type-C port select USB0 via the GPIO expander port P05. Enable super-speed on USB1 by updating SerDes0 lane configuration. Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli --- v2: https://lore.kernel.org/r/20240513114443.16350-4-r-gunasekaran@ti.com/ Changes since v2: - Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change made in patch 1. - Dropped Serdes1 idle-states since it has not yet been added in the serdes_ln_ctrl node. - Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h". - Added newline after /* J722S */ in "k3-serdes.h" following the file convention. v1: https://lore.kernel.org/r/20240429120932.11456-4-r-gunasekaran@ti.com/ Changes since v1: - Removed USB aliases, line-name property for p05 GPIO hog. - Included k3-j722s-main.dtsi. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 54 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-serdes.h | 5 +++ 3 files changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index bf3c246d13d1..a3bda39cc223 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -9,7 +9,9 @@ /dts-v1/; =20 #include +#include #include "k3-j722s.dtsi" +#include "k3-serdes.h" =20 / { compatible =3D "ti,j722s-evm", "ti,j722s"; @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TX= C */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; =20 &cpsw3g { @@ -301,6 +309,13 @@ exp1: gpio@23 { "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + + p05-hog { + /* P05 - USB2.0_MUX_SEL */ + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_LOW>; + output-high; + }; }; }; =20 @@ -384,3 +399,42 @@ &sdhci1 { status =3D "okay"; bootph-all; }; + +&serdes_ln_ctrl { + idle-states =3D ; +}; + +&serdes0 { + status =3D "okay"; + serdes0_usb_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + +&usbss0 { + ti,vbus-divider; + status =3D "okay"; +}; + +&usb0 { + dr_mode =3D "otg"; + usb-role-switch; +}; + +&usbss1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_usb1_pins_default>; + ti,vbus-divider; + status =3D "okay"; +}; + +&usb1 { + dr_mode =3D "host"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb_link>; + phy-names =3D "cdns3,usb3-phy"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c75744edb143..61b64fae1bf4 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -87,3 +87,8 @@ &oc_sram { reg =3D <0x00 0x70000000 0x00 0x40000>; ranges =3D <0x00 0x00 0x70000000 0x40000>; }; + +/* Include bus peripherals that are additionally + * present in J722S + */ + #include "k3-j722s-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3= -serdes.h index a011ad893b44..e6a036a4e70b 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,9 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 =20 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */ --=20 2.40.1 From nobody Fri Feb 13 16:38:51 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F421E86258; 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Fri, 24 May 2024 04:05:37 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:37 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:37 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7J017455; Fri, 24 May 2024 04:05:33 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 4/7] arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S Date: Fri, 24 May 2024 14:35:11 +0530 Message-ID: <20240524090514.152727-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The Serdes1 instance of the Serdes on J722S SoC is a single lane Serdes that is muxed across PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Signed-off-by: Siddharth Vadapalli --- Current patch is v1. No changelog. arch/arm64/boot/dts/ti/k3-serdes.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3= -serdes.h index e6a036a4e70b..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -206,4 +206,7 @@ #define J722S_SERDES0_LANE0_USB 0x0 #define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 =20 +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */ --=20 2.40.1 From nobody Fri Feb 13 16:38:51 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F285542AA0; Fri, 24 May 2024 09:09:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541796; cv=none; b=pG4+MzhXvSgGEeMLoDT6WclkXWPT7QI9sjBJdGlif/8DQO/lodqBKQzV7mcwe5H9u7YRbGkEZPCC0y++EIDvMiIEvrtSiaFFT8uG2o+87E0W4cA0roloH8IQjOioQGY8Q9lzJJRtNl+Wh50BZoU9o1TLcrxBj3DhfhGO7PlJ4FM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541796; c=relaxed/simple; bh=UyJXOFvXCuKXrxVR4X/0AOzG4msi71UdQXvrD03dlk8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dbR+15SzlU53JviyuIY2GZ4+htqoE3efvfaMJXs/pb9HxNFEUCy82Rwu90dWZzejKI+4XU/mgb0Wd7yzUMCyWcCNSOzBhCQT2R55EFpeDdXe1ewOhCgVky+ShuIe3KTKCjd6lu5PYnYmKMG3+wZtkG/pXuWeRq8v9t99ywQwrgQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=CfgpjrhF; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CfgpjrhF" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44O95ge5054220; Fri, 24 May 2024 04:05:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716541542; bh=0vvthN20lN+WXz+n5AK/7aVBNF87CbaFIzew0BHEqkU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CfgpjrhFkA1w4+1D3BK1LOmeumYYLzYqxfnym9dvCxXDHNjPKT9rnQ0xwKHlk9efn ICc5ZzHTcmZ2oR3lcA3Yqf1ZmKHCCQeRiNd0KG3g83jNtWB1rpyQivUSHczpWl941O NuppQPF0dhMWSDTC/5TfcXRM66BGmMiSqraLJtI8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44O95f1l095760 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 May 2024 04:05:41 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:41 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:41 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7K017455; Fri, 24 May 2024 04:05:37 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 5/7] arm64: dts: ti: k3-j722s: Add lane mux for Serdes1 Date: Fri, 24 May 2024 14:35:12 +0530 Message-ID: <20240524090514.152727-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The Serdes1 instance of Serdes on J722S SoC can be muxed between PCIe0 and SGMII1. Update the "serdes_ln_ctrl" node adding support for the lane mux of Serdes1. Additionally, set the default muxing for Serdes1 Lane0 to PCIe0. Signed-off-by: Siddharth Vadapalli --- Current patch is v1. No changelog. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 3 ++- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index a3bda39cc223..16c6ab8ee07e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -401,7 +401,8 @@ &sdhci1 { }; =20 &serdes_ln_ctrl { - idle-states =3D ; + idle-states =3D , + ; }; =20 &serdes0 { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index b069cecebfd9..48b77e476c77 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -96,8 +96,9 @@ usb1: usb@31200000{ &main_conf { serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; - reg =3D <0x4080 0x4>; + reg =3D <0x4080 0x14>; #mux-control-cells =3D <1>; - mux-reg-masks =3D <0x0 0x3>; /* SERDES0 lane0 select */ + mux-reg-masks =3D <0x0 0x3>, /* SERDES0 lane0 select */ + <0x10 0x3>; /* SERDES1 lane0 select */ }; }; --=20 2.40.1 From nobody Fri Feb 13 16:38:51 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 674B0129E86; Fri, 24 May 2024 09:10:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541821; cv=none; b=Ip5bhHX9yqxSzplchAm6KX3Or18s0Eq/56nXhqrxB7VBi0saF9L4cs0az6ZOOksEs9EYnsa5AWqCjtGQ6rNQVTNyE03ol5IO8dMftg5K04VRZTP+Du+VwypnNomQ4v1SFSRNU0TAiR06RKfIvAQlFfD+iy3aU2ddDqA2BtrLKAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716541821; c=relaxed/simple; bh=QgserOuBCjfdDMRxfRBELU3SDqIo+0NouR2Ibum/w/A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EclxxukINXbMte3Vyi/Q++fR4NVI4K0O1xTEMCg93shFpPAKRxrMqcGRe2OhrtwO5B89esl8n1soTHjb+olGSTW1+RtG4C0PfjVKGOPZc8FyZ/qVVDrZM5t+M1OI/p7BmaGfJPl+yG7RSJxdXU9M5k5dfDlR0KjKCMHwBGUejfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ir3HsukY; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ir3HsukY" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44O95kcv030090; Fri, 24 May 2024 04:05:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716541546; bh=GXI/sDOl7VpBlMvsOcRGN+H5CO94FdPVQOL51p0NhD4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ir3HsukYVFIqx+HorK1nwUZIrXUXnWzcKC0+BnhNsJ6Kw6jy3QrUU+IxVb8Mb+1TE hIMf99m+EfpDslUtjFbTc9pYThIBvV8qFVyy4HBxkXCs5PwbGO0rcw8jSZjaC7hBsh SgXPH4i+9ppO4ByCQqijYI0Ubkv1y0zfHbWuoClA= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44O95kxR029731 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 May 2024 04:05:46 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:46 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7L017455; Fri, 24 May 2024 04:05:42 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 6/7] arm64: dts: ti: k3-j722s-main: Add WIZ1 and Serdes1 nodes Date: Fri, 24 May 2024 14:35:13 +0530 Message-ID: <20240524090514.152727-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The Serdes1 instance of Serdes on TI's J722S SoC is a 1 Lane Serdes with the WIZ1 instance of the WIZ wrapper used for configuring the Serdes. Signed-off-by: Siddharth Vadapalli --- Current patch is v1. No changelog. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 48b77e476c77..19a7e8413ad2 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -60,6 +60,42 @@ serdes0: serdes@f000000 { }; }; =20 + serdes_wiz1: phy@f010000 { + compatible =3D "ti,am64-wiz-10g"; + ranges =3D <0x0f010000 0x0 0x0f010000 0x00010000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <1>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + + assigned-clocks =3D <&k3_clks 280 1>; + assigned-clock-parents =3D <&k3_clks 280 5>; + + serdes1: serdes@f010000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x0f010000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz1 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 280 1>, + <&k3_clks 280 1>, + <&k3_clks 280 1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + }; + }; + usbss1: usb@f920000 { compatible =3D "ti,j721e-usb"; reg =3D <0x00 0x0f920000 0x00 0x100>; --=20 2.40.1 From nobody Fri Feb 13 16:38:51 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A487129A8D; Fri, 24 May 2024 09:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 24 May 2024 04:05:50 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:50 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7M017455; Fri, 24 May 2024 04:05:46 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0 Date: Fri, 24 May 2024 14:35:14 +0530 Message-ID: <20240524090514.152727-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com> References: <20240524090514.152727-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The PCIe0 instance of PCIe on TI's J722S SoC is a Gen3 single lane PCIe controller. Add the device-tree nodes for it and enable it in Root Complex mode of operation using Lane 0 of the Serdes1 instance of Serdes. Signed-off-by: Siddharth Vadapalli --- Current patch is v1. No changelog. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 17 +++++++++++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 37 +++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 16c6ab8ee07e..d2d7de5cfe27 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -416,6 +416,16 @@ serdes0_usb_link: phy@0 { }; }; =20 +&serdes1 { + serdes1_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz1 1>; + }; +}; + &usbss0 { ti,vbus-divider; status =3D "okay"; @@ -439,3 +449,10 @@ &usb1 { phys =3D <&serdes0_usb_link>; phy-names =3D "cdns3,usb3-phy"; }; + +&pcie0_rc { + status =3D "okay"; + reset-gpios =3D <&exp1 18 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes1_pcie_link>; + phy-names =3D "pcie-phy"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 19a7e8413ad2..0b32893eb75e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ =20 +#include #include =20 /* @@ -96,6 +97,35 @@ serdes1: serdes@f010000 { }; }; =20 + pcie0_rc: pcie@f102000 { + compatible =3D "ti,j722s-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + ranges =3D <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + max-link-speed =3D <3>; + num-lanes =3D <1>; + power-domains =3D <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names =3D "fck", "pcie_refclk"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb010>; + cdns,no-bar-match-nbits =3D <64>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + status =3D "disabled"; + }; + usbss1: usb@f920000 { compatible =3D "ti,j721e-usb"; reg =3D <0x00 0x0f920000 0x00 0x100>; @@ -138,3 +168,10 @@ serdes_ln_ctrl: mux-controller@4080 { <0x10 0x3>; /* SERDES1 lane0 select */ }; }; + +&wkup_conf { + pcie0_ctrl: pcie0-ctrl@4070 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4070 0x4>; + }; +}; --=20 2.40.1