From nobody Fri Feb 13 18:36:28 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90D3738FA3 for ; Fri, 24 May 2024 07:33:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716536017; cv=none; b=NWuAArTUlCI6QbpE1RSNFhtHkL8hlEdqWv2ryC1PR8YrhfFQJMBHp1CvGgMHyyrebCpZvzVMDp0/bT2DQjpAnkE1QL9CRDXkr1+Xzy8tKipjb1n/rLQ8WOatWb6t9QZExGORxXzVOuFSyde3DG7TL1wXdW3dZwOqqKXxN517AC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716536017; c=relaxed/simple; bh=vAf4OfqTxkekOhU7imfeBrfQM61hNqtAsmvljSXG2/g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sm8J5dQ9HFKj/f4ZZkWC+iauibBG4c/kweptxrYqZHj2sLcUDmQALeYNa5pCY5+n4+VQQreMJV1gWdGK0/B1RRg2SBl6s+WsDwVnARwduF3uPOxvydvajEFUnnebl+f0vZAwqHKCMdnixRQLSYiXXRGVNR65aRRSv3rKFaTIkss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=e1y/Pb5b; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="e1y/Pb5b" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44O7X9HJ023868; Fri, 24 May 2024 02:33:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716535989; bh=YH5PH07tuO/Z/7lFniOpGFT1BozCx5yNjTbNGs3pDHI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=e1y/Pb5be7uy8jXpG1K3Fwau7TxmNL64SMYE7Kk+5mhUtaaZAS18LLr1f9SPytRvs 4EaX9vM37ybYKUIz/DkMIxb8OcquXfI7LASXZB4AqFKHAHHWOnmvznMZN542cSVWe6 p5RWG7LS6Icp2YGyxV3x3raOmYvnNGBB9Kfz53Oo= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44O7X9L3033627 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 May 2024 02:33:09 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 02:33:09 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 02:33:09 -0500 Received: from localhost (jayesh-hp-probook-440-g8-notebook-pc.dhcp.ti.com [172.24.227.102] (may be forged)) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O7X8Uh121725; Fri, 24 May 2024 02:33:09 -0500 From: Jayesh Choudhary To: , , , , , , , CC: , , , , , , Subject: [PATCH v2 2/2] drm/bridge: Add pixel clock check in atomic_check Date: Fri, 24 May 2024 13:03:05 +0530 Message-ID: <20240524073305.107293-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524073305.107293-1-j-choudhary@ti.com> References: <20240524073305.107293-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Check the pixel clock for the mode in atomic_check and ensure that it is within the range supported by the bridge. Signed-off-by: Jayesh Choudhary --- drivers/gpu/drm/bridge/sii902x.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii9= 02x.c index ef7c3ab3386c..a5b7ee1e3bbe 100644 --- a/drivers/gpu/drm/bridge/sii902x.c +++ b/drivers/gpu/drm/bridge/sii902x.c @@ -517,11 +517,16 @@ static int sii902x_bridge_atomic_check(struct drm_bri= dge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + if (crtc_state->mode.clock < SII902X_MIN_PIXEL_CLOCK_KHZ) + return MODE_CLOCK_LOW; + + if (crtc_state->mode.clock > SII902X_MAX_PIXEL_CLOCK_KHZ) + return MODE_CLOCK_HIGH; + /* * There might be flags negotiation supported in future but * set the bus flags in atomic_check statically for now. */ - bridge_state->input_bus_cfg.flags =3D bridge->timings->input_bus_flags; =20 return 0; --=20 2.25.1