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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716541478; l=1161; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=dLqKCSSB83A5CpMYvy5y1AWx1dYh/sN+oOI5PnPOVSY=; b=UqNxuRjXPeTBHKlV/cedr5aBagTA3pLWnK/IbBAMO8LzIZYjxQP/cJw4HIrV2uIKRW8rZ0j0v gMjy5x16ppYCza2SKj8b9pCxHHd+9ZyJAaki0Noua2Oe4BxfAEWcQJu X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= Use thermal zone names that make more sense. Signed-off-by: Julien Panis --- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index bf95309d2525..ddc7302a510a 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -24,7 +24,7 @@ #define MT8186_BIG_CPU1 5 #define MT8186_NNA 6 #define MT8186_ADSP 7 -#define MT8186_MFG 8 +#define MT8186_GPU 8 =20 #define MT8188_MCU_LITTLE_CPU0 0 #define MT8188_MCU_LITTLE_CPU1 1 @@ -34,11 +34,11 @@ #define MT8188_MCU_BIG_CPU1 5 =20 #define MT8188_AP_APU 0 -#define MT8188_AP_GPU1 1 -#define MT8188_AP_GPU2 2 -#define MT8188_AP_SOC1 3 -#define MT8188_AP_SOC2 4 -#define MT8188_AP_SOC3 5 +#define MT8188_AP_GPU0 1 +#define MT8188_AP_GPU1 2 +#define MT8188_AP_ADSP 3 +#define MT8188_AP_VDO 4 +#define MT8188_AP_INFRA 5 #define MT8188_AP_CAM1 6 #define MT8188_AP_CAM2 7 =20 --=20 2.37.3 From nobody Thu Sep 19 19:39:33 2024 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C82EF129E6F for ; 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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716541478; l=1639; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=qOE+NwNH35rMZqPs630S3yw6fUABDjCAXs0E4TU/Lto=; b=rwZi7ol8l4OofuhfkYL6KEqAIXdExwo2d+8HZov5y+dHbOYu64V5flumGoI5gw4dW+mdzQGtM FSxO+nrBjttB8WDBGhUChWjc+R9hv8Vp/Oe7chcgm12gNpeN7Szpxay X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= Use thermal zone names that make more sense. Signed-off-by: Julien Panis --- drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 0bb3a495b56e..89fb92666b81 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1436,7 +1436,7 @@ static const struct lvts_ctrl_data mt8186_lvts_data_c= trl[] =3D { .cal_offsets =3D { 29, 30, 31 } }, { .dt_id =3D MT8186_ADSP, .cal_offsets =3D { 34, 35, 28 } }, - { .dt_id =3D MT8186_MFG, + { .dt_id =3D MT8186_GPU, .cal_offsets =3D { 39, 32, 33 } } }, VALID_SENSOR_MAP(1, 1, 1, 0), @@ -1487,11 +1487,11 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_d= ata_ctrl[] =3D { }, { .lvts_sensor =3D { - { .dt_id =3D MT8188_AP_GPU1, + { .dt_id =3D MT8188_AP_GPU0, .cal_offsets =3D { 43, 44, 45 } }, - { .dt_id =3D MT8188_AP_GPU2, + { .dt_id =3D MT8188_AP_GPU1, .cal_offsets =3D { 46, 47, 48 } }, - { .dt_id =3D MT8188_AP_SOC1, + { .dt_id =3D MT8188_AP_ADSP, .cal_offsets =3D { 49, 50, 51 } }, }, VALID_SENSOR_MAP(1, 1, 1, 0), @@ -1500,9 +1500,9 @@ static const struct lvts_ctrl_data mt8188_lvts_ap_dat= a_ctrl[] =3D { }, { .lvts_sensor =3D { - { .dt_id =3D MT8188_AP_SOC2, + { .dt_id =3D MT8188_AP_VDO, .cal_offsets =3D { 52, 53, 54 } }, - { .dt_id =3D MT8188_AP_SOC3, + { .dt_id =3D MT8188_AP_INFRA, .cal_offsets =3D { 55, 56, 57 } }, }, VALID_SENSOR_MAP(1, 1, 0, 0), --=20 2.37.3 From nobody Thu Sep 19 19:39:33 2024 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AD5812AAC7 for ; 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Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716541478; l=1717; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=ZXPmUPXXFa1JCVfBMk9FrptEjzZlcdWN0z1cSMSnOwA=; b=DnxRTjxW9wcR2LDOBi5XDgQoQhBL6Qg8MGh6B91uPvtLP04Jw+un7gLHna5Fd+Gap9ino5nx7 0fkow0NZ0Q1B2HcwWjk8f3uOiSg6Yj45Xh3lrEEqW62m2BKow3pSlc7 X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Values extracted from vendor source tree. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-8-nico@fluxnic.net [Angelo: Fixed validation and quality issues] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 4763ed5dc86c..caec83f5eece 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1361,6 +1361,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8186-lvts"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>; + nvmem-cells =3D <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names =3D "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells =3D <1>; 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Fri, 24 May 2024 02:04:49 -0700 (PDT) From: Julien Panis Date: Fri, 24 May 2024 11:04:37 +0200 Subject: [PATCH v5 4/6] arm64: dts: mediatek: mt8186: add default thermal zones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240524-mtk-thermal-mt818x-dtsi-v5-4-56f8579820e7@baylibre.com> References: <20240524-mtk-thermal-mt818x-dtsi-v5-0-56f8579820e7@baylibre.com> In-Reply-To: <20240524-mtk-thermal-mt818x-dtsi-v5-0-56f8579820e7@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716541478; l=7777; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=sG5Ze//7RlqRD8XfjGttbCgM09mHkLhEkzGoVC5Po1o=; b=ddNwZyGkYMLsHlw5K9GzjhQ54XMaZybiMes1Coyl8cdtyfFhljpTtyM5BCoNKOSSV0WfIoWT9 PBJ0KjMjVK5A7zZuoqIIomOpVAf651JUJmljzXKEPTQtQXYfuLXdlQT X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Inspired by the vendor kernel but adapted to the upstream thermal driver version. Signed-off-by: Nicolas Pitre Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 297 +++++++++++++++++++++++++++= ++++ 1 file changed, 297 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index caec83f5eece..95fe5a05f0d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "mediatek,mt8186"; @@ -2197,4 +2199,299 @@ larb19: smi@1c10f000 { power-domains =3D <&spm MT8186_POWER_DOMAIN_IPE>; }; }; + + thermal_zones: thermal-zones { + cpu-little0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts MT8186_LITTLE_CPU0>; + + trips { + cpu_little0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little0_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts MT8186_LITTLE_CPU1>; + + trips { + cpu_little1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little1_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts MT8186_LITTLE_CPU2>; + + trips { + cpu_little2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little2_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cam-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_CAM>; + + trips { + cam_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cam_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nna-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_NNA>; + + trips { + nna_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + nna_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + nna_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + adsp-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_ADSP>; + + trips { + adsp_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + adsp_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + adsp_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts MT8186_GPU>; + + trips { + gpu_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + gpu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_alert0>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts MT8186_BIG_CPU0>; + + trips { + cpu_big0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_big0_alert0>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts MT8186_BIG_CPU1>; + + trips { + cpu_big1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big1_crit: trip-crit { + temperature =3D <100000>; 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Fri, 24 May 2024 02:04:51 -0700 (PDT) From: Julien Panis Date: Fri, 24 May 2024 11:04:38 +0200 Subject: [PATCH v5 5/6] arm64: dts: mediatek: mt8188: add lvts definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240524-mtk-thermal-mt818x-dtsi-v5-5-56f8579820e7@baylibre.com> References: <20240524-mtk-thermal-mt818x-dtsi-v5-0-56f8579820e7@baylibre.com> In-Reply-To: <20240524-mtk-thermal-mt818x-dtsi-v5-0-56f8579820e7@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716541478; l=2934; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=UpRqfVTfJj/4HAmfkOjlSQQqb0p0PX5zc+/lgsWNhqY=; b=Gx+63BRCjTxPhtYHJO94l+rLZO/giNvzvSPnRBXAOb4fiO0zkouPa+UhiVToPGnfja1IeLBsv S8PaOVfWQWRAdfrvCg8GMOaIdgVkSFYOVvrvc50uQVKXzwylwaIGpSm X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Various values extracted from the vendor's kernel driver. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-14-nico@fluxnic.net [Angelo: Fixed wrong nvmem-cell-names] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 35 ++++++++++++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index b4315c9214dc..a9f1b9db54a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8188"; @@ -357,6 +358,7 @@ infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8188-infracfg-ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 pericfg: syscon@10003000 { @@ -491,6 +493,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8188-lvts-ap"; + reg =3D <0 0x1100b000 0 0xc00>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells =3D <1>; @@ -604,6 +617,17 @@ mmc1: mmc@11240000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8188-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + i2c0: i2c@11280000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11280000 0 0x1000>, @@ -827,6 +851,17 @@ imp_iic_wrap_en: clock-controller@11ec2000 { #clock-cells =3D <1>; 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Fri, 24 May 2024 02:04:53 -0700 (PDT) From: Julien Panis Date: Fri, 24 May 2024 11:04:39 +0200 Subject: [PATCH v5 6/6] arm64: dts: mediatek: mt8188: add default thermal zones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240524-mtk-thermal-mt818x-dtsi-v5-6-56f8579820e7@baylibre.com> References: <20240524-mtk-thermal-mt818x-dtsi-v5-0-56f8579820e7@baylibre.com> In-Reply-To: <20240524-mtk-thermal-mt818x-dtsi-v5-0-56f8579820e7@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre , "Rafael J. Wysocki" , Zhang Rui , Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716541478; l=11210; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=PlNfQwewW55iPtm2FBXd/o7mTcWM5UJJaAgZGNKmb+Q=; b=ttEY0DWULPMoKBafExGLDh+BDacKW1oxwfvayzgooWH7cebFkT6IhroBs1N4Jn33RPthPFliK SqAZ15JAQ4tDhNIA/7F+SPezL9jxxPQIo7QAEPnVQE3eDOX0UhWDggO X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Inspired by the vendor kernel but adapted to the upstream thermal driver version. Signed-off-by: Nicolas Pitre Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 446 +++++++++++++++++++++++++++= ++++ 1 file changed, 446 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index a9f1b9db54a6..6ab4ccc245b9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -12,6 +12,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "mediatek,mt8188"; @@ -311,6 +313,450 @@ psci { method =3D "smc"; }; =20 + thermal_zones: thermal-zones { + cpu-little0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; + + trips { + cpu_little0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little0_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; + + trips { + cpu_little1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little1_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; + + trips { + cpu_little2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little2_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-little3-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <150>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; + + trips { + cpu_little3_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_little3_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_little3_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_little3_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_BIG_CPU0>; + + trips { + cpu_big0_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big0_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_big0_alert0>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-big1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <100>; + thermal-sensors =3D <&lvts_mcu MT8188_MCU_BIG_CPU1>; + + trips { + cpu_big1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_big1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu_big1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_big1_alert0>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + apu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_APU>; + + trips { + apu_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + apu_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + apu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_GPU0>; + + trips { + gpu_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + gpu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_alert0>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_GPU1>; + + trips { + gpu1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + gpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu1_alert0>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + adsp-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_ADSP>; + + trips { + soc_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + soc_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + soc_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + vdo-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_VDO>; + + trips { + soc1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + soc1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + soc1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + infra-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_INFRA>; + + trips { + soc2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + soc2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + soc2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cam1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_CAM1>; + + trips { + cam1_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam1_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cam1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cam2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8188_AP_CAM2>; + + trips { + cam2_alert0: trip-alert0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam2_alert1: trip-alert1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cam2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + timer: timer { compatible =3D "arm,armv8-timer"; interrupt-parent =3D <&gic>; --=20 2.37.3