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charset="utf-8" From: Milen Mitkov Split the RAW interface (RDI), the CSID receiver (RX) and test pattern generator (testgen), configurations for CSID on Titan 170 Signed-off-by: Milen Mitkov Signed-off-by: Gjorgji Rosikopulos Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # sc8280xp/sm8250/= sdm845/apq8016 Acked-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csid-gen2.c | 252 ++++++++++-------- 1 file changed, 139 insertions(+), 113 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/= media/platform/qcom/camss/camss-csid-gen2.c index eb5dabe2639a..2d8398a91fc2 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -176,150 +176,176 @@ #define TPG_COLOR_BOX_CFG_MODE 0 #define TPG_COLOR_BOX_PATTERN_SEL 2 =20 -static void __csid_configure_stream(struct csid_device *csid, u8 enable, u= 8 vc) +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy, int vc) { - struct csid_testgen_config *tg =3D &csid->testgen; - u32 val; - u32 phy_sel =3D 0; u8 lane_cnt =3D csid->phy.lane_cnt; - /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 ->= RDI1, etc. */ - struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; - const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, - csid->res->formats->nformats, - input_format->code); + int val; =20 if (!lane_cnt) lane_cnt =3D 4; =20 - if (!tg->enabled) - phy_sel =3D csid->phy.csiphy_id; + val =3D (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; + writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); =20 - if (enable) { - /* - * DT_ID is a two bit bitfield that is concatenated with - * the four least significant bits of the five bit VC - * bitfield to generate an internal CID value. - * - * CSID_RDI_CFG0(vc) - * DT_ID : 28:27 - * VC : 26:22 - * DT : 21:16 - * - * CID : VC 3:0 << 2 | DT_ID 1:0 - */ - u8 dt_id =3D vc & 0x03; - - if (tg->enabled) { - /* configure one DT, infinite frames */ - val =3D vc << TPG_VC_CFG0_VC_NUM; - val |=3D INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MOD= E; - val |=3D 0 << TPG_VC_CFG0_NUM_FRAMES; - writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0); - - val =3D 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT; - val |=3D 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT; - writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1); - - writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED); - - val =3D (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT; - val |=3D (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH; - writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0)); - - val =3D format->data_type << TPG_DT_n_CFG_1_DATA_TYPE; - writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0)); - - val =3D (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE; - val |=3D 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD; - val |=3D format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT; - writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0)); - - writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG); - - writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG); - } + val =3D 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; + if (vc > 3) + val |=3D 1 << CSI2_RX_CFG1_VC_MODE; + val |=3D 1 << CSI2_RX_CFG1_MISR_EN; + writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); +} =20 - val =3D 1 << RDI_CFG0_BYTE_CNTR_EN; - val |=3D 1 << RDI_CFG0_FORMAT_MEASURE_EN; - val |=3D 1 << RDI_CFG0_TIMESTAMP_EN; - /* note: for non-RDI path, this should be format->decode_format */ - val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; - val |=3D format->data_type << RDI_CFG0_DATA_TYPE; - val |=3D vc << RDI_CFG0_VIRTUAL_CHANNEL; - val |=3D dt_id << RDI_CFG0_DT_ID; - writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc)); +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val; =20 - /* CSID_TIMESTAMP_STB_POST_IRQ */ - val =3D 2 << RDI_CFG1_TIMESTAMP_STB_SEL; - writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc)); + if (enable) + val =3D HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD; + else + val =3D HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD; + writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi)); +} =20 - val =3D 1; - writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc)); +static void __csid_configure_testgen(struct csid_device *csid, u8 enable, = u8 vc) +{ + struct csid_testgen_config *tg =3D &csid->testgen; + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + u8 lane_cnt =3D csid->phy.lane_cnt; + u32 val; =20 - val =3D 0; - writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc)); + if (!lane_cnt) + lane_cnt =3D 4; =20 - val =3D 1; - writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc)); + /* configure one DT, infinite frames */ + val =3D vc << TPG_VC_CFG0_VC_NUM; + val |=3D INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE; + val |=3D 0 << TPG_VC_CFG0_NUM_FRAMES; + writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0); =20 - val =3D 0; - writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc)); + val =3D 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT; + val |=3D 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT; + writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1); =20 - val =3D 1; - writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc)); + writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED); =20 - val =3D 0; - writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc)); + val =3D (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT; + val |=3D (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH; + writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0)); =20 - val =3D 1; - writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc)); + val =3D format->data_type << TPG_DT_n_CFG_1_DATA_TYPE; + writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0)); =20 - val =3D 0; - writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc)); + val =3D (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE; + val |=3D 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD; + val |=3D format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT; + writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0)); =20 - val =3D 0; - writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc)); + writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG); =20 - val =3D readl_relaxed(csid->base + CSID_RDI_CFG0(vc)); - val |=3D 1 << RDI_CFG0_ENABLE; - writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc)); - } + writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG); =20 - if (tg->enabled) { - val =3D enable << TPG_CTRL_TEST_EN; - val |=3D 1 << TPG_CTRL_FS_PKT_EN; - val |=3D 1 << TPG_CTRL_FE_PKT_EN; - val |=3D (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; - val |=3D 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS; - val |=3D 0xA << TPG_CTRL_NUM_TRAIL_BYTES; - writel_relaxed(val, csid->base + CSID_TPG_CTRL); - } + val =3D enable << TPG_CTRL_TEST_EN; + val |=3D 1 << TPG_CTRL_FS_PKT_EN; + val |=3D 1 << TPG_CTRL_FE_PKT_EN; + val |=3D (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; + val |=3D 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS; + val |=3D 0xA << TPG_CTRL_NUM_TRAIL_BYTES; + writel_relaxed(val, csid->base + CSID_TPG_CTRL); +} =20 - val =3D (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; - val |=3D csid->phy.lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |=3D phy_sel << CSI2_RX_CFG0_PHY_NUM_SEL; - writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 vc) +{ + struct csid_testgen_config *tg =3D &csid->testgen; + u32 val; + u32 phy_sel =3D 0; + /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 ->= RDI1, etc. */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); =20 - val =3D 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; - if (vc > 3) - val |=3D 1 << CSI2_RX_CFG1_VC_MODE; - val |=3D 1 << CSI2_RX_CFG1_MISR_EN; - writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); + if (!tg->enabled) + phy_sel =3D csid->phy.csiphy_id; =20 - if (enable) - val =3D HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD; - else - val =3D HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD; + /* + * DT_ID is a two bit bitfield that is concatenated with + * the four least significant bits of the five bit VC + * bitfield to generate an internal CID value. + * + * CSID_RDI_CFG0(vc) + * DT_ID : 28:27 + * VC : 26:22 + * DT : 21:16 + * + * CID : VC 3:0 << 2 | DT_ID 1:0 + */ + u8 dt_id =3D vc & 0x03; + + val =3D 1 << RDI_CFG0_BYTE_CNTR_EN; + val |=3D 1 << RDI_CFG0_FORMAT_MEASURE_EN; + val |=3D 1 << RDI_CFG0_TIMESTAMP_EN; + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D format->data_type << RDI_CFG0_DATA_TYPE; + val |=3D vc << RDI_CFG0_VIRTUAL_CHANNEL; + val |=3D dt_id << RDI_CFG0_DT_ID; + writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc)); + + /* CSID_TIMESTAMP_STB_POST_IRQ */ + val =3D 2 << RDI_CFG1_TIMESTAMP_STB_SEL; + writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc)); + + val =3D 1; + writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc)); + + val =3D 0; + writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc)); + + val =3D 1; + writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc)); + + val =3D 0; + writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc)); + + val =3D 1; + writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc)); + + val =3D 0; + writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc)); + + val =3D 1; + writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc)); + + val =3D 0; + writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc)); + + val =3D 0; writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc)); + + val =3D readl_relaxed(csid->base + CSID_RDI_CFG0(vc)); + val |=3D enable << RDI_CFG0_ENABLE; + writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc)); } =20 static void csid_configure_stream(struct csid_device *csid, u8 enable) { + struct csid_testgen_config *tg =3D &csid->testgen; u8 i; /* Loop through all enabled VCs and configure stream for each */ for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) - if (csid->phy.en_vc & BIT(i)) - __csid_configure_stream(csid, enable, i); + if (csid->phy.en_vc & BIT(i)) { + if (tg->enabled) + __csid_configure_testgen(csid, enable, i); + + __csid_configure_rdi_stream(csid, enable, i); + __csid_configure_rx(csid, &csid->phy, i); + __csid_ctrl_rdi(csid, enable, i); + } } =20 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 va= l) --=20 2.17.1