From nobody Wed Dec 17 11:32:39 2025 Received: from mail-sh.amlogic.com (unknown [58.32.228.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A3A823AF; Wed, 22 May 2024 08:27:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=58.32.228.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716366469; cv=none; b=Y/rdehBRHVvkFBWoTlMdJ12akvUBupD0gdvkUwgzJ/faOYTRry0uePq8QIHRZLVKb6bI5qgHv/SbDTM43WKFjBFujU12MDKAc6jE7tH2lrqDeZ1uEyKTOJNY7xHM/VULEWtvhr4i+8YixS5D7/Yzr/bUlrcblcMYtFvl653PKIQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716366469; c=relaxed/simple; bh=38V69h8fKUEgAtyEyXdEobiQae+03XcKVkvGo8PX6D8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oRqdzhFJJbeqDW/GDWN7YhbB436lghEeFQAM8vCRZnSicpwx6jeyGkmWHUBI6qiqQSupzpIdEf4BelWtOfCHNAsKVYWSBFGwwBw1oUGrBiamLXUpEYa6I9e/WmnDBt+XmYL62D2oAb4B7z4swHSn8Mp/ExK7QUns7CbwiAb53RA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=58.32.228.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 22 May 2024 16:27:38 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Xianwei Zhao , Chuan Liu Subject: [PATCH v9 4/5] clk: meson: c3: add support for the C3 SoC PLL clock Date: Wed, 22 May 2024 16:27:26 +0800 Message-ID: <20240522082727.3029656-5-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240522082727.3029656-1-xianwei.zhao@amlogic.com> References: <20240522082727.3029656-1-xianwei.zhao@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the C3 PLL clock controller driver for the Amlogic C3 SoC family. Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/c3-pll.c | 746 +++++++++++++++++++++++++++++++++++++ 3 files changed, 760 insertions(+) create mode 100644 drivers/clk/meson/c3-pll.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 29ffd14d267b..31225695b7a3 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -128,6 +128,19 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_C3_PLL + tristate "Amlogic C3 PLL clock controller" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic C302X and C308L devices, + AKA C3. Say Y if you want the board to work, because PLLs are the parent + of most peripherals. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 9ee4b954c896..4420af628b31 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c new file mode 100644 index 000000000000..74e11add165c --- /dev/null +++ b/drivers/clk/meson/c3-pll.c @@ -0,0 +1,746 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic C3 PLL Controller Driver + * + * Copyright (c) 2023 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "meson-clkc-utils.h" +#include + +#define ANACTRL_FIXPLL_CTRL4 0x50 +#define ANACTRL_GP0PLL_CTRL0 0x80 +#define ANACTRL_GP0PLL_CTRL1 0x84 +#define ANACTRL_GP0PLL_CTRL2 0x88 +#define ANACTRL_GP0PLL_CTRL3 0x8c +#define ANACTRL_GP0PLL_CTRL4 0x90 +#define ANACTRL_GP0PLL_CTRL5 0x94 +#define ANACTRL_GP0PLL_CTRL6 0x98 +#define ANACTRL_HIFIPLL_CTRL0 0x100 +#define ANACTRL_HIFIPLL_CTRL1 0x104 +#define ANACTRL_HIFIPLL_CTRL2 0x108 +#define ANACTRL_HIFIPLL_CTRL3 0x10c +#define ANACTRL_HIFIPLL_CTRL4 0x110 +#define ANACTRL_HIFIPLL_CTRL5 0x114 +#define ANACTRL_HIFIPLL_CTRL6 0x118 +#define ANACTRL_MPLL_CTRL0 0x180 +#define ANACTRL_MPLL_CTRL1 0x184 +#define ANACTRL_MPLL_CTRL2 0x188 +#define ANACTRL_MPLL_CTRL3 0x18c +#define ANACTRL_MPLL_CTRL4 0x190 + +static struct clk_regmap fclk_50m_en =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_50m_en", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_50m =3D { + .mult =3D 1, + .div =3D 40, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_50m", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_50m_en.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div2_div =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div2_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div2p5_div =3D { + .mult =3D 2, + .div =3D 5, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2p5_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2p5 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 4, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2p5", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div2p5_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div3_div =3D { + .mult =3D 1, + .div =3D 3, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div3_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div3 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div3", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div3_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div4_div =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div4_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div4 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 21, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div4", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div4_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div5_div =3D { + .mult =3D 1, + .div =3D 5, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div5_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div5 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 22, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div5", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div5_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div7_div =3D { + .mult =3D 1, + .div =3D 7, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div7_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix" + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div7 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 23, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div7", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div7_div.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence c3_gp0_init_regs[] =3D { + { .reg =3D ANACTRL_GP0PLL_CTRL2, .def =3D 0x0 }, + { .reg =3D ANACTRL_GP0PLL_CTRL3, .def =3D 0x48681c00 }, + { .reg =3D ANACTRL_GP0PLL_CTRL4, .def =3D 0x88770290 }, + { .reg =3D ANACTRL_GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D ANACTRL_GP0PLL_CTRL6, .def =3D 0x56540000 }, +}; + +static const struct pll_mult_range c3_gp0_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 9, + }, + .frac =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .n =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &c3_gp0_pll_mult_range, + .init_regs =3D c3_gp0_init_regs, + .init_count =3D ARRAY_SIZE(c3_gp0_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "top", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 32, not 128(2^7) */ +static const struct clk_div_table c3_gp0_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { 5, 32 }, + { /* sentinel */ } +}; + +static struct clk_regmap gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .table =3D c3_gp0_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence c3_hifi_init_regs[] =3D { + { .reg =3D ANACTRL_HIFIPLL_CTRL2, .def =3D 0x0 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D ANACTRL_HIFIPLL_CTRL6, .def =3D 0x56540000 }, +}; + +static struct clk_regmap hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .n =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &c3_gp0_pll_mult_range, + .init_regs =3D c3_hifi_init_regs, + .init_count =3D ARRAY_SIZE(c3_hifi_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "top", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence c3_mclk_init_regs[] =3D { + { .reg =3D ANACTRL_MPLL_CTRL1, .def =3D 0x1420500f }, + { .reg =3D ANACTRL_MPLL_CTRL2, .def =3D 0x00023041 }, + { .reg =3D ANACTRL_MPLL_CTRL3, .def =3D 0x18180000 }, + { .reg =3D ANACTRL_MPLL_CTRL2, .def =3D 0x00023001 } +}; + +static const struct pll_mult_range c3_mclk_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static struct clk_regmap mclk_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &c3_mclk_pll_mult_range, + .init_regs =3D c3_mclk_init_regs, + .init_count =3D ARRAY_SIZE(c3_mclk_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "mclk", + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_div_table c3_mpll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap mclk_pll_od =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL0, + .shift =3D 12, + .width =3D 3, + .table =3D c3_mpll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk_pll_dco.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* both value 0 and 1 gives divide the input rate by one */ +static struct clk_regmap mclk_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .shift =3D 16, + .width =3D 5, + .flags =3D CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk_pll_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data mclk_parent[] =3D { + { .hw =3D &mclk_pll.hw }, + { .fw_name =3D "mclk" }, + { .hw =3D &fclk_50m.hw } +}; + +static struct clk_regmap mclk0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .mask =3D 0x3, + .shift =3D 4, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D mclk_parent, + .num_parents =3D ARRAY_SIZE(mclk_parent), + }, +}; + +static struct clk_regmap mclk0_div_en =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0_div_en", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .shift =3D 2, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk0_div_en.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .mask =3D 0x3, + .shift =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D mclk_parent, + .num_parents =3D ARRAY_SIZE(mclk_parent), + }, +}; + +static struct clk_regmap mclk1_div_en =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1_div_en", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk1_div_en.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *c3_pll_hw_clks[] =3D { + [CLKID_FCLK_50M_EN] =3D &fclk_50m_en.hw, + [CLKID_FCLK_50M] =3D &fclk_50m.hw, + [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, + [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, + [CLKID_FCLK_DIV2P5_DIV] =3D &fclk_div2p5_div.hw, + [CLKID_FCLK_DIV2P5] =3D &fclk_div2p5.hw, + [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, + [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, + [CLKID_FCLK_DIV4_DIV] =3D &fclk_div4_div.hw, + [CLKID_FCLK_DIV4] =3D &fclk_div4.hw, + [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, + [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, + [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, + [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, + [CLKID_GP0_PLL_DCO] =3D &gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &gp0_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &hifi_pll.hw, + [CLKID_MCLK_PLL_DCO] =3D &mclk_pll_dco.hw, + [CLKID_MCLK_PLL_OD] =3D &mclk_pll_od.hw, + [CLKID_MCLK_PLL] =3D &mclk_pll.hw, + [CLKID_MCLK0_SEL] =3D &mclk0_sel.hw, + [CLKID_MCLK0_SEL_EN] =3D &mclk0_div_en.hw, + [CLKID_MCLK0_DIV] =3D &mclk0_div.hw, + [CLKID_MCLK0] =3D &mclk0.hw, + [CLKID_MCLK1_SEL] =3D &mclk1_sel.hw, + [CLKID_MCLK1_SEL_EN] =3D &mclk1_div_en.hw, + [CLKID_MCLK1_DIV] =3D &mclk1_div.hw, + [CLKID_MCLK1] =3D &mclk1.hw +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const c3_pll_clk_regmaps[] =3D { + &fclk_50m_en, + &fclk_div2, + &fclk_div2p5, + &fclk_div3, + &fclk_div4, + &fclk_div5, + &fclk_div7, + &gp0_pll_dco, + &gp0_pll, + &hifi_pll_dco, + &hifi_pll, + &mclk_pll_dco, + &mclk_pll_od, + &mclk_pll, + &mclk0_sel, + &mclk0_div_en, + &mclk0_div, + &mclk0, + &mclk1_sel, + &mclk1_div_en, + &mclk1_div, + &mclk1, +}; + +static struct regmap_config clkc_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D ANACTRL_MPLL_CTRL4, +}; + +static struct meson_clk_hw_data c3_pll_clks =3D { + .hws =3D c3_pll_hw_clks, + .num =3D ARRAY_SIZE(c3_pll_hw_clks), +}; + +static int aml_c3_pll_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int clkid, ret, i; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++) + c3_pll_clk_regmaps[i]->map =3D regmap; + + for (clkid =3D 0; clkid < c3_pll_clks.num; clkid++) { + /* array might be sparse */ + if (!c3_pll_clks.hws[clkid]) + continue; + + ret =3D devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]); + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, + &c3_pll_clks); +} + +static const struct of_device_id c3_pll_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,c3-pll-clkc", + }, + {} +}; +MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table); + +static struct platform_driver c3_pll_driver =3D { + .probe =3D aml_c3_pll_probe, + .driver =3D { + .name =3D "c3-pll-clkc", + .of_match_table =3D c3_pll_clkc_match_table, + }, +}; + +module_platform_driver(c3_pll_driver); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); --=20 2.39.2