From nobody Wed Oct 1 21:02:28 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B842E74C14 for ; Wed, 22 May 2024 05:40:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716356405; cv=none; b=a4CLehQnGHn8Vfu+zoW3ntU3yLW0A85njmonGdktC9YVONkuEPTgjOZRxtf2MZf43EBwCRHChbmsX4bDJ6TRd0S2XK5poJCDFgVqUJx9/B5uPCFELbchKe+0iaLZCwi4vjQxYqfbiOpZMWSVS4XkMWxI7mUnxFQsqfvdWGIWOzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716356405; c=relaxed/simple; bh=qpMDWSd5i1y8+wMUWqd9FfvDaCJzMpbwK0VSUlHiSJ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=stioKhoPaqGlCxvyk7cjLZ8YjrlaP8CUYoCCh/e04AKwfANuix4/3EMxj9t45Es4OKbWaAsWTFE2bMk/ot8SdQUSdGgN2cH03UcY1tUToTjmPpuGqju5u4lqGigjbl+LPuNZLJvTud6ww50tXGwlEpKNRUotcSYdQ8+0OuzbWZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s9ehj-0003db-JI; Wed, 22 May 2024 07:39:59 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1s9ehg-002U0r-OI; Wed, 22 May 2024 07:39:56 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1s9ehg-00Dqu2-28; Wed, 22 May 2024 07:39:56 +0200 From: Sascha Hauer Date: Wed, 22 May 2024 07:39:52 +0200 Subject: [PATCH v4 2/3] mtd: nand: mxc_nand: implement exec_op Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240522-mtd-nand-mxc-nand-exec-op-v4-2-75b611e0ac44@pengutronix.de> References: <20240522-mtd-nand-mxc-nand-exec-op-v4-0-75b611e0ac44@pengutronix.de> In-Reply-To: <20240522-mtd-nand-mxc-nand-exec-op-v4-0-75b611e0ac44@pengutronix.de> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716356396; l=19485; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=qpMDWSd5i1y8+wMUWqd9FfvDaCJzMpbwK0VSUlHiSJ8=; b=yHHRyJGngkxAQF8imVwCpRtAFTT8fcp6KBC79o558OQgOOm8KZNZ8xQytP66TJMQzpJtXGA6A 6aSc3nsw4nKCC339mFr9ZEDKtmDDnfQgG0K/vxl8KE5EAO6J42Wbt6q X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org This converts the driver to the more modern exec_op which gets us rid of a bunch of legacy code. Tested on i.MX27 and i.MX25. Signed-off-by: Sascha Hauer --- drivers/mtd/nand/raw/mxc_nand.c | 468 ++++++++++++++----------------------= ---- 1 file changed, 167 insertions(+), 301 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nan= d.c index 3fe0b471f4a2d..6f8b8f4b118ec 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -126,8 +126,7 @@ struct mxc_nand_host; =20 struct mxc_nand_devtype_data { void (*preset)(struct mtd_info *); - int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc, - int page); + int (*read_page)(struct nand_chip *chip); void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); void (*send_addr)(struct mxc_nand_host *, uint16_t, int); void (*send_page)(struct mtd_info *, unsigned int); @@ -182,8 +181,7 @@ struct mxc_nand_host { =20 struct completion op_completion; =20 - uint8_t *data_buf; - unsigned int buf_start; + void *data_buf; =20 const struct mxc_nand_devtype_data *devtype_data; }; @@ -285,63 +283,6 @@ static void copy_spare(struct mtd_info *mtd, bool bfro= m, void *buf) } } =20 -/* - * MXC NANDFC can only perform full page+spare or spare-only read/write. = When - * the upper layers perform a read/write buf operation, the saved column a= ddress - * is used to index into the full page. So usually this function is called= with - * column =3D=3D 0 (unless no column cycle is needed indicated by column = =3D=3D -1) - */ -static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_a= ddr) -{ - struct nand_chip *nand_chip =3D mtd_to_nand(mtd); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - - /* Write out column address, if necessary */ - if (column !=3D -1) { - host->devtype_data->send_addr(host, column & 0xff, - page_addr =3D=3D -1); - if (mtd->writesize > 512) - /* another col addr cycle for 2k page */ - host->devtype_data->send_addr(host, - (column >> 8) & 0xff, - false); - } - - /* Write out page address, if necessary */ - if (page_addr !=3D -1) { - /* paddr_0 - p_addr_7 */ - host->devtype_data->send_addr(host, (page_addr & 0xff), false); - - if (mtd->writesize > 512) { - if (mtd->size >=3D 0x10000000) { - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, - false); - host->devtype_data->send_addr(host, - (page_addr >> 16) & 0xff, - true); - } else - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, true); - } else { - if (nand_chip->options & NAND_ROW_ADDR_3) { - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, - false); - host->devtype_data->send_addr(host, - (page_addr >> 16) & 0xff, - true); - } else - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, true); - } - } -} - static int check_int_v3(struct mxc_nand_host *host) { uint32_t tmp; @@ -763,18 +704,7 @@ static void mxc_nand_enable_hwecc_v3(struct nand_chip = *chip, bool enable) writel(config2, NFC_V3_CONFIG2); } =20 -/* This functions is used by upper layer to checks if device is ready */ -static int mxc_nand_dev_ready(struct nand_chip *chip) -{ - /* - * NFC handles R/B internally. Therefore, this function - * always returns status as ready. - */ - return 1; -} - -static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *= oob, - bool ecc, int page) +static int mxc_nand_read_page_v1(struct nand_chip *chip) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); @@ -782,15 +712,11 @@ static int mxc_nand_read_page_v1(struct nand_chip *ch= ip, void *buf, void *oob, int i; unsigned int ecc_stats =3D 0; =20 - host->devtype_data->enable_hwecc(chip, ecc); - - host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); - mxc_do_addr_cycle(mtd, 0, page); - - if (mtd->writesize > 512) - host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true); - - no_subpages =3D mtd->writesize >> 9; + if (mtd->writesize) + no_subpages =3D mtd->writesize >> 9; + else + /* READ PARAMETER PAGE is called when mtd->writesize is not yet set */ + no_subpages =3D 1; =20 for (i =3D 0; i < no_subpages; i++) { /* NANDFC buffer 0 is used for page read/write */ @@ -807,181 +733,111 @@ static int mxc_nand_read_page_v1(struct nand_chip *= chip, void *buf, void *oob, =20 host->ecc_stats_v1 =3D ecc_stats; =20 - if (buf) - memcpy32_fromio(buf, host->main_area0, mtd->writesize); - if (oob) - copy_spare(mtd, true, oob); - return 0; } =20 -static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf, - void *oob, bool ecc, int page) +static int mxc_nand_read_page_v2_v3(struct nand_chip *chip) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); =20 - host->devtype_data->enable_hwecc(chip, ecc); - - host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); - mxc_do_addr_cycle(mtd, 0, page); - - if (mtd->writesize > 512) - host->devtype_data->send_cmd(host, - NAND_CMD_READSTART, true); - host->devtype_data->send_page(mtd, NFC_OUTPUT); =20 - if (buf) - memcpy32_fromio(buf, host->main_area0, mtd->writesize); - if (oob) - copy_spare(mtd, true, oob); - return 0; } =20 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { + struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); - void *oob_buf; int ret; =20 - if (oob_required) - oob_buf =3D chip->oob_poi; - else - oob_buf =3D NULL; + host->devtype_data->enable_hwecc(chip, true); + + ret =3D nand_read_page_op(chip, page, 0, buf, mtd->writesize); + + host->devtype_data->enable_hwecc(chip, false); =20 - ret =3D host->devtype_data->read_page(chip, buf, oob_buf, 1, page); if (ret) return ret; =20 + if (oob_required) + copy_spare(mtd, true, chip->oob_poi); + return host->devtype_data->get_ecc_status(chip); } =20 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - void *oob_buf; + struct mtd_info *mtd =3D nand_to_mtd(chip); + int ret; + + ret =3D nand_read_page_op(chip, page, 0, buf, mtd->writesize); + if (ret) + return ret; =20 if (oob_required) - oob_buf =3D chip->oob_poi; - else - oob_buf =3D NULL; + copy_spare(mtd, true, chip->oob_poi); =20 - return host->devtype_data->read_page(chip, buf, oob_buf, 0, page); + return 0; } =20 static int mxc_nand_read_oob(struct nand_chip *chip, int page) -{ - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - - return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0, - page); -} - -static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf, - bool ecc, int page) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); + int ret; =20 - host->devtype_data->enable_hwecc(chip, ecc); - - host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false); - mxc_do_addr_cycle(mtd, 0, page); - - memcpy32_toio(host->main_area0, buf, mtd->writesize); - copy_spare(mtd, false, chip->oob_poi); + ret =3D nand_read_page_op(chip, page, 0, host->data_buf, mtd->writesize); + if (ret) + return ret; =20 - host->devtype_data->send_page(mtd, NFC_INPUT); - host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true); - mxc_do_addr_cycle(mtd, 0, page); + copy_spare(mtd, true, chip->oob_poi); =20 return 0; } =20 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *= buf, int oob_required, int page) -{ - return mxc_nand_write_page(chip, buf, true, page); -} - -static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *= buf, - int oob_required, int page) -{ - return mxc_nand_write_page(chip, buf, false, page); -} - -static int mxc_nand_write_oob(struct nand_chip *chip, int page) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); + int ret; =20 - memset(host->data_buf, 0xff, mtd->writesize); - - return mxc_nand_write_page(chip, host->data_buf, false, page); -} + if (oob_required) + copy_spare(mtd, false, chip->oob_poi); =20 -static u_char mxc_nand_read_byte(struct nand_chip *nand_chip) -{ - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - uint8_t ret; + host->devtype_data->enable_hwecc(chip, true); =20 - /* Check for status request */ - if (host->status_request) - return host->devtype_data->get_dev_status(host) & 0xFF; + ret =3D nand_prog_page_op(chip, page, 0, buf, mtd->writesize); =20 - if (nand_chip->options & NAND_BUSWIDTH_16) { - /* only take the lower byte of each word */ - ret =3D *(uint16_t *)(host->data_buf + host->buf_start); + host->devtype_data->enable_hwecc(chip, false); =20 - host->buf_start +=3D 2; - } else { - ret =3D *(uint8_t *)(host->data_buf + host->buf_start); - host->buf_start++; - } - - dev_dbg(host->dev, "%s: ret=3D0x%hhx (start=3D%u)\n", __func__, ret, host= ->buf_start); return ret; } =20 -/* Write data of length len to buffer buf. The data to be - * written on NAND Flash is first copied to RAMbuffer. After the Data Input - * Operation by the NFC, the data is written to NAND Flash */ -static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *= buf, - int len) +static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *= buf, + int oob_required, int page) { - struct mtd_info *mtd =3D nand_to_mtd(nand_chip); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - u16 col =3D host->buf_start; - int n =3D mtd->oobsize + mtd->writesize - col; - - n =3D min(n, len); + struct mtd_info *mtd =3D nand_to_mtd(chip); =20 - memcpy(host->data_buf + col, buf, n); + if (oob_required) + copy_spare(mtd, false, chip->oob_poi); =20 - host->buf_start +=3D n; + return nand_prog_page_op(chip, page, 0, buf, mtd->writesize); } =20 -/* Read the data buffer from the NAND Flash. To read the data from NAND - * Flash first the data output cycle is initiated by the NFC, which copies - * the data to RAMbuffer. This data of length len is then copied to buffer= buf. - */ -static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf, - int len) +static int mxc_nand_write_oob(struct nand_chip *chip, int page) { - struct mtd_info *mtd =3D nand_to_mtd(nand_chip); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - u16 col =3D host->buf_start; - int n =3D mtd->oobsize + mtd->writesize - col; - - n =3D min(n, len); + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct mxc_nand_host *host =3D nand_get_controller_data(chip); =20 - memcpy(buf, host->data_buf + col, n); + memset(host->data_buf, 0xff, mtd->writesize); + copy_spare(mtd, false, chip->oob_poi); =20 - host->buf_start +=3D n; + return nand_prog_page_op(chip, page, 0, host->data_buf, mtd->writesize); } =20 /* This function is used by upper layer for select and @@ -1360,107 +1216,6 @@ static void preset_v3(struct mtd_info *mtd) writel(0, NFC_V3_DELAY_LINE); } =20 -/* Used by the upper layer to write command to NAND Flash for - * different operations to be carried out on NAND Flash */ -static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command, - int column, int page_addr) -{ - struct mtd_info *mtd =3D nand_to_mtd(nand_chip); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - - dev_dbg(host->dev, "mxc_nand_command (cmd =3D 0x%x, col =3D 0x%x, page = =3D 0x%x)\n", - command, column, page_addr); - - /* Reset command state information */ - host->status_request =3D false; - - /* Command pre-processing step */ - switch (command) { - case NAND_CMD_RESET: - host->devtype_data->preset(mtd); - host->devtype_data->send_cmd(host, command, false); - break; - - case NAND_CMD_STATUS: - host->buf_start =3D 0; - host->status_request =3D true; - - host->devtype_data->send_cmd(host, command, true); - WARN_ONCE(column !=3D -1 || page_addr !=3D -1, - "Unexpected column/row value (cmd=3D%u, col=3D%d, row=3D%d)\n", - command, column, page_addr); - mxc_do_addr_cycle(mtd, column, page_addr); - break; - - case NAND_CMD_READID: - host->devtype_data->send_cmd(host, command, true); - mxc_do_addr_cycle(mtd, column, page_addr); - host->devtype_data->send_read_id(host); - host->buf_start =3D 0; - break; - - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - host->devtype_data->send_cmd(host, command, false); - WARN_ONCE(column !=3D -1, - "Unexpected column value (cmd=3D%u, col=3D%d)\n", - command, column); - mxc_do_addr_cycle(mtd, column, page_addr); - - break; - case NAND_CMD_PARAM: - host->devtype_data->send_cmd(host, command, false); - mxc_do_addr_cycle(mtd, column, page_addr); - host->devtype_data->send_page(mtd, NFC_OUTPUT); - memcpy32_fromio(host->data_buf, host->main_area0, 512); - host->buf_start =3D 0; - break; - default: - WARN_ONCE(1, "Unimplemented command (cmd=3D%u)\n", - command); - break; - } -} - -static int mxc_nand_set_features(struct nand_chip *chip, int addr, - u8 *subfeature_param) -{ - struct mtd_info *mtd =3D nand_to_mtd(chip); - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - int i; - - host->buf_start =3D 0; - - for (i =3D 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) - chip->legacy.write_byte(chip, subfeature_param[i]); - - memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); - host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false); - mxc_do_addr_cycle(mtd, addr, -1); - host->devtype_data->send_page(mtd, NFC_INPUT); - - return 0; -} - -static int mxc_nand_get_features(struct nand_chip *chip, int addr, - u8 *subfeature_param) -{ - struct mtd_info *mtd =3D nand_to_mtd(chip); - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - int i; - - host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false); - mxc_do_addr_cycle(mtd, addr, -1); - host->devtype_data->send_page(mtd, NFC_OUTPUT); - memcpy32_fromio(host->data_buf, host->main_area0, 512); - host->buf_start =3D 0; - - for (i =3D 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) - *subfeature_param++ =3D chip->legacy.read_byte(chip); - - return 0; -} - /* * The generic flash bbt descriptors overlap with our ecc * hardware, so define some i.MX specific ones. @@ -1717,9 +1472,127 @@ static int mxcnd_setup_interface(struct nand_chip *= chip, int chipnr, return host->devtype_data->setup_interface(chip, chipnr, conf); } =20 +static int mxcnd_do_exec_op(struct nand_chip *chip, + const struct nand_subop *op) +{ + struct mxc_nand_host *host =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + int i, j, buf_len; + void *buf_read =3D NULL; + const void *buf_write =3D NULL; + const struct nand_op_instr *instr; + bool readid =3D false; + bool statusreq =3D false; + + for (i =3D 0; i < op->ninstrs; i++) { + instr =3D &op->instrs[i]; + + switch (instr->type) { + case NAND_OP_WAITRDY_INSTR: + /* NFC handles R/B internally, nothing to do here */ + break; + case NAND_OP_CMD_INSTR: + host->devtype_data->send_cmd(host, instr->ctx.cmd.opcode, true); + + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_READID) + readid =3D true; + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_STATUS) + statusreq =3D true; + + break; + case NAND_OP_ADDR_INSTR: + for (j =3D 0; j < instr->ctx.addr.naddrs; j++) { + bool islast =3D j =3D=3D instr->ctx.addr.naddrs - 1; + host->devtype_data->send_addr(host, instr->ctx.addr.addrs[j], islast); + } + break; + case NAND_OP_DATA_OUT_INSTR: + buf_write =3D instr->ctx.data.buf.out; + buf_len =3D instr->ctx.data.len; + + memcpy32_toio(host->main_area0, buf_write, buf_len); + + host->devtype_data->send_page(mtd, NFC_INPUT); + + break; + case NAND_OP_DATA_IN_INSTR: + + buf_read =3D instr->ctx.data.buf.in; + buf_len =3D instr->ctx.data.len; + + if (readid) { + host->devtype_data->send_read_id(host); + readid =3D false; + + memcpy32_fromio(host->data_buf, host->main_area0, buf_len * 2); + + if (chip->options & NAND_BUSWIDTH_16) { + u8 *bufr =3D buf_read; + u16 *bufw =3D host->data_buf; + for (j =3D 0; j < buf_len; j++) + bufr[j] =3D bufw[j]; + } else { + memcpy(buf_read, host->data_buf, buf_len); + } + break; + } + + if (statusreq) { + *(u8*)buf_read =3D host->devtype_data->get_dev_status(host); + statusreq =3D false; + break; + } + + host->devtype_data->read_page(chip); + + if (IS_ALIGNED(buf_len, 4)) { + memcpy32_fromio(buf_read, host->main_area0, buf_len); + } else { + memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize); + memcpy(buf_read, host->data_buf, buf_len); + } + + break; + } + } + + return 0; +} + +#define MAX_DATA_SIZE (4096 + 512) + +static const struct nand_op_parser mxcnd_op_parser =3D NAND_OP_PARSER( + NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7), + NAND_OP_PARSER_PAT_CMD_ELEM(true), + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), + NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, MAX_DATA_SIZE)), + NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7), + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE), + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), + NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7), + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE), + NAND_OP_PARSER_PAT_CMD_ELEM(true), + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), + ); + +static int mxcnd_exec_op(struct nand_chip *chip, + const struct nand_operation *op, bool check_only) +{ + return nand_op_parser_exec_op(chip, &mxcnd_op_parser, + op, check_only); +} + static const struct nand_controller_ops mxcnd_controller_ops =3D { .attach_chip =3D mxcnd_attach_chip, .setup_interface =3D mxcnd_setup_interface, + .exec_op =3D mxcnd_exec_op, }; =20 static int mxcnd_probe(struct platform_device *pdev) @@ -1752,13 +1625,6 @@ static int mxcnd_probe(struct platform_device *pdev) =20 nand_set_controller_data(this, host); nand_set_flash_node(this, pdev->dev.of_node); - this->legacy.dev_ready =3D mxc_nand_dev_ready; - this->legacy.cmdfunc =3D mxc_nand_command; - this->legacy.read_byte =3D mxc_nand_read_byte; - this->legacy.write_buf =3D mxc_nand_write_buf; - this->legacy.read_buf =3D mxc_nand_read_buf; - this->legacy.set_features =3D mxc_nand_set_features; - this->legacy.get_features =3D mxc_nand_get_features; =20 host->clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(host->clk)) --=20 2.39.2