From nobody Wed Feb 11 10:05:03 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19BA4148FFC; Tue, 21 May 2024 17:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716313203; cv=none; b=Dv7BW7Na/I98mnfH5NYpkofBa/cbNi0gRHAUOYxqs6l9l0AWXeW7QkWtc6+vkt5JFdRGh6ODTF5vSYPQVihB0wf33t7KWfy4x9M3oHAV94h8B1oZoqHUeNgD5t6xmuqDyndkSYh/rL7CgSuxp39Xzz3qLPBJnJ3t+x1tdwmVkJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716313203; c=relaxed/simple; bh=JFZfvPynPzZ2TE0Vt2lqzId/TgulfeakQxZrwtr+l44=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=piNm4p8Z0qQuCgv2IxD8lCJ9rJsz9UmCNu2EXe8GzmjzP3k+XmRpuY/AXUPbuKpZri2r9JqFCNXVHcYMrem6OXiTF4iqEhaOk8mkx1X7vNih1Or2LuVMYj4noEy7LGawdsCYhux7uIJ4JUO4YdgVcRAjJ93nL0+GuecxHG17oF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cGzzCN+s; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cGzzCN+s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716313202; x=1747849202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JFZfvPynPzZ2TE0Vt2lqzId/TgulfeakQxZrwtr+l44=; b=cGzzCN+s9t1KzasUMKH7FmmN+NcQ5EGUdFrFRNfEKZZ4cPQzZcwWkHus TqC1J5GcgwfLQEe+mQj2jfCf7BeOTZmbgic2GbRuMfjojPkENgmrkJgIM iMTR8iN8rCF3Ua5hgiLTUEg1H6n8UAuchXteSJT9SngCuGnLz5G1fVVhl GDHk98nvVXMp6OGhMQGlxK4oKbk2eWP3yN4z6fywWsmriwlt34iTZseag KnWe5Jp24vQK9rdlhalUgcpkFYiIaTB3U+WHIRLpyHThc8c5PqCA0GF7g JmvgPtPuhZwxbsQgUEIblijiUB7AYq0/drPBk1wDAqfzcmRZoTxdCbA49 Q==; X-CSE-ConnectionGUID: ZWUs1rgBTE+/Oxlo4pveig== X-CSE-MsgGUID: WpZSK/PQT/O6ij5X6bEYNQ== X-IronPort-AV: E=McAfee;i="6600,9927,11079"; a="12317685" X-IronPort-AV: E=Sophos;i="6.08,178,1712646000"; d="scan'208";a="12317685" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2024 10:39:59 -0700 X-CSE-ConnectionGUID: O5os54H3R8upe/ItjnjJ0w== X-CSE-MsgGUID: RlJ3f5guTn6iFhvmhgGZuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,178,1712646000"; d="scan'208";a="32924977" Received: from fl31ca102ks0602.deacluster.intel.com (HELO gnr-bkc.deacluster.intel.com) ([10.75.133.163]) by fmviesa007.fm.intel.com with ESMTP; 21 May 2024 10:39:59 -0700 From: weilin.wang@intel.com To: weilin.wang@intel.com, Namhyung Kim , Ian Rogers , Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Alexander Shishkin , Jiri Olsa , Adrian Hunter , Kan Liang Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers Subject: [RFC PATCH v9 6/7] perf Document: Add TPEBS to Documents Date: Tue, 21 May 2024 13:39:34 -0400 Message-ID: <20240521173952.3397644-7-weilin.wang@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240521173952.3397644-1-weilin.wang@intel.com> References: <20240521173952.3397644-1-weilin.wang@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Weilin Wang TPEBS is a new feature Intel PMU from Granite Rapids microarchitecture. It = will be used in new TMA releases. Adding related introduction to documents while adding new code to support it in perf stat. Signed-off-by: Weilin Wang --- tools/perf/Documentation/perf-list.txt | 1 + tools/perf/Documentation/topdown.txt | 30 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentat= ion/perf-list.txt index 6bf2468f59d3..dea005410ec0 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -72,6 +72,7 @@ counted. The following modifiers exist: W - group is weak and will fallback to non-group if not schedulable, e - group or event are exclusive and do not share the PMU b - use BPF aggregration (see perf stat --bpf-counters) + R - retire latency value of the event =20 The 'p' modifier can be used for specifying how precise the instruction address should be. The 'p' modifier can be specified multiple times: diff --git a/tools/perf/Documentation/topdown.txt b/tools/perf/Documentatio= n/topdown.txt index ae0aee86844f..98e5503552f5 100644 --- a/tools/perf/Documentation/topdown.txt +++ b/tools/perf/Documentation/topdown.txt @@ -325,6 +325,36 @@ other four level 2 metrics by subtracting correspondin= g metrics as below. Fetch_Bandwidth =3D Frontend_Bound - Fetch_Latency Core_Bound =3D Backend_Bound - Memory_Bound =20 +TPEBS in TopDown +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +TPEBS (Timed PEBS) is one of the new Intel PMU features provided since Gra= nite +Rapids microarchitecture. The TPEBS feature adds a 16 bit retire_latency f= ield +in the Basic Info group of the PEBS record. It records the Core cycles sin= ce the +retirement of the previous instruction to the retirement of current instru= ction. +Please refer to Section 8.4.1 of "Intel=C2=AE Architecture Instruction Set= Extensions +Programming Reference" for more details about this feature. Because this f= eature +extends PEBS record, sampling with weight option is required to get the +retire_latency value. + + perf record -e event_name -W ... + +In the most recent release of TMA, the metrics begin to use event retire_l= atency +values in some of the metrics=E2=80=99 formulas on processors that support= TPEBS feature. +For previous generations that do not support TPEBS, the values are static = and +predefined per processor family by the hardware architects. Due to the div= ersity +of workloads in execution environments, retire_latency values measured at = real +time are more accurate. Therefore, new TMA metrics that use TPEBS will pro= vide +more accurate performance analysis results. + +To support TPEBS in TMA metrics, a new modifier :R on event is added. Perf= would +capture retire_latency value of required events(event with :R in metric fo= rmula) +with perf record. The retire_latency value would be used in metric calcula= tion. +Currently, this feature is supported through perf stat + + perf stat -M metric_name --enable-tpebs-recording ... + + =20 [1] https://software.intel.com/en-us/top-down-microarchitecture-analysis-m= ethod-win [2] https://sites.google.com/site/analysismethods/yasin-pubs --=20 2.43.0