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[90.5.97.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42015deac1asm342085945e9.17.2024.05.21.07.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 07:05:51 -0700 (PDT) From: Julien Panis Date: Tue, 21 May 2024 16:05:37 +0200 Subject: [PATCH v4 3/4] arm64: dts: mediatek: mt8188: add lvts definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240521-mtk-thermal-mt818x-dtsi-v4-3-b91ee678411c@baylibre.com> References: <20240521-mtk-thermal-mt818x-dtsi-v4-0-b91ee678411c@baylibre.com> In-Reply-To: <20240521-mtk-thermal-mt818x-dtsi-v4-0-b91ee678411c@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Lezcano , Nicolas Pitre Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Panis X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716300346; l=2934; i=jpanis@baylibre.com; s=20230526; h=from:subject:message-id; bh=UpRqfVTfJj/4HAmfkOjlSQQqb0p0PX5zc+/lgsWNhqY=; b=QlwxxxZ+8IMEsZ1KOsNLteR7x+69FK/C7WOhQnM3tCwzAiPWf4eqocPeOLgGz5mYgXKfSnXrW ag145bsqnZ7BAnVx5kKVFz5biNQeMyaroUGbCeVtlwoY4LGAtDJ8dfV X-Developer-Key: i=jpanis@baylibre.com; a=ed25519; pk=8eSM4/xkiHWz2M1Cw1U3m2/YfPbsUdEJPCWY3Mh9ekQ= From: Nicolas Pitre Various values extracted from the vendor's kernel driver. Signed-off-by: Nicolas Pitre Link: https://lore.kernel.org/r/20240402032729.2736685-14-nico@fluxnic.net [Angelo: Fixed wrong nvmem-cell-names] Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Julien Panis --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 35 ++++++++++++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index b4315c9214dc..a9f1b9db54a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8188"; @@ -357,6 +358,7 @@ infracfg_ao: syscon@10001000 { compatible =3D "mediatek,mt8188-infracfg-ao", "syscon"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; }; =20 pericfg: syscon@10003000 { @@ -491,6 +493,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8188-lvts-ap"; + reg =3D <0 0x1100b000 0 0xc00>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells =3D <1>; @@ -604,6 +617,17 @@ mmc1: mmc@11240000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8188-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; + nvmem-cells =3D <&lvts_efuse_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + i2c0: i2c@11280000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11280000 0 0x1000>, @@ -827,6 +851,17 @@ imp_iic_wrap_en: clock-controller@11ec2000 { #clock-cells =3D <1>; }; =20 + efuse: efuse@11f20000 { + compatible =3D "mediatek,mt8188-efuse", "mediatek,efuse"; + reg =3D <0 0x11f20000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_efuse_data1: lvts1-calib@1ac { + reg =3D <0x1ac 0x40>; + }; + }; + mfgcfg: clock-controller@13fbf000 { compatible =3D "mediatek,mt8188-mfgcfg"; reg =3D <0 0x13fbf000 0 0x1000>; --=20 2.37.3