From nobody Fri Dec 19 00:34:46 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9031813C66C for ; Mon, 20 May 2024 22:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716245213; cv=none; b=a/uvUxNrR1uIKHW6NhLwNIKJW5VsCexQk9Dtw0d9OltMnswF7pBq+X68n81kqH7ILIGgMR5jbc1kkx2KZafGolKksujw0++yZC1V01aPCcWxFyHUmwbWG9QasTxmn7JmtA5njdQxwcCKCbkom0qH0ApNeP0U9U/Xg/vvaD7EFXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716245213; c=relaxed/simple; bh=CQdIbxPFFGxZJY8rjttoFMJO6IYQfNb94Hv8400ZZHk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gvAEe4y2ZsYFOm1hKGZKt5YwVek2AqolQZ3OZOg8pXRE0vTW/KqrEYhQabloSQwf4LvLrHk5ua7JRqN0PFWzY4xdpaa3wroouaKhHbpCNDV6eBVMcWXmVPn6ybLhenz1jsOLh05i5x0Ilag0iDY4Ai2n3egSdajfKVSTpVfVnIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jF/pHmKR; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jF/pHmKR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716245211; x=1747781211; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CQdIbxPFFGxZJY8rjttoFMJO6IYQfNb94Hv8400ZZHk=; b=jF/pHmKRvgNNE87mcCts8t03HzNcfa8Or84OvT4zX/6iRTzunrqIl2iZ 51xNUzf4IyzV1xw5F1sbvX11zpBFy52/5Ma3mD0IxwVRSqaH6/0+P3YBb cvrdOeAqroU1FDy97+cIFM0hl60H8kYob3Kv75DJuEjN9HNFNkUTVhdf1 a44amDPc4QxjThLlcjKmn5haOG8XB+SGSRL7mzB8J2ifjW3SO51UMbnvy R1DUvRsUcd18vOuyzRSX9rbkq5p8pcG2ZJjJjTWhR9+yGtExdxRm7UcLD H0bn87GLMI4dfPHXXE4uoBYMVOgqjmjASKlvl9IQEkeS3Kkbh9B732Dj0 w==; X-CSE-ConnectionGUID: BIDepFvcSoimYNIbHT2rDQ== X-CSE-MsgGUID: Os2SGVQkQVi06yWXMghp4w== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="12199844" X-IronPort-AV: E=Sophos;i="6.08,176,1712646000"; d="scan'208";a="12199844" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 15:46:39 -0700 X-CSE-ConnectionGUID: XTqqqq27Qwm3AZNn7j3FJQ== X-CSE-MsgGUID: VbRFuBxrQn25GpiKGCSBfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,176,1712646000"; d="scan'208";a="32593476" Received: from agluck-desk3.sc.intel.com ([172.25.222.70]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 15:46:39 -0700 From: Tony Luck To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , "Peter Zijlstra (Intel)" , Uros Bizjak , Rick Edgecombe , Arnd Bergmann , Tony Luck , Mateusz Guzik , Thomas Renninger , Andi Kleen , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: [PATCH v6 31/49] perf/x86/intel: Switch to new Intel CPU model defines Date: Mon, 20 May 2024 15:46:02 -0700 Message-ID: <20240520224620.9480-32-tony.luck@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240520224620.9480-1-tony.luck@intel.com> References: <20240520224620.9480-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck --- arch/x86/events/intel/core.c | 148 +++++++++++++++++------------------ 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 768d1414897f..94206f8cd371 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4698,8 +4698,8 @@ static void intel_pmu_check_extra_regs(struct extra_r= eg *extra_regs); static inline bool intel_pmu_broken_perf_cap(void) { /* The Perf Metric (Bit 15) is always cleared */ - if ((boot_cpu_data.x86_model =3D=3D INTEL_FAM6_METEORLAKE) || - (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_METEORLAKE_L)) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE || + boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE_L) return true; =20 return false; @@ -6245,19 +6245,19 @@ __init int intel_pmu_init(void) /* * Install the hw-cache-events table: */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_CORE_YONAH: + switch (boot_cpu_data.x86_vfm) { + case INTEL_CORE_YONAH: pr_cont("Core events, "); name =3D "core"; break; =20 - case INTEL_FAM6_CORE2_MEROM: + case INTEL_CORE2_MEROM: x86_add_quirk(intel_clovertown_quirk); fallthrough; =20 - case INTEL_FAM6_CORE2_MEROM_L: - case INTEL_FAM6_CORE2_PENRYN: - case INTEL_FAM6_CORE2_DUNNINGTON: + case INTEL_CORE2_MEROM_L: + case INTEL_CORE2_PENRYN: + case INTEL_CORE2_DUNNINGTON: memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, sizeof(hw_cache_event_ids)); =20 @@ -6269,9 +6269,9 @@ __init int intel_pmu_init(void) name =3D "core2"; break; =20 - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_NEHALEM_EP: - case INTEL_FAM6_NEHALEM_EX: + case INTEL_NEHALEM: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, @@ -6303,11 +6303,11 @@ __init int intel_pmu_init(void) name =3D "nehalem"; break; =20 - case INTEL_FAM6_ATOM_BONNELL: - case INTEL_FAM6_ATOM_BONNELL_MID: - case INTEL_FAM6_ATOM_SALTWELL: - case INTEL_FAM6_ATOM_SALTWELL_MID: - case INTEL_FAM6_ATOM_SALTWELL_TABLET: + case INTEL_ATOM_BONNELL: + case INTEL_ATOM_BONNELL_MID: + case INTEL_ATOM_SALTWELL: + case INTEL_ATOM_SALTWELL_MID: + case INTEL_ATOM_SALTWELL_TABLET: memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, sizeof(hw_cache_event_ids)); =20 @@ -6320,11 +6320,11 @@ __init int intel_pmu_init(void) name =3D "bonnell"; break; =20 - case INTEL_FAM6_ATOM_SILVERMONT: - case INTEL_FAM6_ATOM_SILVERMONT_D: - case INTEL_FAM6_ATOM_SILVERMONT_MID: - case INTEL_FAM6_ATOM_AIRMONT: - case INTEL_FAM6_ATOM_AIRMONT_MID: + case INTEL_ATOM_SILVERMONT: + case INTEL_ATOM_SILVERMONT_D: + case INTEL_ATOM_SILVERMONT_MID: + case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_AIRMONT_MID: memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, @@ -6342,8 +6342,8 @@ __init int intel_pmu_init(void) name =3D "silvermont"; break; =20 - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_D: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_D: memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, @@ -6369,7 +6369,7 @@ __init int intel_pmu_init(void) name =3D "goldmont"; break; =20 - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT_PLUS: memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, @@ -6398,9 +6398,9 @@ __init int intel_pmu_init(void) name =3D "goldmont_plus"; break; =20 - case INTEL_FAM6_ATOM_TREMONT_D: - case INTEL_FAM6_ATOM_TREMONT: - case INTEL_FAM6_ATOM_TREMONT_L: + case INTEL_ATOM_TREMONT_D: + case INTEL_ATOM_TREMONT: + case INTEL_ATOM_TREMONT_L: x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); @@ -6427,7 +6427,7 @@ __init int intel_pmu_init(void) name =3D "Tremont"; break; =20 - case INTEL_FAM6_ATOM_GRACEMONT: + case INTEL_ATOM_GRACEMONT: intel_pmu_init_grt(NULL); intel_pmu_pebs_data_source_grt(); x86_pmu.pebs_latency_data =3D adl_latency_data_small; @@ -6439,8 +6439,8 @@ __init int intel_pmu_init(void) name =3D "gracemont"; break; =20 - case INTEL_FAM6_ATOM_CRESTMONT: - case INTEL_FAM6_ATOM_CRESTMONT_X: + case INTEL_ATOM_CRESTMONT: + case INTEL_ATOM_CRESTMONT_X: intel_pmu_init_grt(NULL); x86_pmu.extra_regs =3D intel_cmt_extra_regs; intel_pmu_pebs_data_source_cmt(); @@ -6453,9 +6453,9 @@ __init int intel_pmu_init(void) name =3D "crestmont"; break; =20 - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_WESTMERE_EP: - case INTEL_FAM6_WESTMERE_EX: + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_WESTMERE_EX: memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, @@ -6484,8 +6484,8 @@ __init int intel_pmu_init(void) name =3D "westmere"; break; =20 - case INTEL_FAM6_SANDYBRIDGE: - case INTEL_FAM6_SANDYBRIDGE_X: + case INTEL_SANDYBRIDGE: + case INTEL_SANDYBRIDGE_X: x86_add_quirk(intel_sandybridge_quirk); x86_add_quirk(intel_ht_bug); memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, @@ -6498,7 +6498,7 @@ __init int intel_pmu_init(void) x86_pmu.event_constraints =3D intel_snb_event_constraints; x86_pmu.pebs_constraints =3D intel_snb_pebs_event_constraints; x86_pmu.pebs_aliases =3D intel_pebs_aliases_snb; - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_SANDYBRIDGE_X) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_SANDYBRIDGE_X) x86_pmu.extra_regs =3D intel_snbep_extra_regs; else x86_pmu.extra_regs =3D intel_snb_extra_regs; @@ -6524,8 +6524,8 @@ __init int intel_pmu_init(void) name =3D "sandybridge"; break; =20 - case INTEL_FAM6_IVYBRIDGE: - case INTEL_FAM6_IVYBRIDGE_X: + case INTEL_IVYBRIDGE: + case INTEL_IVYBRIDGE_X: x86_add_quirk(intel_ht_bug); memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); @@ -6541,7 +6541,7 @@ __init int intel_pmu_init(void) x86_pmu.pebs_constraints =3D intel_ivb_pebs_event_constraints; x86_pmu.pebs_aliases =3D intel_pebs_aliases_ivb; x86_pmu.pebs_prec_dist =3D true; - if (boot_cpu_data.x86_model =3D=3D INTEL_FAM6_IVYBRIDGE_X) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_IVYBRIDGE_X) x86_pmu.extra_regs =3D intel_snbep_extra_regs; else x86_pmu.extra_regs =3D intel_snb_extra_regs; @@ -6563,10 +6563,10 @@ __init int intel_pmu_init(void) break; =20 =20 - case INTEL_FAM6_HASWELL: - case INTEL_FAM6_HASWELL_X: - case INTEL_FAM6_HASWELL_L: - case INTEL_FAM6_HASWELL_G: + case INTEL_HASWELL: + case INTEL_HASWELL_X: + case INTEL_HASWELL_L: + case INTEL_HASWELL_G: x86_add_quirk(intel_ht_bug); x86_add_quirk(intel_pebs_isolation_quirk); x86_pmu.late_ack =3D true; @@ -6596,10 +6596,10 @@ __init int intel_pmu_init(void) name =3D "haswell"; break; =20 - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_D: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_BROADWELL_X: + case INTEL_BROADWELL: + case INTEL_BROADWELL_D: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: x86_add_quirk(intel_pebs_isolation_quirk); x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); @@ -6638,8 +6638,8 @@ __init int intel_pmu_init(void) name =3D "broadwell"; break; =20 - case INTEL_FAM6_XEON_PHI_KNL: - case INTEL_FAM6_XEON_PHI_KNM: + case INTEL_XEON_PHI_KNL: + case INTEL_XEON_PHI_KNM: memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, @@ -6658,15 +6658,15 @@ __init int intel_pmu_init(void) name =3D "knights-landing"; break; =20 - case INTEL_FAM6_SKYLAKE_X: + case INTEL_SKYLAKE_X: pmem =3D true; fallthrough; - case INTEL_FAM6_SKYLAKE_L: - case INTEL_FAM6_SKYLAKE: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: - case INTEL_FAM6_COMETLAKE_L: - case INTEL_FAM6_COMETLAKE: + case INTEL_SKYLAKE_L: + case INTEL_SKYLAKE: + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: + case INTEL_COMETLAKE_L: + case INTEL_COMETLAKE: x86_add_quirk(intel_pebs_isolation_quirk); x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); @@ -6715,16 +6715,16 @@ __init int intel_pmu_init(void) name =3D "skylake"; break; =20 - case INTEL_FAM6_ICELAKE_X: - case INTEL_FAM6_ICELAKE_D: + case INTEL_ICELAKE_X: + case INTEL_ICELAKE_D: x86_pmu.pebs_ept =3D 1; pmem =3D true; fallthrough; - case INTEL_FAM6_ICELAKE_L: - case INTEL_FAM6_ICELAKE: - case INTEL_FAM6_TIGERLAKE_L: - case INTEL_FAM6_TIGERLAKE: - case INTEL_FAM6_ROCKETLAKE: + case INTEL_ICELAKE_L: + case INTEL_ICELAKE: + case INTEL_TIGERLAKE_L: + case INTEL_TIGERLAKE: + case INTEL_ROCKETLAKE: x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_ext= ra_regs)); @@ -6759,13 +6759,13 @@ __init int intel_pmu_init(void) name =3D "icelake"; break; =20 - case INTEL_FAM6_SAPPHIRERAPIDS_X: - case INTEL_FAM6_EMERALDRAPIDS_X: + case INTEL_SAPPHIRERAPIDS_X: + case INTEL_EMERALDRAPIDS_X: x86_pmu.flags |=3D PMU_FL_MEM_LOADS_AUX; x86_pmu.extra_regs =3D intel_glc_extra_regs; fallthrough; - case INTEL_FAM6_GRANITERAPIDS_X: - case INTEL_FAM6_GRANITERAPIDS_D: + case INTEL_GRANITERAPIDS_X: + case INTEL_GRANITERAPIDS_D: intel_pmu_init_glc(NULL); if (!x86_pmu.extra_regs) x86_pmu.extra_regs =3D intel_rwc_extra_regs; @@ -6783,11 +6783,11 @@ __init int intel_pmu_init(void) name =3D "sapphire_rapids"; break; =20 - case INTEL_FAM6_ALDERLAKE: - case INTEL_FAM6_ALDERLAKE_L: - case INTEL_FAM6_RAPTORLAKE: - case INTEL_FAM6_RAPTORLAKE_P: - case INTEL_FAM6_RAPTORLAKE_S: + case INTEL_ALDERLAKE: + case INTEL_ALDERLAKE_L: + case INTEL_RAPTORLAKE: + case INTEL_RAPTORLAKE_P: + case INTEL_RAPTORLAKE_S: /* * Alder Lake has 2 types of CPU, core and atom. * @@ -6845,8 +6845,8 @@ __init int intel_pmu_init(void) name =3D "alderlake_hybrid"; break; =20 - case INTEL_FAM6_METEORLAKE: - case INTEL_FAM6_METEORLAKE_L: + case INTEL_METEORLAKE: + case INTEL_METEORLAKE_L: intel_pmu_init_hybrid(hybrid_big_small); =20 x86_pmu.pebs_latency_data =3D mtl_latency_data_small; --=20 2.45.0