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Changes made with respect to original file: - Changed the example to just use interrupt-controller instead of using the whole cpu block - Changed the example compatible string. Signed-off-by: Kanak Shilledar --- .../interrupt-controller/riscv,cpu-intc.txt | 52 ----------------- .../interrupt-controller/riscv,cpu-intc.yaml | 57 +++++++++++++++++++ 2 files changed, 57 insertions(+), 52 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,cpu-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,c= pu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,= cpu-intc.txt deleted file mode 100644 index 265b223cd978..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc= .txt +++ /dev/null @@ -1,52 +0,0 @@ -RISC-V Hart-Level Interrupt Controller (HLIC) ---------------------------------------------- - -RISC-V cores include Control Status Registers (CSRs) which are local to ea= ch -CPU core (HART in RISC-V terminology) and can be read or written by softwa= re. -Some of these CSRs are used to control local interrupts connected to the c= ore. -Every interrupt is ultimately routed through a hart's HLIC before it -interrupts that hart. - -The RISC-V supervisor ISA manual specifies three interrupt sources that are -attached to every HLIC: software interrupts, the timer interrupt, and exte= rnal -interrupts. Software interrupts are used to send IPIs between cores. The -timer interrupt comes from an architecturally mandated real-time timer tha= t is -controlled via Supervisor Binary Interface (SBI) calls and CSR reads. Ext= ernal -interrupts connect all other device interrupts to the HLIC, which are rout= ed -via the platform-level interrupt controller (PLIC). - -All RISC-V systems that conform to the supervisor ISA specification are -required to have a HLIC with these three interrupt sources present. Since= the -interrupt map is defined by the ISA it's not listed in the HLIC's device t= ree -entry, though external interrupt controllers (like the PLIC, for example) = will -need to define how their interrupts map to the relevant HLICs. This means -a PLIC interrupt property will typically list the HLICs for all present HA= RTs -in the system. - -Required properties: -- compatible : "riscv,cpu-intc" -- #interrupt-cells : should be <1>. The interrupt sources are defined by = the - RISC-V supervisor ISA manual, with only the following three interrupts b= eing - defined for supervisor mode: - - Source 1 is the supervisor software interrupt, which can be sent by = an SBI - call and is reserved for use by software. - - Source 5 is the supervisor timer interrupt, which can be configured = by - SBI calls and implements a one-shot timer. - - Source 9 is the supervisor external interrupt, which chains to all o= ther - device interrupts. -- interrupt-controller : Identifies the node as an interrupt controller - -Furthermore, this interrupt-controller MUST be embedded inside the cpu -definition of the hart whose CSRs control these local interrupts. - -An example device tree entry for a HLIC is show below. - - cpu1: cpu@1 { - compatible =3D "riscv"; - ... - cpu1-intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; - interrupt-controller; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,c= pu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv= ,cpu-intc.yaml new file mode 100644 index 000000000000..6fe86d243633 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc= .yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Hart-Level Interrupt Controller (HLIC) + +description: + RISC-V cores include Control Status Registers (CSRs) which are local to + each CPU core (HART in RISC-V terminology) and can be read or written by + software. Some of these CSRs are used to control local interrupts connec= ted + to the core. Every interrupt is ultimately routed through a hart's HLIC + before it interrupts that hart. + + The RISC-V supervisor ISA manual specifies three interrupt sources that = are + attached to every HLIC namely software interrupts, the timer interrupt, = and + external interrupts. Software interrupts are used to send IPIs between + cores. The timer interrupt comes from an architecturally mandated real- + time timer that is controlled via Supervisor Binary Interface (SBI) calls + and CSR reads. External interrupts connect all other device interrupts to + the HLIC, which are routed via the platform-level interrupt controller + (PLIC). + + All RISC-V systems that conform to the supervisor ISA specification are + required to have a HLIC with these three interrupt sources present. Sin= ce + the interrupt map is defined by the ISA it's not listed in the HLIC's de= vice + tree entry, though external interrupt controllers (like the PLIC, for + example) will need to define how their interrupts map to the relevant HL= ICs. + This means a PLIC interrupt property will typically list the HLICs for a= ll + present HARTs in the system. + +maintainers: + - Kanak Shilledar + +properties: + compatible: + const: "riscv,cpu-intc" + + interrupt-controller: true + + '#interrupt-cells': true + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; --=20 2.34.1