From nobody Thu Sep 19 23:06:11 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C1932B2CC; Fri, 17 May 2024 10:30:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715941847; cv=none; b=fXC48ycWQZnDAWIJ/lZncl4XtQS0Bv7X+kKLL0E9CzyvMbKPiojnzYQTYY7QxTvG33nmYNCRsdjRr0lAhH5AJlFo3Oou7r0rEkOM/ytIX56MqWt4SfTIGGjoFnScps+j9hsS78FJPztYhHCwwamN2PgAumxJEmaDnMegbYIYRHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715941847; c=relaxed/simple; bh=yxvSEX+EgS6rHqeued2msTCnz+sHWpWRTGVILa0Nidg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n6NSUfO9mUWdAWif4USG2UXFwn4vPQF6FuTafMskpOSaY3cWlSZRaf5N/wVOugpyNLPDhnOWgSwLzi//6V/2XGMzH0da7X8cmHQZQ74SVbY9AJ7Xl1iujqYxWoqYEEsd7kyl0XwotJp7T1eSa46o38rOQA9uikEVHClZXa/juVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SF2xGnzm; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SF2xGnzm" X-UUID: 828b5442143811efb92737409a0e9459-20240517 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zotP/X0kJr5B6g+bKMaXNDskzCSlvgU0qbm1yBlS+94=; b=SF2xGnzm6UZjk4Yyt95CdUFt8lxdjilELwPFzyzZef6sdnkR+KRQpIuzPhLo74EmvatTOe2quZOk0nWl3zUM7eZvYnjc7ZEUjM3Gme7P04zYbjyXt4AC6RclqX3gwC5aBSoXhxce2q7miFEjlHQv+5qkXHT/XatVxJBRK1rmiKI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.38,REQID:b6711781-5de6-47bf-bce5-f18d4832dd8b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:82c5f88,CLOUDID:c51b38fc-ed05-4274-9204-014369d201e8,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 828b5442143811efb92737409a0e9459-20240517 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 453454458; Fri, 17 May 2024 18:30:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 17 May 2024 18:30:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 17 May 2024 18:30:39 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next v2 4/5] net: phy: mediatek: Extend 1G TX/RX link pulse time Date: Fri, 17 May 2024 18:29:07 +0800 Message-ID: <20240517102908.12079-5-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240517102908.12079-1-SkyLake.Huang@mediatek.com> References: <20240517102908.12079-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "SkyLake.Huang" We observe that some 10G devices' (mostly Marvell's chips inside) 1G training time violates specification, which may last 2230ms and affect later TX/RX link pulse time. This will invalidate MediaTek series gigabit Ethernet PHYs' hardware auto downshift mechanism. Without this patch, if someone is trying to use "4-wire" cable to connect above devices, MediaTek' gigabit Ethernet PHYs may fail to downshift to 100Mbps. (If partner 10G devices' downshift mechanism stops at 1G) This patch extends our 1G TX/RX link pulse time so that we can still link up with those 10G devices. Tested device: - Netgear GS110EMX's 10G port (Marvell 88X3340P) - QNAP QSW-M408-4C Signed-off-by: SkyLake.Huang --- drivers/net/phy/mediatek/mtk-ge-soc.c | 2 + drivers/net/phy/mediatek/mtk-ge.c | 1 + drivers/net/phy/mediatek/mtk-phy-lib.c | 90 ++++++++++++++++++++++++++ drivers/net/phy/mediatek/mtk.h | 16 +++++ 4 files changed, 109 insertions(+) diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediat= ek/mtk-ge-soc.c index 8f23137..62424d4 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -1339,6 +1339,7 @@ static struct phy_driver mtk_socphy_driver[] =3D { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), .name =3D "MediaTek MT7981 PHY", .config_init =3D mt798x_phy_config_init, + .read_status =3D mtk_gphy_cl22_read_status, .config_intr =3D genphy_no_config_intr, .handle_interrupt =3D genphy_handle_interrupt_no_ack, .probe =3D mt7981_phy_probe, @@ -1356,6 +1357,7 @@ static struct phy_driver mtk_socphy_driver[] =3D { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), .name =3D "MediaTek MT7988 PHY", .config_init =3D mt798x_phy_config_init, + .read_status =3D mtk_gphy_cl22_read_status, .config_intr =3D genphy_no_config_intr, .handle_interrupt =3D genphy_handle_interrupt_no_ack, .probe =3D mt7988_phy_probe, diff --git a/drivers/net/phy/mediatek/mtk-ge.c b/drivers/net/phy/mediatek/m= tk-ge.c index 5c0226d..c832c90 100644 --- a/drivers/net/phy/mediatek/mtk-ge.c +++ b/drivers/net/phy/mediatek/mtk-ge.c @@ -211,6 +211,7 @@ static struct phy_driver mtk_gephy_driver[] =3D { .name =3D "MediaTek MT7531 PHY", .probe =3D mt7531_phy_probe, .config_init =3D mt7531_phy_config_init, + .read_status =3D mtk_gphy_cl22_read_status, /* Interrupts are handled by the switch, not the PHY * itself. */ diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/media= tek/mtk-phy-lib.c index 39bfefe..9e302c5 100644 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c @@ -106,6 +106,96 @@ int mtk_phy_write_page(struct phy_device *phydev, int = page) } EXPORT_SYMBOL_GPL(mtk_phy_write_page); =20 +static void extend_an_new_lp_cnt_limit(struct phy_device *phydev) +{ + int mmd_read_ret; + int ret; + u32 reg_val; + + ret =3D read_poll_timeout(mmd_read_ret =3D phy_read_mmd, reg_val, + (mmd_read_ret < 0) || reg_val & MTK_PHY_FINAL_SPEED_1000, + 10000, 1000000, false, phydev, + MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); + if (mmd_read_ret < 0) + ret =3D mmd_read_ret; + /* If final_speed_1000 is raised, try to extend timeout period + * of auto downshift. + */ + if (!ret) { + tr_modify(phydev, 0x0, 0xf, 0x3c, AN_NEW_LP_CNT_LIMIT_MASK, + FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, 0xf)); + mdelay(1500); + + ret =3D read_poll_timeout(mmd_read_ret =3D tr_read, reg_val, + (mmd_read_ret < 0) || + (reg_val & AN_STATE_MASK) !=3D + (AN_STATE_TX_DISABLE << AN_STATE_SHIFT), + 10000, 1000000, false, phydev, + 0x0, 0xf, 0x2); + + if (mmd_read_ret < 0) + ret =3D mmd_read_ret; + + if (!ret) { + mdelay(625); + tr_modify(phydev, 0x0, 0xf, 0x3c, AN_NEW_LP_CNT_LIMIT_MASK, + FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, 0x8)); + mdelay(500); + tr_modify(phydev, 0x0, 0xf, 0x3c, AN_NEW_LP_CNT_LIMIT_MASK, + FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, 0xf)); + } + } +} + +int mtk_gphy_cl22_read_status(struct phy_device *phydev) +{ + int err, old_link =3D phydev->link; + int mii_ctrl; + + /* Update the link, but return if there was an error */ + err =3D genphy_update_link(phydev); + if (err) + return err; + + /* why bother the PHY if nothing can have changed */ + if (phydev->autoneg =3D=3D AUTONEG_ENABLE && old_link && phydev->link) + return 0; + + phydev->master_slave_get =3D MASTER_SLAVE_CFG_UNSUPPORTED; + phydev->master_slave_state =3D MASTER_SLAVE_STATE_UNSUPPORTED; + phydev->speed =3D SPEED_UNKNOWN; + phydev->duplex =3D DUPLEX_UNKNOWN; + phydev->pause =3D 0; + phydev->asym_pause =3D 0; + + if (phydev->is_gigabit_capable) { + err =3D genphy_read_master_slave(phydev); + if (err < 0) + return err; + } + + err =3D genphy_read_lpa(phydev); + if (err < 0) + return err; + + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) { + if (phydev->autoneg_complete) { + phy_resolve_aneg_linkmode(phydev); + } else { + mii_ctrl =3D phy_read(phydev, MII_CTRL1000); + if ((mii_ctrl & ADVERTISE_1000FULL) || (mii_ctrl & ADVERTISE_1000HALF)) + extend_an_new_lp_cnt_limit(phydev); + } + } else if (phydev->autoneg =3D=3D AUTONEG_DISABLE) { + err =3D genphy_read_status_fixed(phydev); + if (err < 0) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(mtk_gphy_cl22_read_status); + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, unsig= ned long rules, unsigned long supported_triggers) { diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h index 10ee9be..32fa3f1 100644 --- a/drivers/net/phy/mediatek/mtk.h +++ b/drivers/net/phy/mediatek/mtk.h @@ -12,6 +12,20 @@ #define MTK_PHY_PAGE_STANDARD 0x0000 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 =20 +/* Registers on Token Ring debug nodes */ +/* ch_addr =3D 0x0, node_addr =3D 0xf, data_addr =3D 0x2 */ +#define AN_STATE_MASK GENMASK(22, 19) +#define AN_STATE_SHIFT 19 +#define AN_STATE_TX_DISABLE 1 + +/* ch_addr =3D 0x0, node_addr =3D 0xf, data_addr =3D 0x3c */ +#define AN_NEW_LP_CNT_LIMIT_MASK GENMASK(23, 20) +#define AUTO_NP_10XEN BIT(6) + +/* Registers on MDIO_MMD_VEND1 */ +#define MTK_PHY_LINK_STATUS_MISC (0xa2) +#define MTK_PHY_FINAL_SPEED_1000 BIT(3) + /* Registers on MDIO_MMD_VEND2 */ #define MTK_PHY_LED0_ON_CTRL 0x24 #define MTK_PHY_LED1_ON_CTRL 0x26 @@ -75,6 +89,8 @@ void __tr_clr_bits(struct phy_device *phydev, u8 ch_addr,= u8 node_addr, u8 data_ int mtk_phy_read_page(struct phy_device *phydev); int mtk_phy_write_page(struct phy_device *phydev, int page); =20 +int mtk_gphy_cl22_read_status(struct phy_device *phydev); + int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, unsig= ned long rules, unsigned long supported_triggers); int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, unsigned = long rules, --=20 2.18.0