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([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:47:54 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu , Conor Dooley Subject: [PATCH v3 1/9] dt-bindings: iio: imu: Add ADIS16501 compatibles Date: Fri, 17 May 2024 10:47:42 +0300 Message-Id: <20240517074750.87376-2-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ADIS16501 compatible. Similarly to other ADIS1650X devices, ADIS16501 supports sync-mode values [0,2]. There are two differences between ADIS16501 and ADIS16477-2: - ADIS16501 does not support pulse sync mode - the delta velocity scale value is different Acked-by: Conor Dooley Signed-off-by: Ramona Gradinariu --- no changes in v3 Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b= /Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml index 9b7ad609f7db..db52e7063116 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -30,6 +30,7 @@ properties: - adi,adis16467-2 - adi,adis16467-3 - adi,adis16500 + - adi,adis16501 - adi,adis16505-1 - adi,adis16505-2 - adi,adis16505-3 @@ -90,6 +91,7 @@ allOf: contains: enum: - adi,adis16500 + - adi,adis16501 - adi,adis16505-1 - adi,adis16505-2 - adi,adis16505-3 -- 2.34.1 From nobody Sat Feb 14 02:50:33 2026 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 171371863C; Fri, 17 May 2024 07:47:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715932080; cv=none; b=P1uLjp6tPX+E2quxWjGHKMVLLlr2/OJtr4dqva4CA07zqrcvnxkNrFYhrc6KRUUypgyMpRx5pDlXA8QJz21+TD2W4aAgiCA33wj0Hg7tThkfECfqFj9GzXTWhJtvNLWEmu9zxFkAICgeGwdydudDTIsuBnQKO+p8EUKK4pGTDMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715932080; c=relaxed/simple; bh=/M+Q0BFUN+2FXUs+wAl0V3zqWuPRNngtMnjq4+cPLfM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=m4GexNAk0gKp2rwk1cc3kopntrmO/YtwzJ1lp4Yfh20nLpI+vKxTUdxso1Xz6eSf7Ne2NZaIyore5GBZNpCdqedKRHlbExyH5T4dAV/f347OcMlb4t+GiHgyInk0sUJ0SwZix6X3hyFxOpB4s7RmMraOgohFqfFLUtc/7D8nXGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZrpSkpZP; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZrpSkpZP" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5238b7d0494so382821e87.3; Fri, 17 May 2024 00:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715932076; x=1716536876; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WWPqUXYjeLP9jBiu1bfABjffqq89QjIiuHCswnkbHKA=; b=ZrpSkpZP71JiMCd56s2pN6gXbflIGJ62d4WmuLkjkA5t71jyM1ava8axvDnfInboy6 lmFDFXdmHnTV9kGosi63dm8DE4OUQQjqgXuFP21Zi0lCZIl5uqeir9h3cHnNi5BjSH+G vcN3a/Gr51/fYS7d/lQ99l8PdQNFAWudeqmQZNo9xe8Y+b4GKitsusf3MMjujv2v26Fr cOoXYe9H5AwtegiiZ4FzBvrgJB3idVxp/t2ZgRzqZZavUctBdVD4lEjdPm6vd8iun01o o8+B0GPcsefB2f+gUmpGGUOFHPQJoJ8F3HCtLKcTwMNWeMK7gInmxiwrT5pFS63CW2gq hv9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715932076; x=1716536876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WWPqUXYjeLP9jBiu1bfABjffqq89QjIiuHCswnkbHKA=; b=TN/GKbvtW/5Wla0Dn8mxOQZ48+wdSPENkj45SAeiwoVqUbQntL0ALosdsPpQXdLK2M Y/kJrlDlpcZt1X7dq0vdQU9zvpk3fVY0Fo5JixpVtgRprQYlza6LbavGGGbYuqCDjdVo LWxfXa0TjeE+T0zPfr8hfNLR7ejD4hob+qB11bv/zWBb8eUq8P8RPP+kEOcIRqg/vTJj 0lhhDNdXf/A/Lb0JTBf/KstGvOsuS0iPsc8du4ebLgbN9EpW7ooYZ11p3pgVZ6iuSBBC aM91MUVd2FzZWOfm4uR1GvOoefYa1XbU1Uh9yD+vPMwEbQF60aIu1bVmURBmJyKRokl4 pWTA== X-Forwarded-Encrypted: i=1; AJvYcCVqj+5ZF1Ht+RszezSkV2FWRjWBqAgIAGqkf1QRI63jLuetNUPuSnsppA1bVfrnzA+mwCqtZ8vZ0vxWxDsRFK1pqYo3IjZqZ/uwf6Kldj65bmS/oB3Eg5/E1dsav2RV50qVkgi2QQ== X-Gm-Message-State: AOJu0Yyd+qDm4Qywd8p0hAjDzuOObb5/iJT4NKbEqQCYFz0316usXyP3 G1SILztb0kEdNX11EL6tYBxKNJYDBERO543RZsSM8GHNu/oCDS9jvHrbfo8HDSg= X-Google-Smtp-Source: AGHT+IH06tewptO4rXbvHsMuftBTokZQyzHaJH3+3A6SCfMfSdB2RIbnU7q5LGdr/4FPxlkQQJmDXQ== X-Received: by 2002:ac2:4bd0:0:b0:523:8d7f:5199 with SMTP id 2adb3069b0e04-5238d7f5495mr9962071e87.41.1715932076222; Fri, 17 May 2024 00:47:56 -0700 (PDT) Received: from rbolboac.. ([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:47:55 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 2/9] drivers: iio: imu: Add support for ADIS16501 Date: Fri, 17 May 2024 10:47:43 +0300 Message-Id: <20240517074750.87376-3-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for ADIS16501 device in already existing ADIS16475 driver. Signed-off-by: Ramona Gradinariu --- no changes in v3 drivers/iio/imu/Kconfig | 4 ++-- drivers/iio/imu/adis16475.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig index 52a155ff3250..782fb80e44c2 100644 --- a/drivers/iio/imu/Kconfig +++ b/drivers/iio/imu/Kconfig @@ -36,8 +36,8 @@ config ADIS16475 select IIO_ADIS_LIB_BUFFER if IIO_BUFFER help Say yes here to build support for Analog Devices ADIS16470, ADIS16475, - ADIS16477, ADIS16465, ADIS16467, ADIS16500, ADIS16505, ADIS16507 inerti= al - sensors. + ADIS16477, ADIS16465, ADIS16467, ADIS16500, ADIS16501, ADIS16505, + ADIS16507 inertial sensors. To compile this driver as a module, choose M here: the module will be called adis16475. diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 01f55cc902fa..53872b716f4a 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -661,6 +661,7 @@ enum adis16475_variant { ADIS16467_2, ADIS16467_3, ADIS16500, + ADIS16501, ADIS16505_1, ADIS16505_2, ADIS16505_3, @@ -980,6 +981,25 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16500, &adis1650x_timeouts), }, + [ADIS16501] =3D { + .name =3D "adis16501", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val =3D 1, + .accel_max_scale =3D IIO_M_S_2_TO_G(800 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(720), + .deltvel_max_val =3D 125, + .int_clk =3D 2000, + .max_dec =3D 1999, + .sync =3D adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, + .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, + .adis_data =3D ADIS16475_DATA(16501, &adis1650x_timeouts), + }, [ADIS16505_1] =3D { .name =3D "adis16505-1", .num_channels =3D ARRAY_SIZE(adis16477_channels), @@ -1482,6 +1502,8 @@ static const struct of_device_id adis16475_of_match[]= =3D { .data =3D &adis16475_chip_info[ADIS16467_3] }, { .compatible =3D "adi,adis16500", .data =3D &adis16475_chip_info[ADIS16500] }, + { .compatible =3D "adi,adis16501", + .data =3D &adis16475_chip_info[ADIS16501] }, { .compatible =3D "adi,adis16505-1", .data =3D &adis16475_chip_info[ADIS16505_1] }, { .compatible =3D "adi,adis16505-2", @@ -1513,6 +1535,7 @@ static const struct spi_device_id adis16475_ids[] =3D= { { "adis16467-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_2] }, { "adis16467-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_3] }, { "adis16500", (kernel_ulong_t)&adis16475_chip_info[ADIS16500] }, + { "adis16501", (kernel_ulong_t)&adis16475_chip_info[ADIS16501] }, { "adis16505-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_1] }, { "adis16505-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_2] }, { "adis16505-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_3] }, -- 2.34.1 From nobody Sat Feb 14 02:50:33 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 058AB200DD; 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([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:47:56 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 3/9] iio: imu: adis16475: Re-define ADIS16475_DATA Date: Fri, 17 May 2024 10:47:44 +0300 Message-Id: <20240517074750.87376-4-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Re-define ADIS16475_DATA such that it takes _burst_max_len and _burst_max_speed_hz as parameters. Signed-off-by: Ramona Gradinariu --- no changes in v3 drivers/iio/imu/adis16475.c | 136 +++++++++++++++++++++++------------- 1 file changed, 89 insertions(+), 47 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 53872b716f4a..f9455ecb348c 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -690,32 +690,32 @@ static const char * const adis16475_status_error_msgs= [] =3D { [ADIS16475_DIAG_STAT_CLK] =3D "Clock error", }; -#define ADIS16475_DATA(_prod_id, _timeouts) \ -{ \ - .msc_ctrl_reg =3D ADIS16475_REG_MSG_CTRL, \ - .glob_cmd_reg =3D ADIS16475_REG_GLOB_CMD, \ - .diag_stat_reg =3D ADIS16475_REG_DIAG_STAT, \ - .prod_id_reg =3D ADIS16475_REG_PROD_ID, \ - .prod_id =3D (_prod_id), \ - .self_test_mask =3D BIT(2), \ - .self_test_reg =3D ADIS16475_REG_GLOB_CMD, \ - .cs_change_delay =3D 16, \ - .read_delay =3D 5, \ - .write_delay =3D 5, \ - .status_error_msgs =3D adis16475_status_error_msgs, \ - .status_error_mask =3D BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ - BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ - BIT(ADIS16475_DIAG_STAT_SPI) | \ - BIT(ADIS16475_DIAG_STAT_STANDBY) | \ - BIT(ADIS16475_DIAG_STAT_SENSOR) | \ - BIT(ADIS16475_DIAG_STAT_MEMORY) | \ - BIT(ADIS16475_DIAG_STAT_CLK), \ - .unmasked_drdy =3D true, \ - .timeouts =3D (_timeouts), \ - .burst_reg_cmd =3D ADIS16475_REG_GLOB_CMD, \ - .burst_len =3D ADIS16475_BURST_MAX_DATA, \ - .burst_max_len =3D ADIS16475_BURST32_MAX_DATA, \ - .burst_max_speed_hz =3D ADIS16475_BURST_MAX_SPEED \ +#define ADIS16475_DATA(_prod_id, _timeouts, _burst_max_len, _burst_max_spe= ed_hz) \ +{ \ + .msc_ctrl_reg =3D ADIS16475_REG_MSG_CTRL, \ + .glob_cmd_reg =3D ADIS16475_REG_GLOB_CMD, \ + .diag_stat_reg =3D ADIS16475_REG_DIAG_STAT, \ + .prod_id_reg =3D ADIS16475_REG_PROD_ID, \ + .prod_id =3D (_prod_id), \ + .self_test_mask =3D BIT(2), \ + .self_test_reg =3D ADIS16475_REG_GLOB_CMD, \ + .cs_change_delay =3D 16, \ + .read_delay =3D 5, \ + .write_delay =3D 5, \ + .status_error_msgs =3D adis16475_status_error_msgs, \ + .status_error_mask =3D BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ + BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ + BIT(ADIS16475_DIAG_STAT_SPI) | \ + BIT(ADIS16475_DIAG_STAT_STANDBY) | \ + BIT(ADIS16475_DIAG_STAT_SENSOR) | \ + BIT(ADIS16475_DIAG_STAT_MEMORY) | \ + BIT(ADIS16475_DIAG_STAT_CLK), \ + .unmasked_drdy =3D true, \ + .timeouts =3D (_timeouts), \ + .burst_reg_cmd =3D ADIS16475_REG_GLOB_CMD, \ + .burst_len =3D ADIS16475_BURST_MAX_DATA, \ + .burst_max_len =3D _burst_max_len, \ + .burst_max_speed_hz =3D _burst_max_speed_hz \ } static const struct adis16475_sync adis16475_sync_mode[] =3D { @@ -753,7 +753,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16470, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16470, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_1] =3D { .name =3D "adis16475-1", @@ -770,7 +772,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_2] =3D { .name =3D "adis16475-2", @@ -787,7 +791,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_3] =3D { .name =3D "adis16475-3", @@ -804,7 +810,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_1] =3D { .name =3D "adis16477-1", @@ -822,7 +830,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_2] =3D { .name =3D "adis16477-2", @@ -840,7 +850,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_3] =3D { .name =3D "adis16477-3", @@ -858,7 +870,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_1] =3D { .name =3D "adis16465-1", @@ -875,7 +889,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_2] =3D { .name =3D "adis16465-2", @@ -892,7 +908,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_3] =3D { .name =3D "adis16465-3", @@ -909,7 +927,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_1] =3D { .name =3D "adis16467-1", @@ -926,7 +946,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_2] =3D { .name =3D "adis16467-2", @@ -943,7 +965,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_3] =3D { .name =3D "adis16467-3", @@ -960,7 +984,9 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .max_dec =3D 1999, .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), - .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts), + .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16500] =3D { .name =3D "adis16500", @@ -979,7 +1005,9 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16500, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16500, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16501] =3D { .name =3D "adis16501", @@ -998,7 +1026,9 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16501, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16501, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_1] =3D { .name =3D "adis16505-1", @@ -1017,7 +1047,9 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_2] =3D { .name =3D "adis16505-2", @@ -1036,7 +1068,9 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_3] =3D { .name =3D "adis16505-3", @@ -1055,7 +1089,9 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_1] =3D { .name =3D "adis16507-1", @@ -1074,7 +1110,9 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_2] =3D { .name =3D "adis16507-2", @@ -1093,7 +1131,9 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts), + .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_3] =3D { .name =3D "adis16507-3", @@ -1112,7 +1152,9 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { /* pulse sync not supported */ .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 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([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:47:58 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 4/9] iio: imu: adis_buffer: Add buffer setup API with buffer attributes Date: Fri, 17 May 2024 10:47:45 +0300 Message-Id: <20240517074750.87376-5-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add new API called devm_adis_setup_buffer_and_trigger_with_attrs() which also takes buffer attributes as a parameter. Rewrite devm_adis_setup_buffer_and_trigger() implementation such that it calls devm_adis_setup_buffer_and_trigger_with_attrs() with buffer attributes parameter NULL Signed-off-by: Ramona Gradinariu --- changes in v3: - added forward declaration for iio_dev_attr drivers/iio/imu/adis_buffer.c | 32 ++++++++++++++++++-------------- include/linux/iio/imu/adis.h | 19 +++++++++++++++---- 2 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/iio/imu/adis_buffer.c b/drivers/iio/imu/adis_buffer.c index 928933027ae3..871b78b225e2 100644 --- a/drivers/iio/imu/adis_buffer.c +++ b/drivers/iio/imu/adis_buffer.c @@ -175,31 +175,36 @@ static void adis_buffer_cleanup(void *arg) } /** - * devm_adis_setup_buffer_and_trigger() - Sets up buffer and trigger for - * the managed adis device + * devm_adis_setup_buffer_and_trigger_with_attrs() - Sets up buffer and tr= igger + * for the managed adis device with buffer attributes. * @adis: The adis device * @indio_dev: The IIO device - * @trigger_handler: Optional trigger handler, may be NULL. + * @trigger_handler: Trigger handler: should handle the buffer readings. + * @ops: Optional buffer setup functions, may be NULL. + * @buffer_attrs: Extra buffer attributes. * * Returns 0 on success, a negative error code otherwise. * - * This function sets up the buffer and trigger for a adis devices. If - * 'trigger_handler' is NULL the default trigger handler will be used. The - * default trigger handler will simply read the registers assigned to the - * currently active channels. + * This function sets up the buffer (with buffer setup functions and extra + * buffer attributes) and trigger for a adis devices with buffer attribute= s. */ int -devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indi= o_dev, - irq_handler_t trigger_handler) +devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, struct ii= o_dev *indio_dev, + irq_handler_t trigger_handler, + const struct iio_buffer_setup_ops *ops, + const struct iio_dev_attr **buffer_attrs) { int ret; if (!trigger_handler) trigger_handler =3D adis_trigger_handler; - ret =3D devm_iio_triggered_buffer_setup(&adis->spi->dev, indio_dev, - &iio_pollfunc_store_time, - trigger_handler, NULL); + ret =3D devm_iio_triggered_buffer_setup_ext(&adis->spi->dev, indio_dev, + &iio_pollfunc_store_time, + trigger_handler, + IIO_BUFFER_DIRECTION_IN, + ops, + buffer_attrs); if (ret) return ret; @@ -212,5 +217,4 @@ devm_adis_setup_buffer_and_trigger(struct adis *adis, s= truct iio_dev *indio_dev, return devm_add_action_or_reset(&adis->spi->dev, adis_buffer_cleanup, adis); } -EXPORT_SYMBOL_NS_GPL(devm_adis_setup_buffer_and_trigger, IIO_ADISLIB); - +EXPORT_SYMBOL_NS_GPL(devm_adis_setup_buffer_and_trigger_with_attrs, IIO_AD= ISLIB); diff --git a/include/linux/iio/imu/adis.h b/include/linux/iio/imu/adis.h index 8898966bc0f0..8dda3cfa5773 100644 --- a/include/linux/iio/imu/adis.h +++ b/include/linux/iio/imu/adis.h @@ -21,6 +21,7 @@ #define ADIS_REG_PAGE_ID 0x00 struct adis; +struct iio_dev_attr; /** * struct adis_timeouts - ADIS chip variant timeouts @@ -515,11 +516,19 @@ int adis_single_conversion(struct iio_dev *indio_dev, #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \ ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits) +#define devm_adis_setup_buffer_and_trigger(adis, indio_dev, trigger_handle= r) \ + devm_adis_setup_buffer_and_trigger_with_attrs((adis), (indio_dev), \ + (trigger_handler), NULL, \ + NULL) + #ifdef CONFIG_IIO_ADIS_LIB_BUFFER int -devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indi= o_dev, - irq_handler_t trigger_handler); +devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, + struct iio_dev *indio_dev, + irq_handler_t trigger_handler, + const struct iio_buffer_setup_ops *ops, + const struct iio_dev_attr **buffer_attrs); int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev); @@ -529,8 +538,10 @@ int adis_update_scan_mode(struct iio_dev *indio_dev, #else /* CONFIG_IIO_BUFFER */ static inline int -devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indi= o_dev, - irq_handler_t trigger_handler) +devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, struct ii= o_dev *indio_dev, + irq_handler_t trigger_handler, + const struct iio_buffer_setup_ops *ops, + const struct iio_dev_attr **buffer_attrs) { return 0; } -- 2.34.1 From nobody Sat Feb 14 02:50:33 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C616B25778; 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([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:47:59 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 5/9] iio: imu: adis16475: Create push single sample API Date: Fri, 17 May 2024 10:47:46 +0300 Message-Id: <20240517074750.87376-6-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create push single sample API reposnsible for pushing a single sample into the buffer. This is a preparation patch for FIFO support where more than one sample has to be pushed in the trigger handler. Signed-off-by: Ramona Gradinariu --- no changes in v3 drivers/iio/imu/adis16475.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index f9455ecb348c..ab955efdad92 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -1249,9 +1249,8 @@ static void adis16475_burst32_check(struct adis16475 = *st) } } -static irqreturn_t adis16475_trigger_handler(int irq, void *p) +static int adis16475_push_single_sample(struct iio_poll_func *pf) { - struct iio_poll_func *pf =3D p; struct iio_dev *indio_dev =3D pf->indio_dev; struct adis16475 *st =3D iio_priv(indio_dev); struct adis *adis =3D &st->adis; @@ -1340,6 +1339,15 @@ static irqreturn_t adis16475_trigger_handler(int irq= , void *p) * array. */ adis16475_burst32_check(st); + return ret; +} + +static irqreturn_t adis16475_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + + adis16475_push_single_sample(pf); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; -- 2.34.1 From nobody Sat Feb 14 02:50:33 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 268192B9D8; Fri, 17 May 2024 07:48:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715932084; cv=none; b=mcurPmBWi3X5/eOirnbe2gbZSm1gQ5j1xAIU40m5tnNQ1HyUaYqYkl5lLeNoRQ5C1t1BeOPQXZWAn9lX150yQxIPRzH733fmqGtIlCk3u+YemwfIGWBIDLpQYztb2Xb1w2iFcGBj7C7EAIXUuZUgAQorEYEcaOjqVLWoN5Na6B0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715932084; c=relaxed/simple; bh=qrPs8pzoQiEEQ+2WlxJkaTF8LTHukfAGBXVl7LEaN+0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VQ4guKweAasRb8n87JXfDHulS2UME8/BccvoisGjGLZmLqNsJSd8/W4jqEgv4I+ix7RMDIJf5r9CHfzJchLxwM8ovQFW9yiL5pAvV2aZ5kxxT1tAY1Kdvhqbng2pppKHlFOHrbzMr+vKFEetWGJBghOhfqQ7w0rLCk9caqSVn38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=O5dD0JYR; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O5dD0JYR" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-34db6a299b8so6822984f8f.3; Fri, 17 May 2024 00:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715932081; x=1716536881; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ONh25RLYtcOHE0peb9x3jbUdlHltO15eKQQqQ+4uktc=; b=O5dD0JYRRlUjZgciP+sjTr9LdAg8kgvKvMWfDy2S0AygNY4MWhg7E/9iU2EDmrM1iQ JovQb63e1eslvHs7R21cT8OkRUBOgqLIG/rBzADAZZ9b8Akd0SviDl5fQO+h+xqNHdMa R90OUkYBaXjYoDhzuBUnFIeUljWHEz9NCsJ1aibWaWnUOy/cgh9Zy4vGMlyG10lNV4tF WX2zR0z95PhKgj7az25jY4OQiFmtwuDE0gGFXGP9ZSMsYyuPrXJYsqOVVj+3GEv6nUrp xnkgLjZPJrRIa028dbLCOEuWTA/a6cFK8wVjtNa8Y8LgWHpmtv77LGYzeu4iYDGr4ilq mM9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715932081; x=1716536881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ONh25RLYtcOHE0peb9x3jbUdlHltO15eKQQqQ+4uktc=; b=iIjuIPsldUC4wMHUOVuJKf51umPMv7AJBdpcxKPhc/TdtI3QnKvLI35TTZUDDF3zzG bhOAyKevBRsi3VGq+vrSqDAFeOPZEbcvSpyBhlNP9iioGYa4ATUW20Go5jBNk3iO+2pm 1Eb0MxFq1LfZWjOxerv4Kfozu7fP6/brHnfgruOVWj4QmdVJY5A51W/w/NGlYh4H9RZP /IFD7OY2QA2sY//9zieLbtiyaXgnlade4lFw2trRFw0de42UTUTHC97wbkFn+9AypFGd ms+7iuroYbUkKNrXuTMcgVig4wYpGwltIKLElH8mg81ebZ24b/5TfKBArk2V5gq9eir5 mZwg== X-Forwarded-Encrypted: i=1; AJvYcCWCy8VS6GHdLIiyb9A2TvCuMEnoXKZZEw09zuRX9sbnTh4Zts8U0Fd1C5SmqEA/eZzkkMCrEVWOfz78yWlX5Vu7VmGxp5uemxaB3ffJ6mr8MVitvdcxJby9KvvcsDTdpksu67UvZA== X-Gm-Message-State: AOJu0YybC64z41P8xdpL2zfikXgsvToRKRqW/0CKPyVDAC8k0jwPqGGN +OLA/LXOG5qIcfAX+3P8E0y2htWA+kUsPt8H+KObL5GvCmJE5B2EY2hgBm3hEVA= X-Google-Smtp-Source: AGHT+IHb385/qxqs7vnJ7HSY0R40KN1Mhv6uCoAj7/Ta5PKKCffL168S9N9qHgS1HWyZVR5NJzFe1A== X-Received: by 2002:a5d:4fc2:0:b0:34d:750c:8b9 with SMTP id ffacd0b85a97d-3504a958127mr14052233f8f.51.1715932080877; Fri, 17 May 2024 00:48:00 -0700 (PDT) Received: from rbolboac.. ([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:48:00 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 6/9] drivers: iio: imu: adis16475: generic computation for sample rate Date: Fri, 17 May 2024 10:47:47 +0300 Message-Id: <20240517074750.87376-7-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently adis16475 supports a sample rate between 1900 and 2100 Hz. This patch changes the setting of sample rate from hardcoded values to a generic computation based on the internal clock frequency. This is a preparatory patch for adding support for adis1657x family devices which allow sample rates between 3900 and 4100 Hz. Signed-off-by: Ramona Gradinariu --- no changes in v3 drivers/iio/imu/adis16475.c | 39 +++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index ab955efdad92..c589f214259b 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -310,6 +310,9 @@ static int adis16475_set_freq(struct adis16475 *st, con= st u32 freq) u16 dec; int ret; u32 sample_rate =3D st->clk_freq; + /* The optimal sample rate for the supported IMUs is between int_clk - 10= 0 and int_clk + 100. */ + u32 max_sample_rate =3D st->info->int_clk * 1000 + 100000; + u32 min_sample_rate =3D st->info->int_clk * 1000 - 100000; if (!freq) return -EINVAL; @@ -317,8 +320,9 @@ static int adis16475_set_freq(struct adis16475 *st, con= st u32 freq) adis_dev_lock(&st->adis); /* * When using sync scaled mode, the input clock needs to be scaled so tha= t we have - * an IMU sample rate between (optimally) 1900 and 2100. After this, we c= an use the - * decimation filter to lower the sampling rate in order to get what the = user wants. + * an IMU sample rate between (optimally) int_clk - 100 and int_clk + 100. + * After this, we can use the decimation filter to lower the sampling rat= e in order + * to get what the user wants. * Optimally, the user sample rate is a multiple of both the IMU sample r= ate and * the input clock. Hence, calculating the sync_scale dynamically gives u= s better * chances of achieving a perfect/integer value for DEC_RATE. The math he= re is: @@ -336,23 +340,24 @@ static int adis16475_set_freq(struct adis16475 *st, c= onst u32 freq) * solution. In this case, we get the highest multiple of the input clock * lower than the IMU max sample rate. */ - if (scaled_rate > 2100000) - scaled_rate =3D 2100000 / st->clk_freq * st->clk_freq; + if (scaled_rate > max_sample_rate) + scaled_rate =3D max_sample_rate / st->clk_freq * st->clk_freq; else - scaled_rate =3D 2100000 / scaled_rate * scaled_rate; + scaled_rate =3D max_sample_rate / scaled_rate * scaled_rate; /* * This is not an hard requirement but it's not advised to run the IMU - * with a sample rate lower than 1900Hz due to possible undersampling - * issues. However, there are users that might really want to take the r= isk. - * Hence, we provide a module parameter for them. If set, we allow sample - * rates lower than 1.9KHz. By default, we won't allow this and we just = roundup - * the rate to the next multiple of the input clock bigger than 1.9KHz. = This - * is done like this as in some cases (when DEC_RATE is 0) might give - * us the closest value to the one desired by the user... + * with a sample rate lower than internal clock frequency, due to possib= le + * undersampling issues. However, there are users that might really want + * to take the risk. Hence, we provide a module parameter for them. If s= et, + * we allow sample rates lower than internal clock frequency. + * By default, we won't allow this and we just roundup the rate to the n= ext + * multiple of the input clock. This is done like this as in some cases + * (when DEC_RATE is 0) might give us the closest value to the one desir= ed + * by the user... */ - if (scaled_rate < 1900000 && !low_rate_allow) - scaled_rate =3D roundup(1900000, st->clk_freq); + if (scaled_rate < min_sample_rate && !low_rate_allow) + scaled_rate =3D roundup(min_sample_rate, st->clk_freq); sync_scale =3D scaled_rate / st->clk_freq; ret =3D __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scal= e); @@ -1359,6 +1364,7 @@ static int adis16475_config_sync_mode(struct adis1647= 5 *st) struct device *dev =3D &st->adis.spi->dev; const struct adis16475_sync *sync; u32 sync_mode; + u16 max_sample_rate =3D st->info->int_clk + 100; /* default to internal clk */ st->clk_freq =3D st->info->int_clk * 1000; @@ -1398,10 +1404,9 @@ static int adis16475_config_sync_mode(struct adis164= 75 *st) /* * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scal= e. * Hence, default the IMU sample rate to the highest multiple of the in= put - * clock lower than the IMU max sample rate. The optimal range is - * 1900-2100 sps... + * clock lower than the IMU max sample rate. */ - up_scale =3D 2100 / st->clk_freq; + up_scale =3D max_sample_rate / st->clk_freq; ret =3D __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, -- 2.34.1 From nobody Sat Feb 14 02:50:33 2026 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7007D2C6B9; Fri, 17 May 2024 07:48:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715932086; cv=none; b=Sk3WGtSnWXYy2fVJvJHruuemg0excYSFJiUCOuCDEsOkvXl67xBAriss5iZux03JxO13n6XAzGN9FaMdqBE1iBHzF9znp45/KFmIXXwndJzHx6ldv1HPk2QL1VIDrEJQrJCbCDei0j4D/U/6UVJl4XbW1fOpaCECAD06xvN86pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715932086; c=relaxed/simple; bh=gaBUrEFUVynj2sCVorwDcz41asBIy8HZEKPMsGjdOlU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EncLXU3iILF51F8FMuor88k1d+GEAo10M4YAjLg82YD3OjrynvsYCCnhiXdJum2SNJQEGkR7zTRuPk8KXHqCYvn3RWfOVx6zzI3HzohRpTAQZUy0SO2xdRHnhBIf/QLayV4U8CrFH5yRcae+Ibj71+D79ZGwFUymUplqDoADnYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hbLOXQ7E; arc=none smtp.client-ip=209.85.208.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hbLOXQ7E" Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2e6f33150bcso17068321fa.2; Fri, 17 May 2024 00:48:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715932082; x=1716536882; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aOo+pbvRtWZONom15kwmr0KzPQ/8pIzCsgN9MAmxo9k=; b=hbLOXQ7E6as724TlhQIoYK1xnSFY5+5esF/hLm2y9LRSKFaI5QaOD6BmtbONpyRG/v eZYpYN/GlXZAiQUm7zyU8WCRvZJPpXQ/nVcoF3Jfud8ayGk6b+WgyO2qO5RalPI1XXrX PCFjxpZlsVYGI2puExwpamFX5HqwDAZq5jlz14qAgwFvHtpB2t9YBcC7dz5eyEb6YkPY G6fBy/T+PQDEr6dQ6p25qQC688FMVyhJpe6mZ4ROPpq+4Lm1q0XDfIrV3I/eC/ZSmuL5 EG2E2BrZLzp0jSeXVcpTOm8y0A/aXuLUbEQvT3M+XN4P7BAnrKPu5mQnw8fzYUU+UkdQ 9MrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715932082; x=1716536882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aOo+pbvRtWZONom15kwmr0KzPQ/8pIzCsgN9MAmxo9k=; b=rnL+OOeDttrTR+LR/onXo2fglKOLHivJtngoPLozICRbAv8MUOWxKQ8gLJsFgdnpkp 3n5q0jJKkONo6fv5k5arhAFevZKvIrZ6zooa9aE5d/8H67RQ9/a6/KGWKpbzH3NLOtnK c/ruQPjs4OrVuNfX6zmb8IZHt07gaiB9AD+vOnXxbczTRsiJWOQ9aYbFPahT1CFuwjgU n6D96BnXl55pqJO72/tq+X7s9SYaB895FxGh0s29cvvT1dkvTU3epBbUjeEJqZD4uJ6O g+WbrBjWs0g6VnsLeUfCa8AFDKl3DKusRM6gIUiQz26tUzEkbrAdGlGUCBOzeXy8cRkQ ORkA== X-Forwarded-Encrypted: i=1; AJvYcCUKf1WEGSDPK9T0N4l7fCAFl5V/pakOb3Kqq2Y3HlDJnalGpZCrJNx0IVt00/k+gZqphgGnkJ/nu2eAsjU//CGTicAPhow70a2KO8GT0MTTuSf5j2BCcZZzA3aLhaME+5R9oI6iww== X-Gm-Message-State: AOJu0Yy/FfiRdlC6xSx/nTSEXt92CXu0vhNVMUHMcfYFQLg2i7ZcCvpI 07WFtG4fLxhsiRbrBxV25j4btfELU0kFH+WTxGCrNibZEzC9Z+gY4JrvqDRlAGc= X-Google-Smtp-Source: AGHT+IGqBfCCz5oZGn2uraZaY9GVMlIUEGVItJ03FgXFFJlZip/rfOtXOLWw2Bs5ZdFp7lrJYTm/ww== X-Received: by 2002:a2e:a54c:0:b0:2e1:f5d3:a6a4 with SMTP id 38308e7fff4ca-2e51fe589e9mr165062831fa.23.1715932082021; Fri, 17 May 2024 00:48:02 -0700 (PDT) Received: from rbolboac.. ([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:48:01 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 7/9] iio: imu: adis_trigger: Allow level interrupts Date: Fri, 17 May 2024 10:47:48 +0300 Message-Id: <20240517074750.87376-8-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, adis library allows configuration only for edge interrupts, needed for data ready sampling. This patch removes the restriction for level interrupts, which are needed to handle FIFO watermark interrupts. Furthermore, in case of level interrupts, devm_request_threaded_irq is used for interrupt allocation, to avoid blocking the processor while retrieving the FIFO samples. Signed-off-by: Ramona Gradinariu --- changes in v3: - new patch drivers/iio/imu/adis_trigger.c | 39 ++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/iio/imu/adis_trigger.c b/drivers/iio/imu/adis_trigger.c index f890bf842db8..becf1f558b4e 100644 --- a/drivers/iio/imu/adis_trigger.c +++ b/drivers/iio/imu/adis_trigger.c @@ -34,21 +34,16 @@ static int adis_validate_irq_flag(struct adis *adis) if (adis->data->unmasked_drdy) adis->irq_flag |=3D IRQF_NO_AUTOEN; /* - * Typically this devices have data ready either on the rising edge or - * on the falling edge of the data ready pin. This checks enforces that - * one of those is set in the drivers... It defaults to - * IRQF_TRIGGER_RISING for backward compatibility with devices that - * don't support changing the pin polarity. + * Typically adis devices without fifo have data ready either on the + * rising edge or on the falling edge of the data ready pin. + * IMU devices with fifo support have the watermark pin level driven + * either high or low when the fifo is filled with the desired number + * of samples. + * It defaults to IRQF_TRIGGER_RISING for backward compatibility with + * devices that don't support changing the pin polarity. */ - if (direction =3D=3D IRQF_TRIGGER_NONE) { + if (direction =3D=3D IRQF_TRIGGER_NONE) adis->irq_flag |=3D IRQF_TRIGGER_RISING; - return 0; - } else if (direction !=3D IRQF_TRIGGER_RISING && - direction !=3D IRQF_TRIGGER_FALLING) { - dev_err(&adis->spi->dev, "Invalid IRQ mask: %08lx\n", - adis->irq_flag); - return -EINVAL; - } return 0; } @@ -77,11 +72,19 @@ int devm_adis_probe_trigger(struct adis *adis, struct i= io_dev *indio_dev) if (ret) return ret; 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([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:48:02 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu , Conor Dooley Subject: [PATCH v3 8/9] dt-bindings: iio: imu: Add ADIS1657X family devices compatibles Date: Fri, 17 May 2024 10:47:49 +0300 Message-Id: <20240517074750.87376-9-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ADIS1657X family devices compatibles and specify the according maximum SPI baudrate. Similarly to other ADIS1650X devices, ADIS1657X supports sync-mode values [0,2]. Each newly added device has a different angular velocity/linear acceleration/ delta velocity scale combination, as follows: Accel dynamic range sensitivity: - 262144000 LSB/g: ADIS16575 - 52428800 LSB/g: ADIS16576, ADIS16577 Gyro dynamic range sensitivity: - 2621440 LSB/deg/sec: ADIS1575-2, ADIS1576-2, ADIS1577-2 - 655360 LSB/deg/sec: ADIS1575-3, ADIS1576-3, ADIS1577-3 Delta velocity sensitivity: - 2^15/100 LSB/m/sec: ADIS16575 - 2^15/125 LSB/m/sec: ADIS16576 - 2^15/400 LSB/m/sec: ADIS16577 Each ADIS1657X device supports FIFO usage and a sample-rate of 4.1KHz, meanwhile the already existing devices do not support FIFO usage and have a maximum sample-rate of 2.1KHz. Reviewed-by: Conor Dooley Signed-off-by: Ramona Gradinariu --- no changes in v3 .../bindings/iio/imu/adi,adis16475.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b= /Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml index db52e7063116..9d185f7bfdcb 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -37,6 +37,12 @@ properties: - adi,adis16507-1 - adi,adis16507-2 - adi,adis16507-3 + - adi,adis16575-2 + - adi,adis16575-3 + - adi,adis16576-2 + - adi,adis16576-3 + - adi,adis16577-2 + - adi,adis16577-3 reg: maxItems: 1 @@ -98,6 +104,12 @@ allOf: - adi,adis16507-1 - adi,adis16507-2 - adi,adis16507-3 + - adi,adis16575-2 + - adi,adis16575-3 + - adi,adis16576-2 + - adi,adis16576-3 + - adi,adis16577-2 + - adi,adis16577-3 then: properties: @@ -114,6 +126,23 @@ allOf: dependencies: adi,sync-mode: [ clocks ] + - if: + properties: + compatible: + contains: + enum: + - adi,adis16575-2 + - adi,adis16575-3 + - adi,adis16576-2 + - adi,adis16576-3 + - adi,adis16577-2 + - adi,adis16577-3 + + then: + properties: + spi-max-frequency: + maximum: 15000000 + unevaluatedProperties: false examples: -- 2.34.1 From nobody Sat Feb 14 02:50:33 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 490C6364AF; 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([2a02:2f0e:350b:4500:569e:359d:dfe4:922e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502baacef2sm21104207f8f.85.2024.05.17.00.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 00:48:03 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH v3 9/9] drivers: iio: imu: Add support for adis1657x family Date: Fri, 17 May 2024 10:47:50 +0300 Message-Id: <20240517074750.87376-10-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> References: <20240517074750.87376-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for ADIS1657X family devices in already exiting ADIS16475 driver. Signed-off-by: Ramona Gradinariu --- changes in v3: - changed format in sysfs_emit - created new function adis16575_update_msg_for_burst to make it more obvi= ous that adis message is changing based on the given burst request value - adjusted line wrapping for adis16475_trigger_handler_with_fifo comment - fixed comment typo regarding watermark pin polarity - configured level interrupts in case device has FIFO drivers/iio/imu/adis16475.c | 628 ++++++++++++++++++++++++++++++++---- 1 file changed, 561 insertions(+), 67 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index c589f214259b..a1a14b0757e8 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,8 @@ FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) +#define ADIS16575_SYNC_4KHZ_MASK BIT(11) +#define ADIS16575_SYNC_4KHZ(x) FIELD_PREP(ADIS16575_SYNC_4KHZ_MASK, x) #define ADIS16475_REG_UP_SCALE 0x62 #define ADIS16475_REG_DEC_RATE 0x64 #define ADIS16475_REG_GLOB_CMD 0x68 @@ -65,15 +68,32 @@ #define ADIS16500_BURST32_MASK BIT(9) #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) /* number of data elements in burst mode */ -#define ADIS16475_BURST32_MAX_DATA 32 +#define ADIS16475_BURST32_MAX_DATA_NO_TS32 32 +#define ADIS16575_BURST32_DATA_TS32 34 #define ADIS16475_BURST_MAX_DATA 20 #define ADIS16475_MAX_SCAN_DATA 20 /* spi max speed in brust mode */ #define ADIS16475_BURST_MAX_SPEED 1000000 +#define ADIS16575_BURST_MAX_SPEED 8000000 #define ADIS16475_LSB_DEC_MASK 0 #define ADIS16475_LSB_FIR_MASK 1 #define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) #define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7) +#define ADIS16575_MAX_FIFO_WM 511UL +#define ADIS16475_REG_FIFO_CTRL 0x5A +#define ADIS16575_WM_LVL_MASK GENMASK(15, 4) +#define ADIS16575_WM_LVL(x) FIELD_PREP(ADIS16575_WM_LVL_MASK, x) +#define ADIS16575_WM_POL_MASK BIT(3) +#define ADIS16575_WM_POL(x) FIELD_PREP(ADIS16575_WM_POL_MASK, x) +#define ADIS16575_WM_EN_MASK BIT(2) +#define ADIS16575_WM_EN(x) FIELD_PREP(ADIS16575_WM_EN_MASK, x) +#define ADIS16575_OVERFLOW_MASK BIT(1) +#define ADIS16575_STOP_ENQUEUE FIELD_PREP(ADIS16575_OVERFLOW_MASK, 0) +#define ADIS16575_OVERWRITE_OLDEST FIELD_PREP(ADIS16575_OVERFLOW_MASK, 1) +#define ADIS16575_FIFO_EN_MASK BIT(0) +#define ADIS16575_FIFO_EN(x) FIELD_PREP(ADIS16575_FIFO_EN_MASK, x) +#define ADIS16575_FIFO_FLUSH_CMD BIT(5) +#define ADIS16575_REG_FIFO_CNT 0x3C enum { ADIS16475_SYNC_DIRECT =3D 1, @@ -95,6 +115,9 @@ struct adis16475_chip_info { const char *name; #define ADIS16475_HAS_BURST32 BIT(0) #define ADIS16475_HAS_BURST_DELTA_DATA BIT(1) +#define ADIS16475_HAS_TIMESTAMP32 BIT(2) +#define ADIS16475_NEEDS_BURST_REQUEST BIT(3) +#define ADIS16475_HAS_FIFO BIT(4) const long flags; u32 num_channels; u32 gyro_max_val; @@ -116,6 +139,7 @@ struct adis16475 { bool burst32; unsigned long lsb_flag; u16 sync_mode; + u16 fifo_watermark; /* Alignment needed for the timestamp */ __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); }; @@ -442,6 +466,124 @@ static int adis16475_set_filter(struct adis16475 *st,= const u32 filter) return 0; } +static ssize_t adis16475_get_fifo_enabled(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct adis16475 *st =3D iio_priv(indio_dev); + int ret; + u16 val; + + ret =3D adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); + if (ret) + return ret; + + return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_FIFO_EN_MASK, val)); +} + +static ssize_t adis16475_get_fifo_watermark(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct adis16475 *st =3D iio_priv(indio_dev); + int ret; + u16 val; + + ret =3D adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); + if (ret) + return ret; + + return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_WM_LVL_MASK, val) + 1= ); +} + +static ssize_t hwfifo_watermark_min_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sysfs_emit(buf, "1\n"); +} + +static ssize_t hwfifo_watermark_max_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sysfs_emit(buf, "%lu\n", ADIS16575_MAX_FIFO_WM); +} + +static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); +static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); +static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, + adis16475_get_fifo_watermark, NULL, 0); +static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, + adis16475_get_fifo_enabled, NULL, 0); + +static const struct iio_dev_attr *adis16475_fifo_attributes[] =3D { + &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr, + &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr, + &iio_dev_attr_hwfifo_watermark.dev_attr.attr, + &iio_dev_attr_hwfifo_enabled.dev_attr.attr, + NULL +}; + +static int adis16475_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adis16475 *st =3D iio_priv(indio_dev); + struct adis *adis =3D &st->adis; + + return adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, + ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(1)); +} + +static int adis16475_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct adis16475 *st =3D iio_priv(indio_dev); + struct adis *adis =3D &st->adis; + int ret; + + adis_dev_lock(&st->adis); + + ret =3D __adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, + ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(0)); + if (ret) + goto unlock; + + ret =3D __adis_write_reg_16(adis, ADIS16475_REG_GLOB_CMD, + ADIS16575_FIFO_FLUSH_CMD); + +unlock: + adis_dev_unlock(&st->adis); + return ret; +} + +static const struct iio_buffer_setup_ops adis16475_buffer_ops =3D { + .postenable =3D adis16475_buffer_postenable, + .postdisable =3D adis16475_buffer_postdisable, +}; + +static int adis16475_set_watermark(struct iio_dev *indio_dev, unsigned int= val) +{ + struct adis16475 *st =3D iio_priv(indio_dev); + int ret; + u16 wm_lvl; + + adis_dev_lock(&st->adis); + + val =3D min_t(unsigned int, val, ADIS16575_MAX_FIFO_WM); + + wm_lvl =3D ADIS16575_WM_LVL(val - 1); + ret =3D __adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16575_= WM_LVL_MASK, wm_lvl); + if (ret) + goto unlock; + + st->fifo_watermark =3D val; + +unlock: + adis_dev_unlock(&st->adis); + return ret; +} + static const u32 adis16475_calib_regs[] =3D { [ADIS16475_SCAN_GYRO_X] =3D ADIS16475_REG_X_GYRO_BIAS_L, [ADIS16475_SCAN_GYRO_Y] =3D ADIS16475_REG_Y_GYRO_BIAS_L, @@ -673,6 +815,12 @@ enum adis16475_variant { ADIS16507_1, ADIS16507_2, ADIS16507_3, + ADIS16575_2, + ADIS16575_3, + ADIS16576_2, + ADIS16576_3, + ADIS16577_2, + ADIS16577_3, }; enum { @@ -730,6 +878,12 @@ static const struct adis16475_sync adis16475_sync_mode= [] =3D { { ADIS16475_SYNC_PULSE, 1000, 2100 }, }; +static const struct adis16475_sync adis16575_sync_mode[] =3D { + { ADIS16475_SYNC_OUTPUT }, + { ADIS16475_SYNC_DIRECT, 1900, 4100 }, + { ADIS16475_SYNC_SCALED, 1, 400 }, +}; + static const struct adis_timeout adis16475_timeouts =3D { .reset_ms =3D 200, .sw_reset_ms =3D 200, @@ -759,7 +913,7 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16470, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_1] =3D { @@ -778,7 +932,7 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_2] =3D { @@ -797,7 +951,7 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_3] =3D { @@ -816,7 +970,7 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16475, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_1] =3D { @@ -836,7 +990,7 @@ static const struct adis16475_chip_info adis16475_chip_= info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_2] =3D { @@ -856,7 +1010,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_3] =3D { @@ -876,7 +1030,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16477, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_1] =3D { @@ -895,7 +1049,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_2] =3D { @@ -914,7 +1068,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_3] =3D { @@ -933,7 +1087,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16465, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_1] =3D { @@ -952,7 +1106,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_2] =3D { @@ -971,7 +1125,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_3] =3D { @@ -990,7 +1144,7 @@ static const struct adis16475_chip_info adis16475_chip= _info[] =3D { .sync =3D adis16475_sync_mode, .num_sync =3D ARRAY_SIZE(adis16475_sync_mode), .adis_data =3D ADIS16475_DATA(16467, &adis16475_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16500] =3D { @@ -1011,7 +1165,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16500, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16501] =3D { @@ -1032,7 +1186,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16501, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_1] =3D { @@ -1053,7 +1207,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_2] =3D { @@ -1074,7 +1228,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_3] =3D { @@ -1095,7 +1249,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16505, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_1] =3D { @@ -1116,7 +1270,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_2] =3D { @@ -1137,7 +1291,7 @@ static const struct adis16475_chip_info adis16475_chi= p_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_3] =3D { @@ -1158,9 +1312,153 @@ static const struct adis16475_chip_info adis16475_c= hip_info[] =3D { .num_sync =3D ARRAY_SIZE(adis16475_sync_mode) - 1, .flags =3D ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data =3D ADIS16475_DATA(16507, &adis1650x_timeouts, - ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST32_MAX_DATA_NO_TS32, ADIS16475_BURST_MAX_SPEED), }, + [ADIS16575_2] =3D { + .name =3D "adis16575-2", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val =3D 8, + .accel_max_scale =3D IIO_M_S_2_TO_G(32000 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(450), + .deltvel_max_val =3D 100, + .int_clk =3D 4000, + .max_dec =3D 3999, + .sync =3D adis16575_sync_mode, + .num_sync =3D ARRAY_SIZE(adis16575_sync_mode), + .flags =3D ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data =3D ADIS16475_DATA(16575, &adis16475_timeouts, + ADIS16575_BURST32_DATA_TS32, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16575_3] =3D { + .name =3D "adis16575-3", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val =3D 8, + .accel_max_scale =3D IIO_M_S_2_TO_G(32000 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(2000), + .deltvel_max_val =3D 100, + .int_clk =3D 4000, + .max_dec =3D 3999, + .sync =3D adis16575_sync_mode, + .num_sync =3D ARRAY_SIZE(adis16575_sync_mode), + .flags =3D ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data =3D ADIS16475_DATA(16575, &adis16475_timeouts, + ADIS16575_BURST32_DATA_TS32, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16576_2] =3D { + .name =3D "adis16576-2", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val =3D 40, + .accel_max_scale =3D IIO_M_S_2_TO_G(32000 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(450), + .deltvel_max_val =3D 125, + .int_clk =3D 4000, + .max_dec =3D 3999, + .sync =3D adis16575_sync_mode, + .num_sync =3D ARRAY_SIZE(adis16575_sync_mode), + .flags =3D ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data =3D ADIS16475_DATA(16576, &adis16475_timeouts, + ADIS16575_BURST32_DATA_TS32, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16576_3] =3D { + .name =3D "adis16576-3", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val =3D 40, + .accel_max_scale =3D IIO_M_S_2_TO_G(32000 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(2000), + .deltvel_max_val =3D 125, + .int_clk =3D 4000, + .max_dec =3D 3999, + .sync =3D adis16575_sync_mode, + .num_sync =3D ARRAY_SIZE(adis16575_sync_mode), + .flags =3D ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data =3D ADIS16475_DATA(16576, &adis16475_timeouts, + ADIS16575_BURST32_DATA_TS32, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16577_2] =3D { + .name =3D "adis16577-2", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val =3D 40, + .accel_max_scale =3D IIO_M_S_2_TO_G(32000 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(450), + .deltvel_max_val =3D 400, + .int_clk =3D 4000, + .max_dec =3D 3999, + .sync =3D adis16575_sync_mode, + .num_sync =3D ARRAY_SIZE(adis16575_sync_mode), + .flags =3D ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data =3D ADIS16475_DATA(16577, &adis16475_timeouts, + ADIS16575_BURST32_DATA_TS32, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16577_3] =3D { + .name =3D "adis16577-3", + .num_channels =3D ARRAY_SIZE(adis16477_channels), + .channels =3D adis16477_channels, + .gyro_max_val =3D 1, + .gyro_max_scale =3D IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val =3D 40, + .accel_max_scale =3D IIO_M_S_2_TO_G(32000 << 16), + .temp_scale =3D 100, + .deltang_max_val =3D IIO_DEGREE_TO_RAD(2000), + .deltvel_max_val =3D 400, + .int_clk =3D 4000, + .max_dec =3D 3999, + .sync =3D adis16575_sync_mode, + .num_sync =3D ARRAY_SIZE(adis16575_sync_mode), + .flags =3D ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data =3D ADIS16475_DATA(16577, &adis16475_timeouts, + ADIS16575_BURST32_DATA_TS32, + ADIS16575_BURST_MAX_SPEED), + }, }; static int adis16475_update_scan_mode(struct iio_dev *indio_dev, @@ -1195,15 +1493,19 @@ static const struct iio_info adis16475_info =3D { .debugfs_reg_access =3D adis_debugfs_reg_access, }; +static const struct iio_info adis16575_info =3D { + .read_raw =3D &adis16475_read_raw, + .write_raw =3D &adis16475_write_raw, + .update_scan_mode =3D adis16475_update_scan_mode, + .debugfs_reg_access =3D adis_debugfs_reg_access, + .hwfifo_set_watermark =3D adis16475_set_watermark, +}; + static bool adis16475_validate_crc(const u8 *buffer, u16 crc, - const bool burst32) + u16 burst_size, u16 start_idx) { int i; - /* extra 6 elements for low gyro and accel */ - const u16 sz =3D burst32 ? ADIS16475_BURST32_MAX_DATA : - ADIS16475_BURST_MAX_DATA; - - for (i =3D 0; i < sz - 2; i++) + for (i =3D start_idx; i < burst_size - 2; i++) crc -=3D buffer[i]; return crc =3D=3D 0; @@ -1213,10 +1515,14 @@ static void adis16475_burst32_check(struct adis1647= 5 *st) { int ret; struct adis *adis =3D &st->adis; + u8 timestamp32 =3D 0; if (!(st->info->flags & ADIS16475_HAS_BURST32)) return; + if (st->info->flags & ADIS16475_HAS_TIMESTAMP32) + timestamp32 =3D 1; + if (st->lsb_flag && !st->burst32) { const u16 en =3D ADIS16500_BURST32(1); @@ -1230,9 +1536,12 @@ static void adis16475_burst32_check(struct adis16475= *st) /* * In 32-bit mode we need extra 2 bytes for all gyro * and accel channels. + * If the device has 32-bit timestamp value we need 2 extra + * bytes for it. */ - adis->burst_extra_len =3D 6 * sizeof(u16); - adis->xfer[1].len +=3D 6 * sizeof(u16); + adis->burst_extra_len =3D (6 + timestamp32) * sizeof(u16); + adis->xfer[1].len +=3D (6 + timestamp32) * sizeof(u16); + dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", adis->xfer[1].len); @@ -1248,7 +1557,7 @@ static void adis16475_burst32_check(struct adis16475 = *st) /* Remove the extra bits */ adis->burst_extra_len =3D 0; - adis->xfer[1].len -=3D 6 * sizeof(u16); + adis->xfer[1].len -=3D (6 + timestamp32) * sizeof(u16); dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", adis->xfer[1].len); } @@ -1263,20 +1572,30 @@ static int adis16475_push_single_sample(struct iio_= poll_func *pf) __be16 *buffer; u16 crc; bool valid; + u8 crc_offset =3D 9; + u16 burst_size =3D ADIS16475_BURST_MAX_DATA; + u16 start_idx =3D (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 2 : 0; + /* offset until the first element after gyro and accel */ const u8 offset =3D st->burst32 ? 13 : 7; + if (st->burst32) { + crc_offset =3D (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 16 : 15; + burst_size =3D (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? + ADIS16575_BURST32_DATA_TS32 : ADIS16475_BURST32_MAX_DATA_NO_TS32; + } + ret =3D spi_sync(adis->spi, &adis->msg); if (ret) - goto check_burst32; + return ret; buffer =3D adis->buffer; - crc =3D be16_to_cpu(buffer[offset + 2]); - valid =3D adis16475_validate_crc(adis->buffer, crc, st->burst32); + crc =3D be16_to_cpu(buffer[crc_offset]); + valid =3D adis16475_validate_crc(adis->buffer, crc, burst_size, start_idx= ); if (!valid) { dev_err(&adis->spi->dev, "Invalid crc\n"); - goto check_burst32; + return ret; } for_each_set_bit(bit, indio_dev->active_scan_mask, @@ -1337,22 +1656,123 @@ static int adis16475_push_single_sample(struct iio= _poll_func *pf) } iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); -check_burst32: + + return 0; +} + +static irqreturn_t adis16475_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct adis16475 *st =3D iio_priv(indio_dev); + + adis16475_push_single_sample(pf); /* * We only check the burst mode at the end of the current capture since * it takes a full data ready cycle for the device to update the burst * array. */ adis16475_burst32_check(st); - return ret; + + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; } -static irqreturn_t adis16475_trigger_handler(int irq, void *p) +/* + * This function updates the first tx byte from the adis message based on = the + * given burst request. + */ +static void adis16575_update_msg_for_burst(struct adis *adis, u8 burst_req) +{ + unsigned int burst_max_length; + u8 *tx; + + if (adis->data->burst_max_len) + burst_max_length =3D adis->data->burst_max_len; + else + burst_max_length =3D adis->data->burst_len + adis->burst_extra_len; + + tx =3D adis->buffer + burst_max_length; + tx[0] =3D ADIS_READ_REG(burst_req); +} + +static int adis16575_custom_burst_read(struct iio_poll_func *pf, u8 burst_= req) +{ + struct iio_dev *indio_dev =3D pf->indio_dev; + struct adis16475 *st =3D iio_priv(indio_dev); + struct adis *adis =3D &st->adis; + + adis16575_update_msg_for_burst(adis, burst_req); + + if (burst_req) + return spi_sync(adis->spi, &adis->msg); + + return adis16475_push_single_sample(pf); +} + +/* + * This handler is meant to be used for devices which support burst readin= gs + * from FIFO (namely devices from adis1657x family). + * In order to pop the FIFO the 0x68 0x00 FIFO pop burst request has to be= sent. + * If the previous device command was not a FIFO pop burst request, the FI= FO pop + * burst request will simply pop the FIFO without returning valid data. + * For the nth consecutive burst request, thedevice will send the data pop= ped + * with the (n-1)th consecutive burst request. + * In order to read the data which was popped previously, without popping = the + * FIFO, the 0x00 0x00 burst request has to be sent. + * If after a 0x68 0x00 FIFO pop burst request, there is any other device = access + * different from a 0x68 0x00 or a 0x00 0x00 burst request, the FIFO data = popped + * previously will be lost. + */ +static irqreturn_t adis16475_trigger_handler_with_fifo(int irq, void *p) { struct iio_poll_func *pf =3D p; struct iio_dev *indio_dev =3D pf->indio_dev; + struct adis16475 *st =3D iio_priv(indio_dev); + struct adis *adis =3D &st->adis; + int ret; + u16 fifo_cnt, i; - adis16475_push_single_sample(pf); + adis_dev_lock(&st->adis); + + ret =3D __adis_read_reg_16(adis, ADIS16575_REG_FIFO_CNT, &fifo_cnt); + if (ret) + goto unlock; + + /* + * If no sample is available, nothing can be read. This can happen if + * a the used trigger has a higher frequency than the selected sample rat= e. + */ + if (!fifo_cnt) + goto unlock; + + /* + * First burst request - FIFO pop: popped data will be returned in the + * next burst request. + */ + ret =3D adis16575_custom_burst_read(pf, adis->data->burst_reg_cmd); + if (ret) + goto unlock; + + for (i =3D 0; i < fifo_cnt - 1; i++) { + ret =3D adis16475_push_single_sample(pf); + if (ret) + goto unlock; + } + + /* FIFO read without popping */ + ret =3D adis16575_custom_burst_read(pf, 0); + if (ret) + goto unlock; + +unlock: + /* + * We only check the burst mode at the end of the current capture since + * reading data from registers will impact the FIFO reading. + */ + adis16475_burst32_check(st); + adis_dev_unlock(&st->adis); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; @@ -1366,6 +1786,14 @@ static int adis16475_config_sync_mode(struct adis164= 75 *st) u32 sync_mode; u16 max_sample_rate =3D st->info->int_clk + 100; + /* if available, enable 4khz internal clock */ + if (st->info->int_clk =3D=3D 4000) { + ret =3D __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16575_SYNC_4KHZ_MASK, (u16)ADIS16575_SYNC_4KHZ(1)); + if (ret) + return ret; + } + /* default to internal clk */ st->clk_freq =3D st->info->int_clk * 1000; @@ -1443,34 +1871,67 @@ static int adis16475_config_irq_pin(struct adis1647= 5 *st) u8 polarity; struct spi_device *spi =3D st->adis.spi; - /* - * It is possible to configure the data ready polarity. Furthermore, we - * need to update the adis struct if we want data ready as active low. - */ irq_type =3D irq_get_trigger_type(spi->irq); - if (irq_type =3D=3D IRQ_TYPE_EDGE_RISING) { - polarity =3D 1; - st->adis.irq_flag =3D IRQF_TRIGGER_RISING; - } else if (irq_type =3D=3D IRQ_TYPE_EDGE_FALLING) { - polarity =3D 0; - st->adis.irq_flag =3D IRQF_TRIGGER_FALLING; + + if (st->info->flags & ADIS16475_HAS_FIFO) { + /* + * It is possible to configure the fifo watermark pin polarity. + * Furthermore, we need to update the adis struct if we want the + * watermark pin active low. + */ + if (irq_type =3D=3D IRQ_TYPE_LEVEL_HIGH) { + polarity =3D 1; + st->adis.irq_flag =3D IRQF_TRIGGER_HIGH; + } else if (irq_type =3D=3D IRQ_TYPE_LEVEL_LOW) { + polarity =3D 0; + st->adis.irq_flag =3D IRQF_TRIGGER_LOW; + } else { + dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", + irq_type); + return -EINVAL; + } + + /* Configure the watermark pin polarity. */ + ret =3D adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, + ADIS16575_WM_POL_MASK, (u16)ADIS16575_WM_POL(polarity)); + if (ret) + return ret; + + /* Enable watermark interrupt pin. */ + ret =3D adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, + ADIS16575_WM_EN_MASK, (u16)ADIS16575_WM_EN(1)); + if (ret) + return ret; + } else { - dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", - irq_type); - return -EINVAL; - } + /* + * It is possible to configure the data ready polarity. Furthermore, we + * need to update the adis struct if we want data ready as active low. + */ + if (irq_type =3D=3D IRQ_TYPE_EDGE_RISING) { + polarity =3D 1; + st->adis.irq_flag =3D IRQF_TRIGGER_RISING; + } else if (irq_type =3D=3D IRQ_TYPE_EDGE_FALLING) { + polarity =3D 0; + st->adis.irq_flag =3D IRQF_TRIGGER_FALLING; + } else { + dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", + irq_type); + return -EINVAL; + } - val =3D ADIS16475_MSG_CTRL_DR_POL(polarity); - ret =3D __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, - ADIS16475_MSG_CTRL_DR_POL_MASK, val); - if (ret) - return ret; - /* - * There is a delay writing to any bits written to the MSC_CTRL - * register. It should not be bigger than 200us, so 250 should be more - * than enough! - */ - usleep_range(250, 260); + val =3D ADIS16475_MSG_CTRL_DR_POL(polarity); + ret =3D __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16475_MSG_CTRL_DR_POL_MASK, val); + if (ret) + return ret; + /* + * There is a delay writing to any bits written to the MSC_CTRL + * register. It should not be bigger than 200us, so 250 should be more + * than enough! + */ + usleep_range(250, 260); + } return 0; } @@ -1499,7 +1960,10 @@ static int adis16475_probe(struct spi_device *spi) indio_dev->name =3D st->info->name; indio_dev->channels =3D st->info->channels; indio_dev->num_channels =3D st->info->num_channels; - indio_dev->info =3D &adis16475_info; + if (st->info->flags & ADIS16475_HAS_FIFO) + indio_dev->info =3D &adis16575_info; + else + indio_dev->info =3D &adis16475_info; indio_dev->modes =3D INDIO_DIRECT_MODE; ret =3D __adis_initial_startup(&st->adis); @@ -1514,8 +1978,20 @@ static int adis16475_probe(struct spi_device *spi) if (ret) return ret; - ret =3D devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, - adis16475_trigger_handler); + if (st->info->flags & ADIS16475_HAS_FIFO) { + ret =3D devm_adis_setup_buffer_and_trigger_with_attrs(&st->adis, indio_d= ev, + adis16475_trigger_handler_with_fifo, + &adis16475_buffer_ops, + adis16475_fifo_attributes); + if (ret) + return ret; + /* Update overflow behavior to always overwrite the oldest sample. */ + ret =3D adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, + ADIS16575_OVERFLOW_MASK, (u16)ADIS16575_OVERWRITE_OLDEST); + } else { + ret =3D devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, + adis16475_trigger_handler); + } if (ret) return ret; @@ -1571,6 +2047,18 @@ static const struct of_device_id adis16475_of_match[= ] =3D { .data =3D &adis16475_chip_info[ADIS16507_2] }, { .compatible =3D "adi,adis16507-3", .data =3D &adis16475_chip_info[ADIS16507_3] }, + { .compatible =3D "adi,adis16575-2", + .data =3D &adis16475_chip_info[ADIS16575_2] }, + { .compatible =3D "adi,adis16575-3", + .data =3D &adis16475_chip_info[ADIS16575_3] }, + { .compatible =3D "adi,adis16576-2", + .data =3D &adis16475_chip_info[ADIS16576_2] }, + { .compatible =3D "adi,adis16576-3", + .data =3D &adis16475_chip_info[ADIS16576_3] }, + { .compatible =3D "adi,adis16577-2", + .data =3D &adis16475_chip_info[ADIS16577_2] }, + { .compatible =3D "adi,adis16577-3", + .data =3D &adis16475_chip_info[ADIS16577_3] }, { }, }; MODULE_DEVICE_TABLE(of, adis16475_of_match); @@ -1597,6 +2085,12 @@ static const struct spi_device_id adis16475_ids[] = =3D { { "adis16507-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_1] }, { "adis16507-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_2] }, { "adis16507-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_3] }, + { "adis16575-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_2] }, + { "adis16575-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_3] }, + { "adis16576-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_2] }, + { "adis16576-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_3] }, + { "adis16577-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_2] }, + { "adis16577-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_3] }, { } }; MODULE_DEVICE_TABLE(spi, adis16475_ids); -- 2.34.1