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Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- .../bindings/reset/nxp,imx8ulp-sim-reset.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim= -reset.yaml diff --git a/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.= yaml b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.yaml new file mode 100644 index 000000000000..ec9a5c73e83c --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-sim-reset.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nxp,imx8ulp-sim-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP System Integration Module Reset Controller + +maintainers: + - Liu Ying + +description: | + Some instances of i.MX8ULP's SIM may offer control over the + reset of some components of a certain domain (e.g: AVD-SIM). + As far as the DT is concerned, this means that the reset + controller needs to be a child of the SIM node. + +properties: + compatible: + const: nxp,imx8ulp-avd-sim-reset + + '#reset-cells': + const: 1 + +required: + - compatible + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible =3D "nxp,imx8ulp-avd-sim", "syscon"; + reg =3D <0x2da50000 0x38>; + clocks =3D <&pcc5 IMX8ULP_CLK_AVD_SIM>; + + reset-controller { + compatible =3D "nxp,imx8ulp-avd-sim-reset"; + #reset-cells =3D <1>; + }; + }; --=20 2.34.1 From nobody Tue Feb 10 23:52:57 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 892E11586C0; Thu, 16 May 2024 20:41:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715892094; cv=none; b=RJVIkPjNkt60LFvECAGCtdLu/1f+6crCJRnTNXhoWYr/wpXoyPLWCrRLgUXscsOkRBWtXgtEMOgdViDRGtFb8O+OZyNzah1aMI0sR4CoMR6mzh8ck/eIcVhEioVx3HSk7Yoe7MuUNlZECIWHFeH1Y7aTgIIPEsuXRSqNsa8sQKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715892094; c=relaxed/simple; bh=Fm8UmZPGCcL7w4efTvhgE4GkAB+5OARyNMPff6mb6Yo=; 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charset="utf-8" From: Laurentiu Mihalcea Certain components can be reset via the SIM module. Add reset controller driver for the SIM module to allow drivers for said components to control the reset signal(s). Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-imx8ulp-sim.c | 98 +++++++++++++++++++ include/dt-bindings/reset/imx8ulp-sim-reset.h | 16 +++ 4 files changed, 122 insertions(+) create mode 100644 drivers/reset/reset-imx8ulp-sim.c create mode 100644 include/dt-bindings/reset/imx8ulp-sim-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 85b27c42cf65..c1f4d9ebd0fd 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -91,6 +91,13 @@ config RESET_IMX7 help This enables the reset controller driver for i.MX7 SoCs. =20 +config RESET_IMX8ULP_SIM + tristate "i.MX8ULP SIM Reset Driver" + depends on ARCH_MXC + help + This enables the SIM (System Integration Module) reset driver + for the i.MX8ULP SoC. + config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index fd8b49fa46fc..f257d6a41f1e 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -42,3 +42,4 @@ obj-$(CONFIG_RESET_UNIPHIER) +=3D reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) +=3D reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) +=3D reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) +=3D reset-zynqmp.o +obj-$(CONFIG_RESET_IMX8ULP_SIM) +=3D reset-imx8ulp-sim.o diff --git a/drivers/reset/reset-imx8ulp-sim.c b/drivers/reset/reset-imx8ul= p-sim.c new file mode 100644 index 000000000000..27923b9cd454 --- /dev/null +++ b/drivers/reset/reset-imx8ulp-sim.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define AVD_SIM_SYSCTRL0 0x8 + +struct imx8ulp_sim_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const u32 imx8ulp_sim_reset_bits[IMX8ULP_SIM_RESET_NUM] =3D { + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N] =3D BIT(3), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N] =3D BIT(4), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N] =3D BIT(5), +}; + +static inline struct imx8ulp_sim_reset * +to_imx8ulp_sim_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct imx8ulp_sim_reset, rcdev); +} + +static int imx8ulp_sim_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr =3D to_imx8ulp_sim_reset(rcdev); + const u32 bit =3D imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, 0); +} + +static int imx8ulp_sim_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr =3D to_imx8ulp_sim_reset(rcdev); + const u32 bit =3D imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, bit); +} + +static const struct reset_control_ops imx8ulp_sim_reset_ops =3D { + .assert =3D imx8ulp_sim_reset_assert, + .deassert =3D imx8ulp_sim_reset_deassert, +}; + +static const struct of_device_id imx8ulp_sim_reset_dt_ids[] =3D { + { .compatible =3D "nxp,imx8ulp-avd-sim-reset", }, + { /* sentinel */ }, +}; + +static int imx8ulp_sim_reset_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct imx8ulp_sim_reset *simr; + int ret; + + simr =3D devm_kzalloc(dev, sizeof(*simr), GFP_KERNEL); + if (!simr) + return -ENOMEM; + + simr->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(simr->regmap)) { + ret =3D PTR_ERR(simr->regmap); + dev_err(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + simr->rcdev.owner =3D THIS_MODULE; + simr->rcdev.nr_resets =3D IMX8ULP_SIM_RESET_NUM; + simr->rcdev.ops =3D &imx8ulp_sim_reset_ops; + simr->rcdev.of_node =3D dev->of_node; + + return devm_reset_controller_register(dev, &simr->rcdev); +} + +static struct platform_driver imx8ulp_sim_reset_driver =3D { + .probe =3D imx8ulp_sim_reset_probe, + .driver =3D { + .name =3D KBUILD_MODNAME, + .of_match_table =3D imx8ulp_sim_reset_dt_ids, + }, +}; +module_platform_driver(imx8ulp_sim_reset_driver); + +MODULE_AUTHOR("Liu Ying "); +MODULE_DESCRIPTION("NXP i.MX8ULP System Integration Module Reset driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/reset/imx8ulp-sim-reset.h b/include/dt-bin= dings/reset/imx8ulp-sim-reset.h new file mode 100644 index 000000000000..a3cee0d60773 --- /dev/null +++ b/include/dt-bindings/reset/imx8ulp-sim-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ + +/* + * Copyright 2024 NXP + */ + +#ifndef DT_BINDINGS_RESET_IMX8ULP_SIM_RESET_H +#define DT_BINDINGS_RESET_IMX8ULP_SIM_RESET_H + +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N 0 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N 1 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N 2 + +#define IMX8ULP_SIM_RESET_NUM 3 + +#endif /* DT_BINDINGS_RESET_IMX8ULP_SIM_RESET_H */ --=20 2.34.1 From nobody Tue Feb 10 23:52:57 2026 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFC84157E6B; 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charset="utf-8" From: Laurentiu Mihalcea Add schema for i.MX8ULP's SIM. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- .../bindings/mfd/nxp,imx8ulp-sim.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.y= aml diff --git a/Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml b/D= ocumentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml new file mode 100644 index 000000000000..fbb17c06e3c0 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nxp,imx8ulp-sim.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nxp,imx8ulp-sim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP System Integration Module + +maintainers: + - Liu Ying + +description: | + 8ULP's SIM provides control and configuration options for + some of the chip's components. + +properties: + compatible: + items: + - enum: + - nxp,imx8ulp-avd-sim + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + mux-controller: + $ref: ../mux/reg-mux.yaml + + reset-controller: + $ref: ../reset/nxp,imx8ulp-sim-reset.yaml + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: nxp,imx8ulp-avd-sim + then: + required: + - reset-controller + - mux-controller + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible =3D "nxp,imx8ulp-avd-sim", "syscon"; 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Thu, 16 May 2024 13:41:34 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer Cc: laurentiu.mihalcea@nxp.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: imx8ulp: add AVD-SIM node Date: Thu, 16 May 2024 23:40:31 +0300 Message-Id: <20240516204031.171920-5-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240516204031.171920-1-laurentiumihalcea111@gmail.com> References: <20240516204031.171920-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Add node for imx8ulp's AVD-SIM. This also includes its children. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index c4a0082f30d3..5135d98dc6f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -520,6 +520,23 @@ per_bridge5: bus@2d800000 { #size-cells =3D <1>; ranges; =20 + avd_sim: syscon@2da50000 { + compatible =3D "nxp,imx8ulp-avd-sim", "syscon"; + reg =3D <0x2da50000 0x38>; + clocks =3D <&pcc5 IMX8ULP_CLK_AVD_SIM>; + + mux: mux-controller { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x8 0x00000200>; + }; + + avd_sim_rst: reset-controller { + compatible =3D "nxp,imx8ulp-avd-sim-reset"; + #reset-cells =3D <1>; + }; + }; + cgc2: clock-controller@2da60000 { compatible =3D "fsl,imx8ulp-cgc2"; reg =3D <0x2da60000 0x10000>; --=20 2.34.1