From nobody Wed Feb 11 04:26:25 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41C0A17EBAE; Tue, 14 May 2024 15:24:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715700257; cv=none; b=Y/jt9s85uASQJAkxHpQ53ZI8l3WBrYgXgAL62C5mUqetSOALR5TNvxQfdRoJ1KpFjIhT/0habCGxDH5x8CqGla1MvdooLhpHWyWiTOlCANWNdUqoE0hIJ54sOb4Zzo7RDvWVm+0h1WPMrCRNVj+5ToFoNxgPB39i3Hsg70WDCg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715700257; c=relaxed/simple; bh=PA/IrvxvIM1ep8+7B89JcUeTkpU1YjsSPqMoeUWmhXE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pRpdWqXxNFcsM1enGIywV2J8wo3t+dDbxWz2nrqm1tkB9Z7PR50KpMtxSnsJqNP6bEJRKZSBvrRQhxAohBnMBCtyHimd96x0LpPmqW/RpP7b8sOviS9d5d32ys/UicMZ0UzV8vHEZeHP+vp1cohxdZeP/mysqbj5YBGNk0YmQcM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=FTBoB/7u; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="FTBoB/7u" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1715700254; bh=PA/IrvxvIM1ep8+7B89JcUeTkpU1YjsSPqMoeUWmhXE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FTBoB/7uotXXUuwJ8K2YfoYtA/rDvdjmDaQQEPVWDdXWA202pbtg8J7SPXQoW3ufN UaQMlPxpioSSIfoX90k0nPA377XM0GYLVHL/atltBTMSY33pYN64CCHQQW2my9agS7 k/on0z/UGaaQs0akuOubpl1+KtZ0ciLAtOcDl+vC+Hyi4BtJpRN89jDlNUrO7rnnWK cv7xupPLy+51AxvvlgSE/2fR+O/+lO4g/0ed1R8e9SxfRo6db8xh+lYlmgiZ1dkIEb DhQ9mtc51bNAsvyVAR5SrC1jJpcitZuhfkPgAdQdHPBPYBZlL4v17cAt9ZzhixLReG S7lwSTHqRC0EA== Received: from arisu.hitronhub.home (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madrid.collaboradmins.com (Postfix) with ESMTPSA id ED28B3782191; Tue, 14 May 2024 15:24:10 +0000 (UTC) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Dragan Simic , Chris Morgan , Diederik de Haas , Boris Brezillon , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Detlev Casanova Subject: [PATCH 1/3] drm/rockchip: vop2: Add clock resets support Date: Tue, 14 May 2024 11:19:45 -0400 Message-ID: <20240514152328.21415-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240514152328.21415-1-detlev.casanova@collabora.com> References: <20240514152328.21415-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the end of initialization, each VP clock needs to be reset before they can be used. Failing to do so can put the VOP in an undefined state where the generated HDMI signal is either lost or not matching the selected mode. Signed-off-by: Detlev Casanova --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index fdd768bbd487c..e81a67161d29a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #include @@ -157,6 +158,7 @@ struct vop2_win { struct vop2_video_port { struct drm_crtc crtc; struct vop2 *vop2; + struct reset_control *dclk_rst; struct clk *dclk; unsigned int id; const struct vop2_video_port_data *data; @@ -1915,6 +1917,26 @@ static int us_to_vertical_line(struct drm_display_mo= de *mode, int us) return us * mode->clock / mode->htotal / 1000; } =20 +static int vop2_clk_reset(struct vop2_video_port *vp) +{ + struct reset_control *rstc =3D vp->dclk_rst; + struct vop2 *vop2 =3D vp->vop2; + int ret; + + if (!rstc) + return 0; + + ret =3D reset_control_assert(rstc); + if (ret < 0) + drm_warn(vop2->drm, "failed to assert reset\n"); + udelay(10); + ret =3D reset_control_deassert(rstc); + if (ret < 0) + drm_warn(vop2->drm, "failed to deassert reset\n"); + + return ret; +} + static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -2055,6 +2077,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, =20 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); =20 + vop2_clk_reset(vp); + drm_crtc_vblank_on(crtc); =20 vop2_unlock(vop2); @@ -2706,6 +2730,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) vp->data =3D vp_data; =20 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); + vp->dclk_rst =3D devm_reset_control_get_optional(vop2->dev, dclk_name); + if (IS_ERR(vp->dclk_rst)) { + drm_err(vop2->drm, "failed to get %s reset\n", dclk_name); + return PTR_ERR(vp->dclk_rst); + } + vp->dclk =3D devm_clk_get(vop2->dev, dclk_name); if (IS_ERR(vp->dclk)) { drm_err(vop2->drm, "failed to get %s\n", dclk_name); --=20 2.43.2