From nobody Fri Dec 19 20:55:27 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F8D13B284; Tue, 14 May 2024 11:31:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715686317; cv=none; b=NwMqg53kGOlOIlZ3FjpqqzwOUV1GvyV3wDaIDlSb2wuM1YRALr9PjkoF/6RQImTOH2626mpVuDHNRU8OgWL5bo+ZmciJw0zXVFCWcArbU1lU3bwNGo3h5NepbY8oANoU6T0WDFoGVfo9noCC0Ao9nD/6Bx/NwlYl4UUmPLPFzQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715686317; c=relaxed/simple; bh=ycAlJAFDIexTuV0gkyQkoIj4+wwZGM3l2xmJQx719nA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=oblPtPhKzYBSD1xVUZUqCH8D/Lyyj/yY0GbxkNlWpL3eeeh6KsOKcoDM4GKYswBVipNaF2zeoAiwSWavTQV5AFOSbpIc765cEZLZny+EVUGYmY5n0pzIItGgksp72e29pCjXmclyr1voZJtVO/bqA+eIUS22w2U7VcXI8ozNCzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RENJ3nSk; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RENJ3nSk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715686317; x=1747222317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ycAlJAFDIexTuV0gkyQkoIj4+wwZGM3l2xmJQx719nA=; b=RENJ3nSk5ZCiRQAg/jdkzLriqAqmUOjPxZuak749764EPvwzhf5tb0FO 0Z5zFUE8FWBGsZTyzIY8HkmvSNXS7VvD8yB20aDS3vOSLGymptaKBg+Ar IX0BnmeYTCWIRGm26+7UHcUydWlz+Zp3YoGs+mXo79+UFbJ/o3uIYLzci pWO2WWXJHzbNjUgMjP/5fT1Ez0FgUFr+iGAOKaEntWhIwrWIVf7qYIkTp uPUcdR1V8aQQVmcRo+YRhv7GdqbWgOsuKtZCCGDBT8V+mtU/5Aq0/eCVS CpB0LO08KckNkuIujVnmAU4u/nTgNmnq7TdxeQjX+R+0SMH93km9BkdPO Q==; X-CSE-ConnectionGUID: KNZgCWAySDaOCP6PHflmmw== X-CSE-MsgGUID: ZZvcn7yyQ7aUC64OGn2NuQ== X-IronPort-AV: E=McAfee;i="6600,9927,11072"; a="29152266" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="29152266" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 04:31:56 -0700 X-CSE-ConnectionGUID: Dbq15eO4TPmBIv3TodE8zw== X-CSE-MsgGUID: CfNksod0RFCPkXF33zJD+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="35367366" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.94]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 04:31:54 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Mahesh J Salgaonkar , Oliver O'Halloran , Lukas Wunner , linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v5 5/7] PCI: Store # of supported End-End TLP Prefixes Date: Tue, 14 May 2024 14:31:07 +0300 Message-Id: <20240514113109.6690-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240514113109.6690-1-ilpo.jarvinen@linux.intel.com> References: <20240514113109.6690-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable eetlp_prefix_path in the struct pci_dev tells if End-End TLP Prefixes are supported by the path or not, the value is only calculated if CONFIG_PCI_PASID is set. The Max End-End TLP Prefixes field in the Device Capabilities Register 2 also tells how many (1-4) End-End TLP Prefixes are supported (PCIe r6 sec 7.5.3.15). The number of supported End-End Prefixes is useful for reading correct number of DWORDs from TLP Prefix Log register in AER capability (PCIe r6 sec 7.8.4.12). Replace eetlp_prefix_path with eetlp_prefix_max and determine the number of supported End-End Prefixes regardless of CONFIG_PCI_PASID so that an upcoming commit generalizing TLP Prefix Log register reading does not have to read extra DWORDs for End-End Prefixes that never will be there. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/ats.c | 2 +- drivers/pci/probe.c | 14 +++++++++----- include/linux/pci.h | 2 +- include/uapi/linux/pci_regs.h | 1 + 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index c570892b2090..e13433dcfc82 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -377,7 +377,7 @@ int pci_enable_pasid(struct pci_dev *pdev, int features) if (WARN_ON(pdev->pasid_enabled)) return -EBUSY; =20 - if (!pdev->eetlp_prefix_path && !pdev->pasid_no_tlp) + if (!pdev->eetlp_prefix_max && !pdev->pasid_no_tlp) return -EINVAL; =20 if (!pasid) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 1325fbae2f28..02035b005a53 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2211,8 +2211,8 @@ static void pci_configure_relaxed_ordering(struct pci= _dev *dev) =20 static void pci_configure_eetlp_prefix(struct pci_dev *dev) { -#ifdef CONFIG_PCI_PASID struct pci_dev *bridge; + unsigned int eetlp_max; int pcie_type; u32 cap; =20 @@ -2224,15 +2224,19 @@ static void pci_configure_eetlp_prefix(struct pci_d= ev *dev) return; =20 pcie_type =3D pci_pcie_type(dev); + + eetlp_max =3D FIELD_GET(PCI_EXP_DEVCAP2_EE_PREFIX_MAX, cap); + /* 00b means 4 */ + eetlp_max =3D eetlp_max ?: 4; + if (pcie_type =3D=3D PCI_EXP_TYPE_ROOT_PORT || pcie_type =3D=3D PCI_EXP_TYPE_RC_END) - dev->eetlp_prefix_path =3D 1; + dev->eetlp_prefix_max =3D eetlp_max; else { bridge =3D pci_upstream_bridge(dev); - if (bridge && bridge->eetlp_prefix_path) - dev->eetlp_prefix_path =3D 1; + if (bridge && bridge->eetlp_prefix_max) + dev->eetlp_prefix_max =3D eetlp_max; } -#endif } =20 static void pci_configure_serr(struct pci_dev *dev) diff --git a/include/linux/pci.h b/include/linux/pci.h index 16493426a04f..29c51325b1d9 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -397,7 +397,7 @@ struct pci_dev { supported from root to here */ #endif unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ - unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ + unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=3Dno= t supported */ =20 pci_channel_state_t error_state; /* Current connectivity state */ struct device dev; /* Generic device interface */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a39193213ff2..09e0c300c952 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -661,6 +661,7 @@ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ +#define PCI_EXP_DEVCAP2_EE_PREFIX_MAX 0x00c00000 /* Max End-End TLP Prefi= xes */ #define PCI_EXP_DEVCTL2 0x28 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disab= le */ --=20 2.39.2