From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6A761292E6 for ; Thu, 9 May 2024 22:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294261; cv=none; b=Qw4d80P9w1kyK2wnYyOwG+5WOYoEBulz3bOA6wqN3Kk39SDSETeDzOsbEZqOGc/pWgyy3rcpRVsUg/djE5neapTHppJvT5ZcRLeT27jpIDt4qnvwFLOn16itvp7MxCcpgswjMel8sGyeCRj/tEd3zz3dE9PD8q7YDgilkaUG2WM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294261; c=relaxed/simple; bh=vRxiLvTGirbB6HN43H6Eoei1WmxE/UqWmb9+hJ19B+U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iyu6oXxeF0Dz1QyjM1DfIHRz+C8+ZPvko4Np9OmVSC009O/uSMp4o1mF+dwAGKiALm06TcEsG8B1cgCgkj8K2cChfgUoeKpwhLW95XXMonRAIn2L0vl3mv9X3RfQaWdcN9ZsUf+ioqaRw37UL6k9FAoGGqoHl1LkRmNm/AEtN0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=yM5bU7Mh; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yM5bU7Mh" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-5210684cee6so1519097e87.0 for ; Thu, 09 May 2024 15:37:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294257; x=1715899057; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wy0dt4C+2st62hdh4kql6KATuv+sQnVh0BPdtj9s5/U=; b=yM5bU7MhbiMtMsIRQrG7p2MuzvC8lVc8DJNR7ijZhpWQc2FSX7diTSReH/BybWtzy5 2Ayh9lEoWrpRLOIN6EarQ3j9p5nyQeOwpxz/s0GlBEvwfLib4wqjLMC42B22AlSjseU+ a7iFvYTsSOM7Mj8w1E+CijhGWyzidrQlSyj5UHOP++uLxxVsGUboiUpzqz/RnvxW5Yz7 FZpuHz77sQrLjjto6NCqzjcoGsNTIbld3VZ+MmTOyhQ4NUEjvUlZ3v94ToAakRoOvZq0 6NYqeRc76MT/IuqmsRz6VjQGnwaD1PUH26Wxeb1uBd13I8ijx04C6Fio3YdarBsXUH5V RefQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294257; x=1715899057; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wy0dt4C+2st62hdh4kql6KATuv+sQnVh0BPdtj9s5/U=; b=QvXgtTEBugPMg8y/sjqdaP1j3JJbS1Nhi4mBm7NwzE1mkOxcpdE++pZ90WMRUnojOJ D3zLC4kBhs5e7AJk8ouFcEx1YZ4UeHKnEgdTWuaDHbOptsFrABA0uSqh2kWNwbMG89oz FK0o/lJQNx7RrvwTG4fVEJUL/SfbqRhXfZTm2JtZMWXqFwxaklmvcYXaUHkes2/NGmwK vFW0VABfd3/jghGuU9NCSFqBj17qf9H3OAZMci6RVm0B1Td+wVpBZVfpcxkA0Lozsl8s Nwt64WgKKnP6JPR1l8dqPrgkDhZ1dHAaaAmwqKtIEGzdppZU/DRwwtNm6esedd7JJvzL 0Xmg== X-Forwarded-Encrypted: i=1; AJvYcCWLZ8jhcSTL7gpNNLwzsFwvN8aRpLmMsF4xRIEE50YnJvJuXFo7Xx/kydsK+QRCGyQpwQhUoTwVcTtzPYUpGE3GdUN1Ijo0AqtH7KI3 X-Gm-Message-State: AOJu0YyXqHdshGT7UFMox6GBjtQPdJ7viuWhcaEfGYSQPCfn43x1UcVH JfPdygARJGpuJ4mJLDCS0Z12pMdAxFLkPVlNmmTLBWZB+p/5V4jWH2PRC19J/nE= X-Google-Smtp-Source: AGHT+IFFYEts9ZdAyO7Nds0YpCPtjBBhbL4QPT1Cngkc5NgAxY7Yoqv1tCL+scNEb/egzkHvDimwRw== X-Received: by 2002:a19:6449:0:b0:51d:8756:33f3 with SMTP id 2adb3069b0e04-5220fc6d46bmr467761e87.32.1715294256979; Thu, 09 May 2024 15:37:36 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:36 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:34 +0300 Subject: [PATCH RFC 1/7] drm/mipi-dsi: wrap more functions for streamline handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-1-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9046; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=vRxiLvTGirbB6HN43H6Eoei1WmxE/UqWmb9+hJ19B+U=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmPVAuK86GU8+ebU/1bVmiEBTyjZ+Bg5j7tOlty DaCkxLKzTGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj1QLgAKCRCLPIo+Aiko 1YWoB/9zqwhRLAqs5SU32GE/oZfJ/4r5Ewh0B+3p+KKiFO/MoILG5QBiSBlw09fRoyjCcKxKOqk v3SifezXPjC9mSGKE3owHb9fVL2GmsOEVct669hYocAXHvZMkwM3PCqBpm6HmMA9zPyAIZNu5lQ ipuTJt0YczcR4Xe/cHHqGtj6iRXM56SxsVYpmRi4IdvzLIfSRAePrgScU4g9D0Qrr/mNqI08bil 1KvLUlaMIa6vo776VEoCbgMX+BtWIZEZhkF86mTPNt/aSQn8tlcZeWvVs/4mRmkuEo1fMDb9qNG KNr6AuQ264YR/sq9E4pl/8hx7G7QO3MlqN3dtZqeKhFsyUQ/ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow the pattern of mipi_dsi_dcs_*_multi() and wrap several existing MIPI DSI functions to use the context for processing. This simplifies and streamlines driver code to use simpler code pattern. Note, msleep function is also wrapped in this way as it is frequently called inbetween other mipi_dsi_dcs_*() functions. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/drm_mipi_dsi.c | 209 +++++++++++++++++++++++++++++++++++++= ++++ include/drm/drm_mipi_dsi.h | 19 ++++ 2 files changed, 228 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index d2957cb692d3..4e5e7ad10b7e 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -1429,6 +1429,215 @@ int mipi_dsi_dcs_get_display_brightness_large(struc= t mipi_dsi_device *dsi, } EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness_large); =20 +/** + * mipi_dsi_picture_parameter_set_multi() - transmit the DSC PPS to the pe= ripheral + * @ctx: Context for multiple DSI transactions + * @pps: VESA DSC 1.1 Picture Parameter Set + * + * Like mipi_dsi_picture_parameter_set() but deals with errors in a way th= at + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_picture_parameter_set_multi(struct mipi_dsi_multi_context *c= tx, + const struct drm_dsc_picture_parameter_set *pps) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_picture_parameter_set(dsi, pps); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending PPS failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_picture_parameter_set_multi); + +/** + * mipi_dsi_compression_mode_ext() - enable/disable DSC on the peripheral + * @ctx: Context for multiple DSI transactions + * @enable: Whether to enable or disable the DSC + * @algo: Selected compression algorithm + * @pps_selector: Select PPS from the table of pre-stored or uploaded PPS = entries + * + * Like mipi_dsi_compression_mode_ext_multi() but deals with errors in a w= ay that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_compression_mode_ext_multi(struct mipi_dsi_multi_context *ct= x, + bool enable, + enum mipi_dsi_compression_algo algo, + unsigned int pps_selector) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_compression_mode_ext(dsi, enable, algo, pps_selector); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending COMPRESSION_MODE failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_compression_mode_ext_multi); + +/** + * mipi_dsi_dcs_nop_multi() - send DCS NOP packet + * @ctx: Context for multiple DSI transactions + * + * Like mipi_dsi_dcs_nop() but deals with errors in a way that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_dcs_nop_multi(struct mipi_dsi_multi_context *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_dcs_nop(dsi); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending DCS NOP failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_dcs_nop_multi); + +/** + * mipi_dsi_dcs_enter_sleep_mode_multi() - send DCS ENTER_SLEEP_MODE pack= et + * @ctx: Context for multiple DSI transactions + * + * Like mipi_dsi_dcs_enter_sleep_mode() but deals with errors in a way that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_dcs_enter_sleep_mode_multi(struct mipi_dsi_multi_context *ct= x) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending DCS ENTER_SLEEP_MODE failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_dcs_enter_sleep_mode_multi); + +/** + * mipi_dsi_dcs_exit_sleep_mode_multi() - send DCS EXIT_SLEEP_MODE packet + * @ctx: Context for multiple DSI transactions + * + * Like mipi_dsi_dcs_exit_sleep_mode() but deals with errors in a way that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_dcs_exit_sleep_mode_multi(struct mipi_dsi_multi_context *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending DCS EXIT_SLEEP_MODE failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_dcs_exit_sleep_mode_multi); + +/** + * mipi_dsi_dcs_set_display_off_multi() - send DCS SET_DISPLAY_OFF packet + * @ctx: Context for multiple DSI transactions + * + * Like mipi_dsi_dcs_set_display_off() but deals with errors in a way that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_dcs_set_display_off_multi(struct mipi_dsi_multi_context *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending DCS SET_DISPLAY_OFF failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_off_multi); + +/** + * mipi_dsi_dcs_set_display_on_multi() - send DCS SET_DISPLAY_ON packet + * @ctx: Context for multiple DSI transactions + * + * Like mipi_dsi_dcs_set_display_on() but deals with errors in a way that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_dcs_set_display_on_multi(struct mipi_dsi_multi_context *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending DCS SET_DISPLAY_ON failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_on_multi); + +/** + * mipi_dsi_dcs_set_tear_on_multi() - send DCS SET_TEAR_ON packet + * @ctx: Context for multiple DSI transactions + * + * Like mipi_dsi_dcs_set_tear_on() but deals with errors in a way that + * makes it convenient to make several calls in a row. + */ +void mipi_dsi_dcs_set_tear_on_multi(struct mipi_dsi_multi_context *ctx, + enum mipi_dsi_dcs_tear_mode mode) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + ssize_t ret; + + if (ctx->accum_err) + return; + + ret =3D mipi_dsi_dcs_set_tear_on(dsi, mode); + if (ret < 0) { + ctx->accum_err =3D ret; + dev_err(dev, "sending DCS SET_TEAR_ON failed: %d\n", + ctx->accum_err); + } +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_on_multi); + static int mipi_dsi_drv_probe(struct device *dev) { struct mipi_dsi_driver *drv =3D to_mipi_dsi_driver(dev->driver); diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 5e9cad541bd6..b74a89b40f21 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -275,6 +275,13 @@ int mipi_dsi_compression_mode_ext(struct mipi_dsi_devi= ce *dsi, bool enable, int mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi, const struct drm_dsc_picture_parameter_set *pps); =20 +void mipi_dsi_compression_mode_ext_multi(struct mipi_dsi_multi_context *ct= x, + bool enable, + enum mipi_dsi_compression_algo algo, + unsigned int pps_selector); +void mipi_dsi_picture_parameter_set_multi(struct mipi_dsi_multi_context *c= tx, + const struct drm_dsc_picture_parameter_set *pps); + ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *pa= yload, size_t size); int mipi_dsi_generic_write_chatty(struct mipi_dsi_device *dsi, @@ -338,6 +345,18 @@ int mipi_dsi_dcs_set_display_brightness_large(struct m= ipi_dsi_device *dsi, int mipi_dsi_dcs_get_display_brightness_large(struct mipi_dsi_device *dsi, u16 *brightness); =20 +void mipi_dsi_dcs_nop_multi(struct mipi_dsi_multi_context *ctx); +void mipi_dsi_dcs_enter_sleep_mode_multi(struct mipi_dsi_multi_context *ct= x); +void mipi_dsi_dcs_exit_sleep_mode_multi(struct mipi_dsi_multi_context *ctx= ); +void mipi_dsi_dcs_set_display_off_multi(struct mipi_dsi_multi_context *ctx= ); +void mipi_dsi_dcs_set_display_on_multi(struct mipi_dsi_multi_context *ctx); +void mipi_dsi_dcs_set_tear_on_multi(struct mipi_dsi_multi_context *ctx, + enum mipi_dsi_dcs_tear_mode mode); + +#define mipi_dsi_msleep(ctx, delay) \ + if (!ctx.accum_err) \ + msleep(delay) \ + /** * mipi_dsi_generic_write_seq - transmit data using a generic write packet * --=20 2.39.2 From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55DF6129A6B for ; Thu, 9 May 2024 22:37:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294261; cv=none; b=twE6du06OeqoIsX2tnqKHRb63C2j7lsBKjJ8q9gtZczhEDV3Yiks8UepzKZH4pqU4BlerbqkM8N/SEfn5sy8pc4NahHLXO7rnnD61EkmnWG1X+yhIjNfXaM5ozMf9z7p15QSuQcvWiE7A7ILJOFWo5M3GPBzHyKxhO2oW8WmIF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294261; c=relaxed/simple; bh=u3yXba0jhIsz5BJfPsDI7HZ3897wJIDUeZTmdvqZ37g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GyaGqeY2n6eSIQuOCHHN7aUuPPVze3mAGzcErBERn1WddWfprqc7pJ2t2A6zJEL0lCXzGuz2OvaXU86lzVjTc4A/ATBHF8QRYniyWMQ39xzadl4OuMvn6njEJOzorqrVhcQNpQR9Ujr1DBT6La4CA5VO50JqNLd47grDrBHvJyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZtgtPKJk; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZtgtPKJk" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-51f1bf83f06so1572865e87.1 for ; Thu, 09 May 2024 15:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294257; x=1715899057; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=a2fkQEr6eD7CRzENX13yKAuKTWqMq+M/tO0KGCERLKE=; b=ZtgtPKJkL+l6VnIgHgvLgK1UombWpGijMsQvTOwC68AGf0+KP9ikcC2bInlP89Mr0D ZE8//lp+RXlteKVwyZ+vMzuzLmgrmMdl1dXRN6KQ6B5zOH6ht2qBssBYRdhjz3UKvs3k YP1tYVkLbmhfNvWx00AWYniiLmZ6+6A2+tP1l+ZLJ+J/Ym3poGdhimWb0y6kZaScQmaX F3huhhwycoEzjaNexRJ4uIB5Px1TPgZjKUdpZdb1N917BbcAMrk3ZGL5/puiwCk3TbnS ThAF2Qb5osbKXoJLUHtYZmqA55jf/t3iMHBhksv3ZElin2XrBmnqBjTao6jNKXK09ZLv 9KYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294257; x=1715899057; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a2fkQEr6eD7CRzENX13yKAuKTWqMq+M/tO0KGCERLKE=; b=DqyRQDNy6bgCj2+PhZfZ6iPfhLv+gmjULeFLZ5bNOUEce87zF9t8ubTP/I1I/ZaDnc aJEwr0ayBvKnNRvwuMvhH0eKFeqJndb9FqXa88xMmERoTfAktVTKE5E7Ib6F6E7duGaF Ee4OMa8lVwjM1R1v5c03b844etn29DxiV8uu21uVlvNHRm02cMBFHEkZU/dPC6iTb+Kf 7W14jLUXVqdoMk8JXleOQNErm2rI+oy7HlWecrtVDhWhshzGCO9USYbBzAZyNsIx/a/b qyxDuvS7P8XYKBpvTyzy3rjtK71BGlGUws6SGI3bAp2ycXcG56sagZY4yNXro6o1A82F 8W+Q== X-Forwarded-Encrypted: i=1; AJvYcCUQpeIvzYvz5g5cP8LFS/oJWZjNdYJk7BhPtPRvpUCiCT9wbCK9BT3sgOzlpoJTXu1mbt1OiJBzLJhTQqeBa4Ux3lD27d9kTBlImy+d X-Gm-Message-State: AOJu0YxGlGLvz6yQsVtNSlCRcNylukdiaFzGIpcqXo3K0kP8uqFiuFi7 uqYqRnlWKErrXwe9wdVmG7eoA0Lj9iBSXieVyb6dhB0JXVcp7081AOtv4W1bNok= X-Google-Smtp-Source: AGHT+IHIGDQk1/cR1Ijjw8/YhWlQDoNEI2P8frX0ryotsgebdB4Pvl9HL4FG6+YRX/QVkOW+BTjnxg== X-Received: by 2002:ac2:4c55:0:b0:51f:4165:9305 with SMTP id 2adb3069b0e04-5221007016dmr553026e87.55.1715294257577; Thu, 09 May 2024 15:37:37 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:37 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:35 +0300 Subject: [PATCH RFC 2/7] drm/panel: boe-tv101wum-nl6: use wrapped MIPI DCS functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-2-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4789; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=u3yXba0jhIsz5BJfPsDI7HZ3897wJIDUeZTmdvqZ37g=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ5ptgN5k7t8f7LdnPmr5YqjeduNPwsvnmuKdC9e+zb3NZ 5WcIyjUyWjMwsDIxSArpsjiU9AyNWZTctiHHVPrYQaxMoFMYeDiFICJfO9n/18tNMH4xx+D7hW2 jnYVSfl+flaKuZ7/mkJvXLzTJ5aX3BuTfnxzUtYqud67+p/f74st7Tliku+zMWACT7fQ1vtL564 zn33Wuz3SR/TY56Tqre7xZxr+LJ4SlnXO4izLxSU3M9g2Zcdy2D/VnTpTjMl1Pvc9donUcps1tt 1izVNyNDIr+TdsuhYQmNV5qLVRc5qi5hGPGM/39po5nBZs5y8LrKo8VrinwizteQlH8RZRtUjXX 3NSOezuaxhe9WbT36N5dHX4ZqEdc6a7rGxcInu0QKFMYuaTT4Fsp24dXiBqwc/4Y+KW3JUrI2Q+ detb6Mvc+bruaYmCqYuP8bxIKas5P++bNHPsT6gPvvEYAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to simplify driver's init/exit code. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 73 ++++++++--------------= ---- 1 file changed, 21 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/d= rm/panel/panel-boe-tv101wum-nl6.c index aab60cec0603..456c1a5a2110 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -448,22 +448,16 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x13); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3b, 0x03, 0x96, 0x1a, 0x04, 0x04); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(100); + mipi_dsi_msleep(&ctx, 100); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(200); + mipi_dsi_msleep(&ctx, 200); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(100); + mipi_dsi_msleep(&ctx, 100); =20 return 0; }; @@ -893,22 +887,16 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x01); mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3b, 0x03, 0xae, 0x1a, 0x04, 0x04); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(100); + mipi_dsi_msleep(&ctx, 100); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(200); + mipi_dsi_msleep(&ctx, 200); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(100); + mipi_dsi_msleep(&ctx, 100); =20 return 0; }; @@ -1207,10 +1195,8 @@ static int boe_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xb3, 0x08); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x04); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb8, 0x68); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(150); + mipi_dsi_msleep(&ctx, 150); =20 return 0; }; @@ -1222,16 +1208,12 @@ static int auo_kd101n80_45na_init(struct boe_panel = *boe) msleep(24); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(120); + mipi_dsi_msleep(&ctx, 120); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(120); + mipi_dsi_msleep(&ctx, 120); =20 return 0; }; @@ -1283,10 +1265,8 @@ static int auo_b101uan08_3_init(struct boe_panel *bo= e) mipi_dsi_dcs_write_seq_multi(&ctx, 0xe5, 0x4f); mipi_dsi_dcs_write_seq_multi(&ctx, 0xe6, 0x41); mipi_dsi_dcs_write_seq_multi(&ctx, 0xe7, 0x41); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(150); + mipi_dsi_msleep(&ctx, 150); =20 return 0; }; @@ -1385,16 +1365,12 @@ static int starry_qfh032011_53g_init(struct boe_pan= el *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xe1, 0x23); mipi_dsi_dcs_write_seq_multi(&ctx, 0xe2, 0x07); mipi_dsi_dcs_write_seq_multi(&ctx, 0X11); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(120); + mipi_dsi_msleep(&ctx, 120); =20 mipi_dsi_dcs_write_seq_multi(&ctx, 0X29); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(80); + mipi_dsi_msleep(&ctx, 80); =20 return 0; }; @@ -1490,13 +1466,12 @@ static int starry_himax83102_j02_init(struct boe_pa= nel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x4f); mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f); mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); - if (ctx.accum_err) - return ctx.accum_err; =20 - msleep(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); =20 - mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); + mipi_dsi_msleep(&ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&ctx); =20 return ctx.accum_err; }; @@ -1508,20 +1483,14 @@ static inline struct boe_panel *to_boe_panel(struct= drm_panel *panel) =20 static int boe_panel_enter_sleep_mode(struct boe_panel *boe) { - struct mipi_dsi_device *dsi =3D boe->dsi; - int ret; - - dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D boe->dsi }; =20 - ret =3D mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - return ret; + boe->dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; =20 - ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - return ret; + mipi_dsi_dcs_set_display_off_multi(&ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); =20 - return 0; + return ctx.accum_err; } =20 static int boe_panel_disable(struct drm_panel *panel) --=20 2.39.2 From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDEE4129A70 for ; Thu, 9 May 2024 22:37:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294261; cv=none; b=EZ9k5mAFiWCsih5pgfSsgT/XpBL159kupYgruFumGvlv4YLmV+mLrrjnW5/1TJFjw2HBPCi7uWPcVPUoQ/Ilvz8s7gn0zNHQ9lYXxEVJIUOb2SDH7uvRlf9gTiT7MjjZGTqBsLm845D99U47tBZ//d9+j8RhxRXFTLDAGHuacxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294261; c=relaxed/simple; bh=LbXKWqiDtaK+AQ1NXY6dRRGJIa5nbJ3JMjRjO+iNdK4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ex++hIO0zAVrBhMgeMXMnSladie06YyqWuWoCpyu1SqJht5HlFcNVX//2u1Fqhoy0rzSB9mKNaQWhPJ5YfYJ8JMPWRLN4Lh6tGxj21pHHDVQ1c3o0YUMq0Z/d8wLe59w7QyvZ+AFDsgpKZFV0w6qrO97rQBPQDQJx6edfGBJzZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=MziOdwdB; arc=none smtp.client-ip=209.85.208.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MziOdwdB" Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2e43c481b53so18205291fa.2 for ; Thu, 09 May 2024 15:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294258; x=1715899058; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MJY1WdpDYNtMmaPK1COHpoOEPTHjLRXGYqacL5vf5B8=; b=MziOdwdBWQ3YQ1JOZS/BBqkzOq0ai2/CBJmYW4VxHxl36Q6cpk9iWd+vv4Y8QwRV5L DnCE6BR6tU6zLJWm3LQ3ewJldqmATBVMt6JR4A+fDconEd19HV3+cKWeyOuq8lqpFZTr fRhUZWOj2U2VcDY51S33QfGfbkF9xOc93hlWqV/GJP+XkvWbSSATpuUFSwyB1tfj4VUr lIA0H9ry2QLc4EjP02CQxSibPdi+/twcX5Jwg4yXYniOoRdcdsnMyzJpZu4pV+I+AUOn eWLZpWwUCMrSTNTKH29B5lAWAbXqYUTHBtdyayyAHbLbv/hI20tB0dv8rpggqP1LnR1R G6FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294258; x=1715899058; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MJY1WdpDYNtMmaPK1COHpoOEPTHjLRXGYqacL5vf5B8=; b=YkjRwJK62MNqLYC+lun46eK/hgY8aILah8rMGILeH1yv6qAEJUtSe4KxEfabeIBJQs nkv6JhugzSyKldelbkvvovfwJnyvc7DUpXL0yNiqiaZtGsB7wLNICYhvbkCZkzHfpW2r RJyMIJHZl8WBNQ2Esc49xWqy3SBPBOK0wHAkVPyjlvdRzdDh7lEnT5L7X+2DyNsHrXWK e7dzm1OUFVZHy/kIcXrTbbKnnZCUatN0FQmc8hMe0gSVtUpWaCIroze6UpU4irBgdMoE +67hnroDL/zjQXuvfaGfQPV9SEGkAyXao2aWqHf7c1bgp6ROz3RKiGE8Q6DtG1hjiU0O KZMg== X-Forwarded-Encrypted: i=1; AJvYcCVRjT0ctcum5uA/Nr8DmRz97NeLCMzlSrKmvHorOR72AIC+cj75JgRuSv+YxanoTFajqQPkeO9M/mAFF8HUPvjKElC/+XgA1TIaxY7y X-Gm-Message-State: AOJu0YwUJlpe5sFMHgOhLlZHb5YUCpWVv9YWoSw6sEB2vzorOZtktgUG KH/URUYpjt617ps5fUT5A77U0ZPfNarp2Z+vKNBDNZ3WpWoXSBgFxIhcEYX+GjE= X-Google-Smtp-Source: AGHT+IGFTvw1vxx85dKbJll5ZaDg39l0SDuhBFDjN3HTXmrCOzJmUUBmBQXdeARfZ/bdKcDF52kWww== X-Received: by 2002:a05:6512:451:b0:51e:ff32:16a8 with SMTP id 2adb3069b0e04-52210273f01mr460200e87.62.1715294258223; Thu, 09 May 2024 15:37:38 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:37 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:36 +0300 Subject: [PATCH RFC 3/7] drm/panel: ilitek-ili9882t: use wrapped MIPI DCS functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-3-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2005; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=LbXKWqiDtaK+AQ1NXY6dRRGJIa5nbJ3JMjRjO+iNdK4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmPVAuGD8s+0CZnKan0NSsgk22yRkq0bYPJEx4s J4D6SGoo62JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj1QLgAKCRCLPIo+Aiko 1U1QB/9jf6h6hbySFkd5s3YSe7Rk72+e2cx8A9V4vSgxt24eApZJ8tUZarJ3aHGtZ2fr2/pPdLz /Eq6giUUMEAURLyx956TTierWY5J7Ifq9AVSoQDdyxcmMMiXdclrpBzeR/fPA3br+R+xqBoXhHb DAKhaiXm776JWUDqglqM6VoEaH+ciW2ZQG1Wa1jKU92K3EHRzTaDFa3xruoems2yPxoQvy69N+k E7hAEAhb9IF5gVcFYPUWKKyUHsPRB6jIJ2xMeuNX2WkR7G15sr33GQvQLlaSVdAnEm4nMIyBn7h X4myAKi0Qf2VNKhrFKpGwzMDBu9PkLnkloCNcZZaRHBlc2xY X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to simplify driver's init/exit code. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-ilitek-ili9882t.c | 30 +++++++++--------------= ---- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c b/drivers/gpu/dr= m/panel/panel-ilitek-ili9882t.c index 58fc1d799371..e7a74d5443b0 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c @@ -402,19 +402,15 @@ static int starry_ili9882t_init(struct ili9882t *ili) mipi_dsi_dcs_write_seq_multi(&ctx, 0x92, 0x22); =20 ili9882t_switch_page(&ctx, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_EXIT_SLEEP_MODE); - if (ctx.accum_err) - return ctx.accum_err; + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); =20 - msleep(120); + mipi_dsi_msleep(&ctx, 120); =20 - mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_DISPLAY_ON); - if (ctx.accum_err) - return ctx.accum_err; + mipi_dsi_dcs_set_display_on_multi(&ctx); =20 - msleep(20); + mipi_dsi_msleep(&ctx, 20); =20 - return 0; + return ctx.accum_err; }; =20 static inline struct ili9882t *to_ili9882t(struct drm_panel *panel) @@ -424,20 +420,14 @@ static inline struct ili9882t *to_ili9882t(struct drm= _panel *panel) =20 static int ili9882t_enter_sleep_mode(struct ili9882t *ili) { - struct mipi_dsi_device *dsi =3D ili->dsi; - int ret; - - dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D ili->dsi }; =20 - ret =3D mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - return ret; + ili->dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; =20 - ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - return ret; + mipi_dsi_dcs_set_display_off_multi(&ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); =20 - return 0; + return ctx.accum_err; } =20 static int ili9882t_disable(struct drm_panel *panel) --=20 2.39.2 From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90091129E75 for ; Thu, 9 May 2024 22:37:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294262; cv=none; b=YTc0AUgwvzxkFy8/tDJjgmONQKbcwLLeOo2WlrY0/KtL+KeNAR/iQGip0eoZIL6jm22iMjrxvF/VnnOx07m75clsRg5/PhBtN1bdTJLoigz3ri5TObzKo6WTMDybtfgmET0fmORXpvt47bUq995vyKnNEYEtlQ/Nh9th/in8L/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294262; c=relaxed/simple; bh=/ICGqi9rxo6d+dzzW1CgRoe58bcq3pT7pDZm1a8aL8Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IC1acvT9WzKmAPqAU9ifYwaatWQ5QYf6enZyRsSOGa4ujFaAl50EJ1DtwvvTnupDhGi4EgTo0H3a5TWYodUvBl2oSN8MRA8zgn4zDItn/P/HO9nR9l0a3Lly2XuLlbwJseH3jBZ0GVTYcRqsAMuXjIEJs9WmuLuyUtAG2XO3sAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=X2KeVncB; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="X2KeVncB" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-51f2ebbd8a7so1511140e87.2 for ; Thu, 09 May 2024 15:37:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294259; x=1715899059; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XPxTEl/rjN+bSOjCHxAgRV15YEB3RII6eshoI73E95Q=; b=X2KeVncBnVBLj3kn5H4eNM5welccjNpHiilra53EapqDzvRpNL+b/R+EUmTtE7MmAo 6cHE5Pgzeoe48YACgzs3tF5MMnsyuyxhXO/eDo0mY4d2mZex6orVm4Q9hgVxcTK8hkq1 O9LWnjtx4RNZHSmKZp/EkXTgUm+1VB0w/hYpmzwQhYJeXbEexj5HC/JiFf5kvb/wOhai 6cjsUx0tVRS1ewgz1uk5/APzCIxPuQ0p1ErzmWLOPdH+yanlo5lmTV2ja3VKYZlPg2NU eWzHdeEYc+08xTaIu56ioF1fNEJC8qfar9AMdJXl5WGLUfGiTGicFznDS/fSJyjysVJl vukg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294259; x=1715899059; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XPxTEl/rjN+bSOjCHxAgRV15YEB3RII6eshoI73E95Q=; b=u2qnfAJdwe5d8TdY1smRZdhJ/90BJ8IpCTXkmhOryurq6F+Id13PFSavbp3NZUomhg HSOb3+DBuHwVRX9GUYhDyJPblA7EFqOspBqnunVcE+RNqyx+BhNNjccXp1WDjJe1xH0r qxUVzQPS6phSy39ed7wsE1FLSd28BDWuYbxm19R9ahJhTT7RalRu9RsIdhOg7H9NdsqO I485p4Y4SHAEoBlumhLQo+84vR80N3m307DDvg0/M6uDJogyxNOMzXX/g95Ky4+5Vo05 wJ0LUHpvtIkus8a0tLv8AkjCA7L4qyNBsRm3TPDWy/T1UAKzYoZl3fSzWVmy1sOPCG1L pbjg== X-Forwarded-Encrypted: i=1; AJvYcCVFkx5x9ZmsVGSMaxARzVRHoQcAduXIZ6r/TmF8CpKHdglndOAj9fHpaN81J7U2hsdLnjC+VcStKnn0nQXHMCbvvtwnttP98M23QzH2 X-Gm-Message-State: AOJu0Yz1g+rGWwZu+EmrAAjOWffol8qGWuFvWoeYPH5vi+N+3aSrvYpH bmbRiSvYDVw2l9nnYz9j6XxKZXG4X/mpsK6nWn7ObrkYsR7Z9ho61lvpN2Fkpt0= X-Google-Smtp-Source: AGHT+IF3NNf3KZ9S9uBPtp2LgTHFubboDS0GgeBWPRxg1SvUZQS//fedQ5j2Q+2Ujoyni9I7AiK27g== X-Received: by 2002:a05:6512:4012:b0:51a:b933:b297 with SMTP id 2adb3069b0e04-5220fb6983emr569030e87.2.1715294258864; Thu, 09 May 2024 15:37:38 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:38 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:37 +0300 Subject: [PATCH RFC 4/7] drm/panel: innolux-p079zca: use mipi_dsi_dcs_nop_multi() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-4-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1349; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=/ICGqi9rxo6d+dzzW1CgRoe58bcq3pT7pDZm1a8aL8Y=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmPVAv+hJcCRRz/1N4z/5nZnoSCFPmnaflwApji eYhLOpmvgCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj1QLwAKCRCLPIo+Aiko 1QBmB/kBfZNnW8LsfL5YALIrGr1vlDsGY/TMulRiyB3ma/rYpTdqKUWu2IcP/mVYN5f8PoptNqR zmmQx3yamiNeQSO2YVPk8YA99zhDUhm+NFbaDQXYLqgjLyVesZZxyGO4/jB9oWLwMQ97S+WV+SI SNKHeE1Bry/mghLEjJE+r76Br3C019t5P57GDJ5aNZoREBMDi5WpR/4D9TS4ToMTsql0/nLAWMN OtX894c98lOz+uz6VHWIkaDRywhOKJUBIVDyMxSiYkxQOmr3n2aTrGV9/cnbbzUJVprWsCc0aKP LO3pRkNP3pg/29EV/4A+hsP44tCYINaYPPKK0K5vOEemn9NP X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Remove conditional code and use mipi_dsi_dcs_nop_multi() wrapper to simplify driver code. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-innolux-p079zca.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-innolux-p079zca.c b/drivers/gpu/dr= m/panel/panel-innolux-p079zca.c index ade8bf7491ee..0691a27a0daa 100644 --- a/drivers/gpu/drm/panel/panel-innolux-p079zca.c +++ b/drivers/gpu/drm/panel/panel-innolux-p079zca.c @@ -224,21 +224,14 @@ static const struct drm_display_mode innolux_p097pfg_= mode =3D { static void innolux_panel_write_multi(struct mipi_dsi_multi_context *ctx, const void *payload, size_t size) { - struct mipi_dsi_device *dsi =3D ctx->dsi; - struct device *dev =3D &dsi->dev; - mipi_dsi_generic_write_multi(ctx, payload, size); - if (ctx->accum_err) - return; =20 /* * Included by random guessing, because without this * (or at least, some delay), the panel sometimes * didn't appear to pick up the command sequence. */ - ctx->accum_err =3D mipi_dsi_dcs_nop(ctx->dsi); - if (ctx->accum_err) - dev_err(dev, "failed to send DCS nop: %d\n", ctx->accum_err); + mipi_dsi_dcs_nop_multi(ctx); } =20 #define innolux_panel_init_cmd_multi(ctx, seq...) \ --=20 2.39.2 From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C1FE12D210 for ; Thu, 9 May 2024 22:37:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294264; cv=none; b=UJJ/JNW87zO+CIeAysbNiNTs5wf7FQiIs4e+mBbz/nznBuyP80k5K6U2XbfHFB3cNtQfqJcQwUWoWbHkatGk3e9opQJw8bvv/L2npSdV6vWc9lU5gCCCwDMwATJVWiplHaMeRa8YL8CSsrAg3Lz/i9JqZ768TYGMF+HRAWBtjh0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294264; c=relaxed/simple; bh=19zx/qwcigAhIYqmKy1s852n2d4kEuylkHN2kcUSurk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kl45tj1zVIKGS+NV61jFm+0x5fNjPrT3vsj2xrJzczZ66GwVuf04yPe1WBDSm55rutmaC3SQRhb/VLi6lhGhWbcHFjYY8UFcwkd0En21KfX1UD8OL7SIkMkz74e7cU0F0qyyKL4EC8ZqN432eRzh09mVUwiaz6eBJvyn4nmNJc8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=B1sn1Npg; arc=none smtp.client-ip=209.85.167.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="B1sn1Npg" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-52192578b95so1554976e87.2 for ; Thu, 09 May 2024 15:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294259; x=1715899059; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bSx2hn/xWCc6eWMHzVDFgGFEONW2CZf8+nMGEDqucms=; b=B1sn1Npgbi3pOfaMLJUzlh43id31UM2u8r1+9i8Rp3Yytiatna5/1yhLQIGFpf/ET9 b+XMUxpat7cG/MzMfO9A6/S2yo1uCI9ax+d7V4JvPgrTOFwI3cYjIrlG/DIBx/WHEyEy 4/u1opowdRD6GsJQyb8JG/8S2joGRRqKAC/L4NWX4VDEj3QWj6tEIwkmw1sNAN+Vnhai HHwFXJV6CdQhwbBbmTO4bTU+LNNsnXiA7Mxjsm1/hXzdkcIlQYuLxUFEcwa1rZ9qa/b2 KGQQlMSypPjkcTliG1nq+YHttSE4zGZ/hEbvoZIBulRrSjtFsjD3K08+MQjhtKS9l+0R 71Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294259; x=1715899059; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bSx2hn/xWCc6eWMHzVDFgGFEONW2CZf8+nMGEDqucms=; b=gy9Wr2Ovy7bd0V3byQQDyJbyT1/oKsXyYjG5o814yGxhCTDBhMyjgdRXdSF0lugNAj pUYROjCF4paHJeyKUPh85KE0gGxWGUgzVc0ACnKeod/xwrBMJ4kE3wBXrJRq0hcGAFVQ IsL478Nv3VvHK9PvoEF2hWdl7ggZ8X1EvUa8zrPBZYPs/hVc7ZWoJf3T8f2urDTvvI7N 3Jcn2xhdqlFdqMgSPUpXq0rfvkEh5BCShAs5Fq0Mye0lAmUC2JP0lJznim3QECdETp3L plX5w1GAK7Zki9qP0wmf/HefBH/wbp5DE7bmosv90rjij7u28BoMBSMFatBEMnC9LTGl qYGA== X-Forwarded-Encrypted: i=1; AJvYcCWte9mY43U0mzE+WLbSSuYFO+SD60cMPJqbDJbofX0L6kpEKzYW83DLu8JNtx9ReAxTrEfhegRNTCqGG8D08WyxeVWKmnPRNoQg0oTZ X-Gm-Message-State: AOJu0YyPLHlSid3mFuQF3fV1KYHvUEwqCA6+W9gEYl4VATLgVC/Q8BGq Gga15MBsVrULu8YjzXSnmFUjC2PPOb7qfRhGDvpKKmnIP9P8Dr1H78aPMdRPdIE= X-Google-Smtp-Source: AGHT+IHaFY07NKwTgoPNxr7uZPPo4Jm7OXbCMiTW3QKXsq4m5RT/eEUmbcE9lEC+pIqoQCbkEwXBHw== X-Received: by 2002:ac2:424d:0:b0:521:b2b5:60ea with SMTP id 2adb3069b0e04-5220fb6b131mr444931e87.23.1715294259550; Thu, 09 May 2024 15:37:39 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:39 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:38 +0300 Subject: [PATCH RFC 5/7] drm/panel: novatek-nt36672e: use wrapped MIPI DCS functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-5-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=33067; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=19zx/qwcigAhIYqmKy1s852n2d4kEuylkHN2kcUSurk=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ5ptgL7mqZat2fFcvY+9xVM9HZbd6z6xN1grf9eOCtPLX H9/5eV0MhqzMDByMciKKbL4FLRMjdmUHPZhx9R6mEGsTCBTGLg4BWAidXns/xO+GSRcF19TGadV n7To6YUFZ1d6/F/+a+7bR+n6nQ6N9/iWfvnNEZuz9flPF2UN2+vVPbs/87danpiY9rieqbAkaHf 6v+IbxwKUPlsKdjevWdbQ97qDbUv8vifs1mIW81m+SqR5n56jqi67ue+2s4fw2/SwRyv9pWR2xm r6RctGPp0UKf5SYKP7Yre0mrM5D0tkucsZawJ4fsYqNdTNtFse9+KtNtOi2DyFek6eqHPt8h2mG WJfXzlcLfmw6J7o3TbWbS2LAjcoiUzj7r+cmMv1NDnG8WJ+5+bMdP0ohW47P9Zb06cyWhn7r2Tb fFCtL/Fiw9Mg/tXX9l3crM8z49r6GTJ7Qg3MtRe+uzkDAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to simplify driver's init/exit code. This also includes passing context to the init_sequence() function instead of passing the DSI device. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-novatek-nt36672e.c | 587 ++++++++++++---------= ---- 1 file changed, 281 insertions(+), 306 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672e.c index 9ce8df455232..f190285d75a1 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c @@ -33,7 +33,7 @@ struct panel_desc { enum mipi_dsi_pixel_format format; unsigned int lanes; const char *panel_name; - int (*init_sequence)(struct mipi_dsi_device *dsi); + void (*init_sequence)(struct mipi_dsi_multi_context *ctx); }; =20 struct nt36672e_panel { @@ -49,297 +49,293 @@ static inline struct nt36672e_panel *to_nt36672e_pane= l(struct drm_panel *panel) return container_of(panel, struct nt36672e_panel, panel); } =20 -static int nt36672e_1080x2408_60hz_init(struct mipi_dsi_device *dsi) +static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ct= x) { - struct mipi_dsi_multi_context ctx =3D { .dsi =3D dsi }; - - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0x= aa, 0x02, + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0xa= a, 0x02, 0x0e, 0x00, 0x2b, 0x00, 0x07, 0x0d, 0xb7, 0x0c, 0xb7); =20 - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc2, 0x1b, 0xa0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x01, 0x66); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x06, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x38); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2f, 0x83); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x69, 0x91); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x95, 0xd1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x96, 0xd1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x64); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf3, 0x54); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf4, 0x64); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf5, 0x54); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf6, 0x64); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf7, 0x54); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf8, 0x64); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf9, 0x54); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x24); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x01, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x03, 0x0c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0x1d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x08, 0x2f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x09, 0x2e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0a, 0x2d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0b, 0x2c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x11, 0x17); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x12, 0x13); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x13, 0x15); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x15, 0x14); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x16, 0x16); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x17, 0x18); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1b, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1d, 0x1d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x20, 0x2f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x21, 0x2e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x22, 0x2d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x23, 0x2c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x29, 0x17); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x13); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x15); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2f, 0x14); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x30, 0x16); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x31, 0x18); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x32, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x34, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x1f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x36, 0x1f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x4d, 0x14); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x4e, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x4f, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x53, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x71, 0x30); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x79, 0x11); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7a, 0x82); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7b, 0x8f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7d, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x80, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x81, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x82, 0x13); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x84, 0x31); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x85, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x86, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x87, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x90, 0x13); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x92, 0x31); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x93, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x94, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x95, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9c, 0xf4); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9d, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa0, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa2, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa3, 0x02); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa4, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa5, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc6, 0xc0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc9, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xd9, 0x80); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x02); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x25); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x18, 0x22); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x19, 0xe4); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x21, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x66, 0xd8); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x68, 0x50); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x69, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6b, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6d, 0x0d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6e, 0x48); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x72, 0x41); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x73, 0x4a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x74, 0xd0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x77, 0x62); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x79, 0x7e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7d, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7e, 0x15); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7f, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x84, 0x4d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xcf, 0x80); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xd6, 0x80); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xd7, 0x80); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xef, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xf0, 0x84); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x26); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x81, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x83, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x84, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x85, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x86, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x87, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x88, 0x05); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8a, 0x1a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8b, 0x11); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8c, 0x24); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8e, 0x42); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8f, 0x11); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x90, 0x11); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x91, 0x11); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9a, 0x80); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9b, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9c, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9d, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x9e, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x27); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x01, 0x68); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x20, 0x81); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x21, 0x6a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x25, 0x81); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x26, 0x94); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6e, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6f, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x70, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x71, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x72, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x75, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x76, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x77, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7d, 0x09); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7e, 0x67); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x80, 0x23); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x82, 0x09); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x83, 0x67); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x88, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x89, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa5, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa6, 0x23); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa7, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb6, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xe5, 0x02); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xe6, 0xd3); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xeb, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xec, 0x28); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x2a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x91); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x03, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x50); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0a, 0x70); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0c, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0d, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0f, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x11, 0xe0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x15, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x16, 0xa4); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x19, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1a, 0x78); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1b, 0x23); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1d, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1e, 0x3e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1f, 0x3e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x20, 0x3e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x28, 0xfd); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x29, 0x12); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0xe1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2d, 0x0a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x30, 0x49); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x33, 0x96); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x34, 0xff); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x36, 0xde); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x37, 0xf9); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x38, 0x45); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x39, 0xd9); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x3a, 0x49); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x4a, 0xf0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7a, 0x09); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7b, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7f, 0xf0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x83, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x84, 0xa4); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x87, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x88, 0x78); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x89, 0x23); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8b, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8c, 0x7d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8d, 0x7d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x8e, 0x7d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x= 49, 0x00, + mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x1b, 0xa0); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x66); + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x40); + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x38); + mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x83); + mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x91); + mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0xd1); + mipi_dsi_dcs_write_seq_multi(ctx, 0x96, 0xd1); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf2, 0x64); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf3, 0x54); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf4, 0x64); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf5, 0x54); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf6, 0x64); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf7, 0x54); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x64); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf9, 0x54); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x24); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x1d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x2f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x2e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x2d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x2c); + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x17); + mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x15); + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x16); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x18); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x1d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x2f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x2e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x2d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x2c); + mipi_dsi_dcs_write_seq_multi(ctx, 0x29, 0x17); + mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0x2b, 0x15); + mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x16); + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x18); + mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x1f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x1f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x4d, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0x4e, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x4f, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x30); + mipi_dsi_dcs_write_seq_multi(ctx, 0x79, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7a, 0x82); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7b, 0x8f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x82, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x31); + mipi_dsi_dcs_write_seq_multi(ctx, 0x85, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x86, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x90, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0x92, 0x31); + mipi_dsi_dcs_write_seq_multi(ctx, 0x93, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x94, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0xf4); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x02); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0xc0); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xd9, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x02); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x25); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0xe4); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x40); + mipi_dsi_dcs_write_seq_multi(ctx, 0x66, 0xd8); + mipi_dsi_dcs_write_seq_multi(ctx, 0x68, 0x50); + mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0x0d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0x48); + mipi_dsi_dcs_write_seq_multi(ctx, 0x72, 0x41); + mipi_dsi_dcs_write_seq_multi(ctx, 0x73, 0x4a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x74, 0xd0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x77, 0x62); + mipi_dsi_dcs_write_seq_multi(ctx, 0x79, 0x7e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x15); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7f, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x4d); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0xd6, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0xd7, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0xef, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x84); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x26); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x85, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x86, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8a, 0x1a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8b, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x24); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x42); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8f, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x90, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x91, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9a, 0x80); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9b, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x9e, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x27); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x68); + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x81); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x6a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x81); + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x94); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6f, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x72, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x75, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x77, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x82, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x40); + mipi_dsi_dcs_write_seq_multi(ctx, 0xe5, 0x02); + mipi_dsi_dcs_write_seq_multi(ctx, 0xe6, 0xd3); + mipi_dsi_dcs_write_seq_multi(ctx, 0xeb, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0xec, 0x28); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2a); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x91); + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x50); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x70); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x40); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xe0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0xa4); + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x78); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1e, 0x3e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1f, 0x3e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x3e); + mipi_dsi_dcs_write_seq_multi(ctx, 0x28, 0xfd); + mipi_dsi_dcs_write_seq_multi(ctx, 0x29, 0x12); + mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0xe1); + mipi_dsi_dcs_write_seq_multi(ctx, 0x2d, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x49); + mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0x96); + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xff); + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x40); + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xde); + mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0xf9); + mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x45); + mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0xd9); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x49); + mipi_dsi_dcs_write_seq_multi(ctx, 0x4a, 0xf0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7a, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7b, 0x40); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7f, 0xf0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0xa4); + mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x78); + mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8b, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x7d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8d, 0x7d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x7d); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x4= 9, 0x00, 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x= 3a, 0x01, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3= a, 0x01, 0x7a, 0x01, 0xa9, 0x01, 0xf2, 0x02, 0x2d, 0x02, 0x2e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0x= ca, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0xc= a, 0x03, 0x00, 0x03, 0x1e, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0x= ab, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xa= b, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x= 51, 0x00, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x5= 1, 0x00, 0x71, 0x00, 0x90, 0x00, 0xa7, 0x00, 0xbf, 0x00, 0xd1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x= 43, 0x01, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x4= 3, 0x01, 0x83, 0x01, 0xb2, 0x01, 0xfa, 0x02, 0x34, 0x02, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0x= d0, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0xd= 0, 0x03, 0x03, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5b, 0x03, 0x6b); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0x= ac, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0xa= c, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x= 51, 0x00, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x5= 1, 0x00, 0x72, 0x00, 0x92, 0x00, 0xa8, 0x00, 0xbf, 0x00, 0xd1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x= 42, 0x01, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x4= 2, 0x01, 0x81, 0x01, 0xaf, 0x01, 0xf5, 0x02, 0x2f, 0x02, 0x31); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0x= cd, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xc= d, 0x03, 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0x= ab, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xa= b, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x21); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x= 49, 0x00, + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x21); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x4= 9, 0x00, 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x= 3a, 0x01, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3= a, 0x01, 0x7a, 0x01, 0xa9, 0x01, 0xf2, 0x02, 0x2d, 0x02, 0x2e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0x= ca, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0xc= a, 0x03, 0x00, 0x03, 0x1e, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0x= ab, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xa= b, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x= 51, 0x00, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x5= 1, 0x00, 0x71, 0x00, 0x90, 0x00, 0xa7, 0x00, 0xbf, 0x00, 0xd1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x= 43, 0x01, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x4= 3, 0x01, 0x83, 0x01, 0xb2, 0x01, 0xfa, 0x02, 0x34, 0x02, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0x= d0, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0xd= 0, 0x03, 0x03, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5b, 0x03, 0x6b); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0x= ac, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0xa= c, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x= 51, 0x00, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x5= 1, 0x00, 0x72, 0x00, 0x92, 0x00, 0xa8, 0x00, 0xbf, 0x00, 0xd1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x= 42, 0x01, + mipi_dsi_dcs_write_seq_multi(ctx, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x4= 2, 0x01, 0x81, 0x01, 0xaf, 0x01, 0xf5, 0x02, 0x2f, 0x02, 0x31); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0x= cd, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xc= d, 0x03, 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0x= ab, 0x03, + mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xa= b, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x2c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x61, 0x1f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x62, 0x1f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7e, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6a, 0x14); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6b, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6c, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6d, 0x36); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x53, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x54, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x56, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x58, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x59, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0xf0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x5a, 0x00); - - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x51, 0xff); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x53, 0x24); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x01); - - return ctx.accum_err; + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x1f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x1f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6a, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6c, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0x36); + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x04); + mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x58, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0x59, 0x0f); + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xf0); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x5a, 0x00); + + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0xff); + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x24); + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x01); } =20 static int nt36672e_power_on(struct nt36672e_panel *ctx) @@ -381,61 +377,40 @@ static int nt36672e_power_off(struct nt36672e_panel *= ctx) return ret; } =20 -static int nt36672e_on(struct nt36672e_panel *ctx) +static int nt36672e_on(struct nt36672e_panel *panel) { - struct mipi_dsi_device *dsi =3D ctx->dsi; - const struct panel_desc *desc =3D ctx->desc; - int ret =3D 0; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D panel->dsi }; + struct mipi_dsi_device *dsi =3D panel->dsi; + const struct panel_desc *desc =3D panel->desc; =20 dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; =20 - if (desc->init_sequence) { - ret =3D desc->init_sequence(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "panel init sequence failed: %d\n", ret); - return ret; - } - } + if (desc->init_sequence) + desc->init_sequence(&ctx); =20 - ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 120); =20 - ret =3D mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "Failed to set display on: %d\n", ret); - return ret; - } - msleep(100); + mipi_dsi_dcs_set_display_on_multi(&ctx); =20 - return 0; + mipi_dsi_msleep(&ctx, 100); + + return ctx.accum_err; } =20 -static int nt36672e_off(struct nt36672e_panel *ctx) +static int nt36672e_off(struct nt36672e_panel *panel) { - struct mipi_dsi_device *dsi =3D ctx->dsi; - int ret =3D 0; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D panel->dsi }; =20 - dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + panel->dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; =20 - ret =3D mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(20); + mipi_dsi_dcs_set_display_off_multi(&ctx); + mipi_dsi_msleep(&ctx, 20); =20 - ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(60); + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 60); =20 - return 0; + return ctx.accum_err; } =20 static int nt36672e_panel_prepare(struct drm_panel *panel) --=20 2.39.2 From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFC6212D753 for ; Thu, 9 May 2024 22:37:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294263; cv=none; b=tONYzMQa56AG4u97cpllE+9eawmUc4h9E3xLW6r3uGBW64D8axsF3cec/JlJv5tUImj9mnHgUTGGKBBOoN+X0iODQGVOoiRq7eOWO6Cv81igAE5WIcQoJFf6MdhRlMinDGXV2e+LutLf+5A5m8caDwoCi9H0xGq/iEkVFG3/dtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294263; c=relaxed/simple; bh=0hHShducaAcMM1humQX/WthNAOeANb5d92F25xx+Ojw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LeF9y2duynxkHQPXsPaqJeS4xL3DxyG1cTj2jcVbOfZ9no3+wI2iLgFg88iw74ga5KJ2prYz6hFf/JmhHkX3yS+PsHL5e4fVgoQ4Cgcv2sNc/ufP+pn2E6vEfWuGpWs64fvynU6YtHAveopjaO4sR2qNc+NxSA4l592CegFXb2k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=YPq6I4ic; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YPq6I4ic" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-5206a5854adso1604246e87.0 for ; Thu, 09 May 2024 15:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294260; x=1715899060; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=t68VnMD7f5eQp0ZMoa1zqW8nBoF/NRoHSPk2XnhQ8lw=; b=YPq6I4icl0cIWSgj3hW7EiLZsv4Npd8VD1ZJGmA1c1n0Ra8PVYko53Q556z6o5tn/2 2KOnFfho/gLJHUO7HnRrV3696x4r6aGRRru8XZo2KwHNYujkoqHguUy5i1AkAWrI9+CY /HMtGxoC5wnsZoDHSmYUTAPia+2X3nIBnYeiiscaHAMJHb+vk3MaBHo60Rs6F6Of3KVU g87VMjQZhV6nAMn215sXrqxsUyvojEqIrA67JvgR9znYKu67ONZQTmNf4DK+DqNHbb4X i+l4WQ/AP5bC5lH5PAe4vhhdhJGjgPsI3AlDT8j6UVlYqV7kFzYO6AkEcGgUGgmXXboo T34g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294260; x=1715899060; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t68VnMD7f5eQp0ZMoa1zqW8nBoF/NRoHSPk2XnhQ8lw=; b=Nu1b7X5AnnMubppiqVnQFd9vsCOGWwvNOO8rf98oYZcT7CkAIUIuFxLkkIKv0sOQHu 1e4bwgSCWnGRlo2xgKnKsNOBd2vNMS91RhaX1l9vdS1yRWM4n/JiJlFZhES+uNbJyjw9 RGC6CUaX+Ck64uWxNnHHBXSio0W1fRRvxP625/R1Rt5CfPsZqkx3riA9UdEX3zlQ2Bf3 sw1Mn8HdkcCaKnMqPjzunSzxBm8mBqOjLZAOFI9eHAbXbUH7DMSwPK9eu3rZTZ/jlfa/ Vd+zuLHRib+TWi25uFe2bhfjreGbG+1i5iBJJ3GsjEDkWy1lqduEMCm/xhUXMlwvtPYy Nhdg== X-Forwarded-Encrypted: i=1; AJvYcCWGZurzfXnAoX38WIOlpl7M7MPKLTA8ZriyYWeZQ6/63NhHh1tXp4NQKrd0cDN/t85ej+WkkxiHWBem4Q623ABurUrPwqeC5y8EmIAr X-Gm-Message-State: AOJu0Ywe2QKu+gLWj9a5zmmy0biJeBEQEb24ZFAZytcam7wVGyC2Vm4B lWY2wmrl4+Iz5/kazGyfroi6ObYHzoEhkZaHx4VtOinzsivMtb/GO5VjOx/m75k= X-Google-Smtp-Source: AGHT+IHFA/cX0NP9mCPfOfOYMEWQuBq1O8OW9hOsbV/JoUh2wlE3WrWL4Tbx12X8W80ajNAGYt4JUg== X-Received: by 2002:ac2:59d0:0:b0:51a:c913:a9ce with SMTP id 2adb3069b0e04-5221016e9b5mr451242e87.50.1715294260157; Thu, 09 May 2024 15:37:40 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:39 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:39 +0300 Subject: [PATCH RFC 6/7] drm/panel: lg-sw43408: add missing error handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-6-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2829; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=0hHShducaAcMM1humQX/WthNAOeANb5d92F25xx+Ojw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmPVAv7uOuDHmzIgnZl/hgCLHI0ZGC3YAQ6chPy Lo2F9poo2qJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj1QLwAKCRCLPIo+Aiko 1X4zCACLyiMXdslsIcAFwHjM5jLM9yNm8VCGKPBgQsAj+QXVcpr+yNuaAhwp3y5hy5dQc+ZmzUL xCK65hUPV2jIWvhcGahKYiHJCVmjtLxMAU5mYO2YTCnBnSqgvLrKNuDFSbhbRK+Pk+5Vy3Dio86 ea1ttyRr4DaTFvL3eEpTEWSbP4S3xrDwP++NQvpqh3R9Zu67Ik8pV2b65uKQcxgtHiImdo3rrEA l8k356tA62lWznZWLTrMQHIla//i71FW9KQXHOmO0Cc0XnjU0ahapJPh1pe++Crht0oWU9z9pnM 5fOf5xjkP3d//Wqc1GxiyIsAbZF081LHg+Q2d+Z+GwoYwpKZ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add missing error handling for the mipi_dsi_ functions that actually return error code instead of silently ignoring it. Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 33 ++++++++++++++++++++++++++--= ---- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index 2b3a73696dce..67a98ac508f8 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -62,16 +62,25 @@ static int sw43408_program(struct drm_panel *panel) { struct sw43408_panel *ctx =3D to_panel_info(panel); struct drm_dsc_picture_parameter_set pps; + int ret; =20 mipi_dsi_dcs_write_seq(ctx->link, MIPI_DCS_SET_GAMMA_CURVE, 0x02); =20 - mipi_dsi_dcs_set_tear_on(ctx->link, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + ret =3D mipi_dsi_dcs_set_tear_on(ctx->link, MIPI_DSI_DCS_TEAR_MODE_VBLANK= ); + if (ret < 0) { + dev_err(panel->dev, "Failed to set tearing: %d\n", ret); + return ret; + } =20 mipi_dsi_dcs_write_seq(ctx->link, 0x53, 0x0c, 0x30); mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xd= f); mipi_dsi_dcs_write_seq(ctx->link, 0xf7, 0x01, 0x49, 0x0c); =20 - mipi_dsi_dcs_exit_sleep_mode(ctx->link); + ret =3D mipi_dsi_dcs_exit_sleep_mode(ctx->link); + if (ret < 0) { + dev_err(panel->dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } =20 msleep(135); =20 @@ -97,14 +106,22 @@ static int sw43408_program(struct drm_panel *panel) mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0xd= b); mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xca); =20 - mipi_dsi_dcs_set_display_on(ctx->link); + ret =3D mipi_dsi_dcs_set_display_on(ctx->link); + if (ret < 0) { + dev_err(panel->dev, "Failed to set display on: %d\n", ret); + return ret; + } =20 msleep(50); =20 ctx->link->mode_flags &=3D ~MIPI_DSI_MODE_LPM; =20 drm_dsc_pps_payload_pack(&pps, ctx->link->dsc); - mipi_dsi_picture_parameter_set(ctx->link, &pps); + ret =3D mipi_dsi_picture_parameter_set(ctx->link, &pps); + if (ret < 0) { + dev_err(panel->dev, "Failed to set PPS: %d\n", ret); + return ret; + } =20 ctx->link->mode_flags |=3D MIPI_DSI_MODE_LPM; =20 @@ -113,8 +130,12 @@ static int sw43408_program(struct drm_panel *panel) * PPS 1 if pps_identifier is 0 * PPS 2 if pps_identifier is 1 */ - mipi_dsi_compression_mode_ext(ctx->link, true, - MIPI_DSI_COMPRESSION_DSC, 1); + ret =3D mipi_dsi_compression_mode_ext(ctx->link, true, + MIPI_DSI_COMPRESSION_DSC, 1); + if (ret < 0) { + dev_err(panel->dev, "Failed to set compression mode: %d\n", ret); + return ret; + } =20 return 0; } --=20 2.39.2 From nobody Sun Dec 14 12:02:35 2025 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 872E912D775 for ; Thu, 9 May 2024 22:37:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294264; cv=none; b=D6z+sevKVZGm4Zxi00QN82NvjSrZ4cr2vngNeEPy2SOhJvTMRjwKKSPESMh0lUduNb0o3/NNZfLvS5VM+HfAFMPZLq42LoeSoelaOCceBSTYRqMTRRNq1SHcsd9QDzeIH4psk80I2ZHYWglwqfMjrE/rMq1xbvYEauoF4u9tJic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715294264; c=relaxed/simple; bh=GUWCnr41TB+Guk2h1/zSROPDGudIEU9m291d3/Tj7jk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dd5GSCBb/k/q+eD7U/TzORL16moZcRh1h5l8CR1uExDdpw8ZuleWmBUKed9yPTJb4+JXkUJbTC02qxaXRwBF5xa3uASOKEc3qnNr5mfQPVCN0DDMqXnYVUHmTwt6z7O7QVoO0AQkcmOB2Rt2AqGyucDoL/f5xAA+NzEwd3E4nlM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=QPGP/b1V; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QPGP/b1V" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-51f60817e34so1722710e87.2 for ; Thu, 09 May 2024 15:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715294261; x=1715899061; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4V9OACuRHbXmTK2HTg8i0N9cnf1QLVjm1D07G84y0Mc=; b=QPGP/b1VPRIkuWBbyLfoZMA5MLHDqiQCB9ItPEPiPxChaTQODgCYDzCYKTX5Jp17Pc 9WSiEuvpsgDzDfnS0Lfd+J58wXt4hlM1nwd+mbdj090GjlL8rouw5yDPgFWibi3Q5OW4 UotU+rR9nh6waipK7ZgD9BDblQ0VjWR0wK1fYGz8UY9u5YFyUvioePiLYQRgTNB1lAMS hRcdqvrxNN9YICeO/3DeJ8tPY3z0gkW57lJhos/Rde+vZrZBdVWlq4CXMOWawXAKWwkm d3IyQbKAFPaeESCYa6ZtU+hCnueoOzeK/5t6I7FlgrVgVxteE9sUgnEf4rHzegMcyoeH UjgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715294261; x=1715899061; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4V9OACuRHbXmTK2HTg8i0N9cnf1QLVjm1D07G84y0Mc=; b=MflDeuHtnn6n58pwDskaK/1qmmjRaEGLwnr4DHXJoGZsDjwnr91Jzl8E0YCXdynZSx zBG683767WU6Dj5vm/fkNGqBxIpzIQ7+Cm1zeCoa+/8dgesFZz/SoqAz0SCLOp8WKLY+ NSWWIlmERmhEfF4AFsw5N1pazHzhA8rClfPhxuW0dR9VvsB7hXJkSo/eOEHGVj6xjru1 MpsqJ+6i+M1XUAHciQAJtgpMrR50iCxsaneUt3z1ro4u2gHGWIn/TQ3SQ+qdRAynH3Kd RC1yeduU0yCXNwM9NLmgd4YUGFiNxF7Z/ZhYNamrWCVHtC9H5PaLAVr9VOIbopcnya0q xUcQ== X-Forwarded-Encrypted: i=1; AJvYcCWmoS0jSBE7XJwC+luYJr39LzYtYjb+KVsKihDYbtRj8A06nNcX4iRYCA/1ZrEsI+9A+wAPz+NWxGDBZC70zPCnIAk219Lm44RYJus2 X-Gm-Message-State: AOJu0YwvKTSvUEKv0nGCXrgr8Bp40emCxcdCvvm8YUkj+h1nySy5iAzj de3Hv8Xhuq7TZdWtYqdGu8Yzcd1coIDKdp1EoFgOzL0QOJL6SeuugE4Qy9zVm6g= X-Google-Smtp-Source: AGHT+IH4bxmqWpDeL+ZzttXl0YgWZBnt+QPrn2JZIDE00Yte/ysK+RFkfP2uB4AOozawEkV0ixvYWQ== X-Received: by 2002:a05:6512:33ce:b0:513:edf4:6f20 with SMTP id 2adb3069b0e04-5220fe79457mr584485e87.54.1715294260804; Thu, 09 May 2024 15:37:40 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d32f1sm457974e87.181.2024.05.09.15.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 15:37:40 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 10 May 2024 01:37:40 +0300 Subject: [PATCH RFC 7/7] drm/panel: lg-sw43408: use new streamlined MIPI DSI API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240510-dsi-panels-upd-api-v1-7-317c78a0dcc8@linaro.org> References: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> In-Reply-To: <20240510-dsi-panels-upd-api-v1-0-317c78a0dcc8@linaro.org> To: Douglas Anderson , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Sumit Semwal , Caleb Connolly , Marijn Suijten , Vinod Koul Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5760; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=GUWCnr41TB+Guk2h1/zSROPDGudIEU9m291d3/Tj7jk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmPVAvVHEpsHtQ0Di+uIOFvItselZiMK+9r+UUI k5OzkP5BZSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj1QLwAKCRCLPIo+Aiko 1Q3LB/9UnKKgdFuiCU5XHDbX1us37+pggofnVIlW3X8wgOEa4mWSE/6EpOUFQ2lzlJtqOZhs9jN XAwNM2NpoWTDGpXVFo5yOeHuRKKLPxVrjCr5C1DSPtnVqjEIn/tNYhAkRkA+r/rhHFS8KC8SL9i DIOibWPdbZmUfQybcPMc1IT7xP65iKfVbHo00p3VdDODEFC41reHt3GP6FeYnCT3KTQQsSMaBo0 cW704hv6ADVO6lAqo95JjqZizVkt6YBuDuGyOI2kuLEzOza3qcWH1z+eIMNQPbgJ3FxihDg57Gr WoYpZp4zDFXGsnXHCgW6qDEK58pAHGDm8h1UxN+aRTsVSr8a X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Use newer mipi_dsi_*_multi() functions in order to simplify and cleanup panel's prepare() and unprepare() functions. Signed-off-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 95 +++++++++++++---------------= ---- 1 file changed, 37 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index 67a98ac508f8..f3dcc39670ea 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -40,104 +40,83 @@ static inline struct sw43408_panel *to_panel_info(stru= ct drm_panel *panel) =20 static int sw43408_unprepare(struct drm_panel *panel) { - struct sw43408_panel *ctx =3D to_panel_info(panel); + struct sw43408_panel *sw43408 =3D to_panel_info(panel); + struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; int ret; =20 - ret =3D mipi_dsi_dcs_set_display_off(ctx->link); - if (ret < 0) - dev_err(panel->dev, "set_display_off cmd failed ret =3D %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&ctx); =20 - ret =3D mipi_dsi_dcs_enter_sleep_mode(ctx->link); - if (ret < 0) - dev_err(panel->dev, "enter_sleep cmd failed ret =3D %d\n", ret); + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); =20 - msleep(100); + mipi_dsi_msleep(&ctx, 100); =20 - gpiod_set_value(ctx->reset_gpio, 1); + gpiod_set_value(sw43408->reset_gpio, 1); + + ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408->supplies), sw43408->su= pplies); =20 - return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + return ret ? : ctx.accum_err; } =20 static int sw43408_program(struct drm_panel *panel) { - struct sw43408_panel *ctx =3D to_panel_info(panel); + struct sw43408_panel *sw43408 =3D to_panel_info(panel); + struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; struct drm_dsc_picture_parameter_set pps; - int ret; =20 - mipi_dsi_dcs_write_seq(ctx->link, MIPI_DCS_SET_GAMMA_CURVE, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x02); =20 - ret =3D mipi_dsi_dcs_set_tear_on(ctx->link, MIPI_DSI_DCS_TEAR_MODE_VBLANK= ); - if (ret < 0) { - dev_err(panel->dev, "Failed to set tearing: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_tear_on_multi(&ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); =20 - mipi_dsi_dcs_write_seq(ctx->link, 0x53, 0x0c, 0x30); - mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xd= f); - mipi_dsi_dcs_write_seq(ctx->link, 0xf7, 0x01, 0x49, 0x0c); + mipi_dsi_dcs_write_seq_multi(&ctx, 0x53, 0x0c, 0x30); + mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0x= df); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf7, 0x01, 0x49, 0x0c); =20 - ret =3D mipi_dsi_dcs_exit_sleep_mode(ctx->link); - if (ret < 0) { - dev_err(panel->dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); =20 - msleep(135); + mipi_dsi_msleep(&ctx, 135); =20 /* COMPRESSION_MODE moved after setting the PPS */ =20 - mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xac); - mipi_dsi_dcs_write_seq(ctx->link, 0xe5, + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xac); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xe5, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x0e, 0x10); - mipi_dsi_dcs_write_seq(ctx->link, 0xb5, + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, 0x75, 0x60, 0x2d, 0x5d, 0x80, 0x00, 0x0a, 0x0b, 0x00, 0x05, 0x0b, 0x00, 0x80, 0x0d, 0x0e, 0x40, 0x00, 0x0c, 0x00, 0x16, 0x00, 0xb8, 0x00, 0x80, 0x0d, 0x0e, 0x40, 0x00, 0x0c, 0x00, 0x16, 0x00, 0xb8, 0x00, 0x81, 0x00, 0x03, 0x03, 0x03, 0x01, 0x01); - msleep(85); - mipi_dsi_dcs_write_seq(ctx->link, 0xcd, + mipi_dsi_msleep(&ctx, 85); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xcd, 0x00, 0x00, 0x00, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x16, 0x16); - mipi_dsi_dcs_write_seq(ctx->link, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28); - mipi_dsi_dcs_write_seq(ctx->link, 0xc0, 0x02, 0x02, 0x0f); - mipi_dsi_dcs_write_seq(ctx->link, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0xd= b); - mipi_dsi_dcs_write_seq(ctx->link, 0xb0, 0xca); - - ret =3D mipi_dsi_dcs_set_display_on(ctx->link); - if (ret < 0) { - dev_err(panel->dev, "Failed to set display on: %d\n", ret); - return ret; - } + mipi_dsi_dcs_write_seq_multi(&ctx, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x02, 0x02, 0x0f); + mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0x= db); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xca); =20 - msleep(50); + mipi_dsi_dcs_set_display_on_multi(&ctx); =20 - ctx->link->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + mipi_dsi_msleep(&ctx, 50); =20 - drm_dsc_pps_payload_pack(&pps, ctx->link->dsc); - ret =3D mipi_dsi_picture_parameter_set(ctx->link, &pps); - if (ret < 0) { - dev_err(panel->dev, "Failed to set PPS: %d\n", ret); - return ret; - } + sw43408->link->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + + drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); =20 - ctx->link->mode_flags |=3D MIPI_DSI_MODE_LPM; + mipi_dsi_picture_parameter_set_multi(&ctx, &pps); + + sw43408->link->mode_flags |=3D MIPI_DSI_MODE_LPM; =20 /* * This panel uses PPS selectors with offset: * PPS 1 if pps_identifier is 0 * PPS 2 if pps_identifier is 1 */ - ret =3D mipi_dsi_compression_mode_ext(ctx->link, true, + mipi_dsi_compression_mode_ext_multi(&ctx, true, MIPI_DSI_COMPRESSION_DSC, 1); - if (ret < 0) { - dev_err(panel->dev, "Failed to set compression mode: %d\n", ret); - return ret; - } - - return 0; + return ctx.accum_err; } =20 static int sw43408_prepare(struct drm_panel *panel) --=20 2.39.2