From nobody Wed Dec 17 05:55:58 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31412823DC for ; Wed, 8 May 2024 11:09:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715166553; cv=none; b=TPH2Q+YEFCGnTmX2ryfij4liO59kS+7NZDFD2+7kQaR8qnJbNq2nZkpEtDjugzOzUxasGrmtCz3WNMaHWUTek85k+tW6udLq1s1KFBDrVQpbDnzXvEVnDzueMsqFMgEJbt7kiAlNYUHEnphFCaOlHTTvHQ10ShlHpFTezsXkJCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715166553; c=relaxed/simple; bh=7BAnbozBUGliEkFA2yy81ruk4ikDMyqp7A70k41kDBQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D1ymIv1/sWRSH+dSVb4mvn3H6BLGeQ6d4DpiQiXQOqcYogq0AW92g0o8OsVFpW894LCqSrNie2Iu/ojTkpDaBXBXPDPl92PWFbPe1EVAybfWG5XinMmYi8LoAXCj/ErJPAapOTkIK/vSZmP6+wl5TDq4TiaM2egDGVUkliDKSMc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s4fAA-0001ir-NP; Wed, 08 May 2024 13:08:42 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1s4fA9-000GOD-F5; Wed, 08 May 2024 13:08:41 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1s4fA9-000NrM-18; Wed, 08 May 2024 13:08:41 +0200 From: Sascha Hauer Date: Wed, 08 May 2024 13:08:27 +0200 Subject: [PATCH v2 1/3] mtd: nand: mxc_nand: separate page read from ecc calc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240508-mtd-nand-mxc-nand-exec-op-v2-1-6b7366b7831f@pengutronix.de> References: <20240508-mtd-nand-mxc-nand-exec-op-v2-0-6b7366b7831f@pengutronix.de> In-Reply-To: <20240508-mtd-nand-mxc-nand-exec-op-v2-0-6b7366b7831f@pengutronix.de> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715166521; l=7729; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=7BAnbozBUGliEkFA2yy81ruk4ikDMyqp7A70k41kDBQ=; b=yhAIzWa5qms2dXU4uKUQwYJg+e8o2uH/ni6HwL5eJY7H9BL2xBkG53ZPRBgfqav0uPQlGOgHo AXzs3y6qS3ZBcIpDvS0BzqDZOmmyHMeDhJeEgPkgUMw9JOCVUEePNay X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Our read_page hook currently reads out a page and also counts and returns the number of bitflips. In upcoming exec_op conversion we'll need to read the page data in exec_op, but the bitflip information will be needed in mxc_nand_read_page(). To ease exec_op conversion separate the page read out from the bitflip evaluation. For the v2/v3 controllers we can leave the bitflip information in the status register for later evaluation. For the v1 controller this is not possible, because the status register is overwritten with each subpage read. We therefore store the bitflip information in the private data. Signed-off-by: Sascha Hauer --- drivers/mtd/nand/raw/mxc_nand.c | 140 ++++++++++++++++++++++++------------= ---- 1 file changed, 86 insertions(+), 54 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nan= d.c index 003008355b3c2..3fe0b471f4a2d 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #define DRIVER_NAME "mxc_nand" =20 @@ -47,6 +48,8 @@ #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) =20 +#define NFC_V1_V2_ECC_STATUS_RESULT_ERM GENMASK(3, 2) + #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) @@ -132,7 +135,7 @@ struct mxc_nand_devtype_data { uint16_t (*get_dev_status)(struct mxc_nand_host *); int (*check_int)(struct mxc_nand_host *); void (*irq_control)(struct mxc_nand_host *, int); - u32 (*get_ecc_status)(struct mxc_nand_host *); + u32 (*get_ecc_status)(struct nand_chip *); const struct mtd_ooblayout_ops *ooblayout; void (*select_chip)(struct nand_chip *chip, int cs); int (*setup_interface)(struct nand_chip *chip, int csline, @@ -175,6 +178,7 @@ struct mxc_nand_host { int eccsize; int used_oobsize; int active_cs; + unsigned int ecc_stats_v1; =20 struct completion op_completion; =20 @@ -406,19 +410,81 @@ static void irq_control(struct mxc_nand_host *host, i= nt activate) } } =20 -static u32 get_ecc_status_v1(struct mxc_nand_host *host) +static u32 get_ecc_status_v1(struct nand_chip *chip) { - return readw(NFC_V1_V2_ECC_STATUS_RESULT); + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct mxc_nand_host *host =3D nand_get_controller_data(chip); + unsigned int ecc_stats, max_bitflips =3D 0; + int no_subpages, i; + + no_subpages =3D mtd->writesize >> 9; + + ecc_stats =3D host->ecc_stats_v1; + + for (i =3D 0; i < no_subpages; i++) { + switch (ecc_stats & 0x3) { + case 0: + default: + break; + case 1: + mtd->ecc_stats.corrected++; + max_bitflips =3D 1; + break; + case 2: + mtd->ecc_stats.failed++; + break; + } + + ecc_stats >>=3D 2; + } + + return max_bitflips; } =20 -static u32 get_ecc_status_v2(struct mxc_nand_host *host) +static u32 get_ecc_status_v2_v3(struct nand_chip *chip, unsigned int ecc_s= tat) { - return readl(NFC_V1_V2_ECC_STATUS_RESULT); + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct mxc_nand_host *host =3D nand_get_controller_data(chip); + u8 ecc_bit_mask, err_limit; + unsigned int max_bitflips =3D 0; + int no_subpages, err; + + ecc_bit_mask =3D (host->eccsize =3D=3D 4) ? 0x7 : 0xf; + err_limit =3D (host->eccsize =3D=3D 4) ? 0x4 : 0x8; + + no_subpages =3D mtd->writesize >> 9; + + do { + err =3D ecc_stat & ecc_bit_mask; + if (err > err_limit) { + mtd->ecc_stats.failed++; + } else { + mtd->ecc_stats.corrected +=3D err; + max_bitflips =3D max_t(unsigned int, max_bitflips, err); + } + + ecc_stat >>=3D 4; + } while (--no_subpages); + + return max_bitflips; } =20 -static u32 get_ecc_status_v3(struct mxc_nand_host *host) +static u32 get_ecc_status_v2(struct nand_chip *chip) { - return readl(NFC_V3_ECC_STATUS_RESULT); + struct mxc_nand_host *host =3D nand_get_controller_data(chip); + + u32 ecc_stat =3D readl(NFC_V1_V2_ECC_STATUS_RESULT); + + return get_ecc_status_v2_v3(chip, ecc_stat); +} + +static u32 get_ecc_status_v3(struct nand_chip *chip) +{ + struct mxc_nand_host *host =3D nand_get_controller_data(chip); + + u32 ecc_stat =3D readl(NFC_V3_ECC_STATUS_RESULT); + + return get_ecc_status_v2_v3(chip, ecc_stat); } =20 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) @@ -712,9 +778,9 @@ static int mxc_nand_read_page_v1(struct nand_chip *chip= , void *buf, void *oob, { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); - unsigned int bitflips_corrected =3D 0; int no_subpages; int i; + unsigned int ecc_stats =3D 0; =20 host->devtype_data->enable_hwecc(chip, ecc); =20 @@ -727,8 +793,6 @@ static int mxc_nand_read_page_v1(struct nand_chip *chip= , void *buf, void *oob, no_subpages =3D mtd->writesize >> 9; =20 for (i =3D 0; i < no_subpages; i++) { - uint16_t ecc_stats; - /* NANDFC buffer 0 is used for page read/write */ writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); =20 @@ -737,32 +801,18 @@ static int mxc_nand_read_page_v1(struct nand_chip *ch= ip, void *buf, void *oob, /* Wait for operation to complete */ wait_op_done(host, true); =20 - ecc_stats =3D get_ecc_status_v1(host); - - ecc_stats >>=3D 2; - - if (buf && ecc) { - switch (ecc_stats & 0x3) { - case 0: - default: - break; - case 1: - mtd->ecc_stats.corrected++; - bitflips_corrected =3D 1; - break; - case 2: - mtd->ecc_stats.failed++; - break; - } - } + ecc_stats |=3D FIELD_GET(NFC_V1_V2_ECC_STATUS_RESULT_ERM, + readw(NFC_V1_V2_ECC_STATUS_RESULT)) << i * 2; } =20 + host->ecc_stats_v1 =3D ecc_stats; + if (buf) memcpy32_fromio(buf, host->main_area0, mtd->writesize); if (oob) copy_spare(mtd, true, oob); =20 - return bitflips_corrected; + return 0; } =20 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf, @@ -770,10 +820,6 @@ static int mxc_nand_read_page_v2_v3(struct nand_chip *= chip, void *buf, { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); - unsigned int max_bitflips =3D 0; - u32 ecc_stat, err; - int no_subpages; - u8 ecc_bit_mask, err_limit; =20 host->devtype_data->enable_hwecc(chip, ecc); =20 @@ -791,26 +837,7 @@ static int mxc_nand_read_page_v2_v3(struct nand_chip *= chip, void *buf, if (oob) copy_spare(mtd, true, oob); =20 - ecc_bit_mask =3D (host->eccsize =3D=3D 4) ? 0x7 : 0xf; - err_limit =3D (host->eccsize =3D=3D 4) ? 0x4 : 0x8; - - no_subpages =3D mtd->writesize >> 9; - - ecc_stat =3D host->devtype_data->get_ecc_status(host); - - do { - err =3D ecc_stat & ecc_bit_mask; - if (err > err_limit) { - mtd->ecc_stats.failed++; - } else { - mtd->ecc_stats.corrected +=3D err; - max_bitflips =3D max_t(unsigned int, max_bitflips, err); - } - - ecc_stat >>=3D 4; - } while (--no_subpages); - - return max_bitflips; + return 0; } =20 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf, @@ -818,13 +845,18 @@ static int mxc_nand_read_page(struct nand_chip *chip,= uint8_t *buf, { struct mxc_nand_host *host =3D nand_get_controller_data(chip); void *oob_buf; + int ret; =20 if (oob_required) oob_buf =3D chip->oob_poi; else oob_buf =3D NULL; =20 - return host->devtype_data->read_page(chip, buf, oob_buf, 1, page); + ret =3D host->devtype_data->read_page(chip, buf, oob_buf, 1, page); + if (ret) + return ret; + + return host->devtype_data->get_ecc_status(chip); } =20 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, --=20 2.39.2 From nobody Wed Dec 17 05:55:58 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A2E281AC9 for ; Wed, 8 May 2024 11:09:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715166545; cv=none; b=pAYWm5cs34KZvK1M2KCk+DWd63XPGmvp1SvXP/VNnufXBsTvTYy9gHcdYOogOKwf/suFFpih9tZBZR1Jqv71IZzHUp8biidU7auLEHsEUFPAjAGpWaheFH4MlQJsEjVlXBXyUbPsNohnU3IV6aQQ5U2vTOU1ZNOGJmmL9VWtv2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715166545; c=relaxed/simple; bh=nR24a7ok93BDZYsQ8WLTNN6iykSFPU6FBLUbOMRyfWE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UeEE4fstNq8TH4Jyd/C4rCHoESSiUFZHmNaOav7Vhl450xX9l5Gp465TiqE0/ocjw87YWcBAdr4Sfpibe4zDQZUAdduaydiR5btwDRlIt6vWZKLkKNwfufcxm5GzW1y4Luis/qsQS6ppFgj2amKSvqySQj84O2aOoR50wp7GqsM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s4fAA-0001io-NQ; Wed, 08 May 2024 13:08:42 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1s4fA9-000GOA-En; Wed, 08 May 2024 13:08:41 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1s4fA9-000NrM-19; Wed, 08 May 2024 13:08:41 +0200 From: Sascha Hauer Date: Wed, 08 May 2024 13:08:28 +0200 Subject: [PATCH v2 2/3] mtd: nand: mxc_nand: implement exec_op Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240508-mtd-nand-mxc-nand-exec-op-v2-2-6b7366b7831f@pengutronix.de> References: <20240508-mtd-nand-mxc-nand-exec-op-v2-0-6b7366b7831f@pengutronix.de> In-Reply-To: <20240508-mtd-nand-mxc-nand-exec-op-v2-0-6b7366b7831f@pengutronix.de> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715166521; l=18409; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=nR24a7ok93BDZYsQ8WLTNN6iykSFPU6FBLUbOMRyfWE=; b=FPSeL+plFCFM1Bgfht0G4CkVkQInwUPA+lzqKR+Mt3vFmq82wDSUa/G40VwBIwIAdrt32/3Vb XreQPjstKdVDrACprtK/z7ZmNB4wkOTHcNWBhvb1morI1keouIhwheC X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org This converts the driver to the more modern exec_op which gets us rid of a bunch of legacy code. Tested on i.MX27 and i.MX25. Signed-off-by: Sascha Hauer --- drivers/mtd/nand/raw/mxc_nand.c | 449 +++++++++++++-----------------------= ---- 1 file changed, 146 insertions(+), 303 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nan= d.c index 3fe0b471f4a2d..1e8b4553e03ba 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -126,8 +126,7 @@ struct mxc_nand_host; =20 struct mxc_nand_devtype_data { void (*preset)(struct mtd_info *); - int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc, - int page); + int (*read_page)(struct nand_chip *chip); void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); void (*send_addr)(struct mxc_nand_host *, uint16_t, int); void (*send_page)(struct mtd_info *, unsigned int); @@ -182,8 +181,7 @@ struct mxc_nand_host { =20 struct completion op_completion; =20 - uint8_t *data_buf; - unsigned int buf_start; + void *data_buf; =20 const struct mxc_nand_devtype_data *devtype_data; }; @@ -285,63 +283,6 @@ static void copy_spare(struct mtd_info *mtd, bool bfro= m, void *buf) } } =20 -/* - * MXC NANDFC can only perform full page+spare or spare-only read/write. = When - * the upper layers perform a read/write buf operation, the saved column a= ddress - * is used to index into the full page. So usually this function is called= with - * column =3D=3D 0 (unless no column cycle is needed indicated by column = =3D=3D -1) - */ -static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_a= ddr) -{ - struct nand_chip *nand_chip =3D mtd_to_nand(mtd); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - - /* Write out column address, if necessary */ - if (column !=3D -1) { - host->devtype_data->send_addr(host, column & 0xff, - page_addr =3D=3D -1); - if (mtd->writesize > 512) - /* another col addr cycle for 2k page */ - host->devtype_data->send_addr(host, - (column >> 8) & 0xff, - false); - } - - /* Write out page address, if necessary */ - if (page_addr !=3D -1) { - /* paddr_0 - p_addr_7 */ - host->devtype_data->send_addr(host, (page_addr & 0xff), false); - - if (mtd->writesize > 512) { - if (mtd->size >=3D 0x10000000) { - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, - false); - host->devtype_data->send_addr(host, - (page_addr >> 16) & 0xff, - true); - } else - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, true); - } else { - if (nand_chip->options & NAND_ROW_ADDR_3) { - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, - false); - host->devtype_data->send_addr(host, - (page_addr >> 16) & 0xff, - true); - } else - /* paddr_8 - paddr_15 */ - host->devtype_data->send_addr(host, - (page_addr >> 8) & 0xff, true); - } - } -} - static int check_int_v3(struct mxc_nand_host *host) { uint32_t tmp; @@ -763,18 +704,7 @@ static void mxc_nand_enable_hwecc_v3(struct nand_chip = *chip, bool enable) writel(config2, NFC_V3_CONFIG2); } =20 -/* This functions is used by upper layer to checks if device is ready */ -static int mxc_nand_dev_ready(struct nand_chip *chip) -{ - /* - * NFC handles R/B internally. Therefore, this function - * always returns status as ready. - */ - return 1; -} - -static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *= oob, - bool ecc, int page) +static int mxc_nand_read_page_v1(struct nand_chip *chip) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); @@ -782,15 +712,11 @@ static int mxc_nand_read_page_v1(struct nand_chip *ch= ip, void *buf, void *oob, int i; unsigned int ecc_stats =3D 0; =20 - host->devtype_data->enable_hwecc(chip, ecc); - - host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); - mxc_do_addr_cycle(mtd, 0, page); - - if (mtd->writesize > 512) - host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true); - - no_subpages =3D mtd->writesize >> 9; + if (mtd->writesize) + no_subpages =3D mtd->writesize >> 9; + else + /* READ PARAMETER PAGE is called when mtd->writesize is not yet set */ + no_subpages =3D 1; =20 for (i =3D 0; i < no_subpages; i++) { /* NANDFC buffer 0 is used for page read/write */ @@ -807,181 +733,104 @@ static int mxc_nand_read_page_v1(struct nand_chip *= chip, void *buf, void *oob, =20 host->ecc_stats_v1 =3D ecc_stats; =20 - if (buf) - memcpy32_fromio(buf, host->main_area0, mtd->writesize); - if (oob) - copy_spare(mtd, true, oob); - return 0; } =20 -static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf, - void *oob, bool ecc, int page) +static int mxc_nand_read_page_v2_v3(struct nand_chip *chip) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); =20 - host->devtype_data->enable_hwecc(chip, ecc); - - host->devtype_data->send_cmd(host, NAND_CMD_READ0, false); - mxc_do_addr_cycle(mtd, 0, page); - - if (mtd->writesize > 512) - host->devtype_data->send_cmd(host, - NAND_CMD_READSTART, true); - host->devtype_data->send_page(mtd, NFC_OUTPUT); =20 - if (buf) - memcpy32_fromio(buf, host->main_area0, mtd->writesize); - if (oob) - copy_spare(mtd, true, oob); - return 0; } =20 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { + struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); - void *oob_buf; int ret; =20 - if (oob_required) - oob_buf =3D chip->oob_poi; - else - oob_buf =3D NULL; + host->devtype_data->enable_hwecc(chip, true); + + ret =3D nand_read_page_op(chip, page, 0, buf, mtd->writesize); + + host->devtype_data->enable_hwecc(chip, false); =20 - ret =3D host->devtype_data->read_page(chip, buf, oob_buf, 1, page); if (ret) return ret; =20 + if (oob_required) + copy_spare(mtd, true, chip->oob_poi); + return host->devtype_data->get_ecc_status(chip); } =20 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - void *oob_buf; + struct mtd_info *mtd =3D nand_to_mtd(chip); + int ret; + + ret =3D nand_read_page_op(chip, page, 0, buf, mtd->writesize); + if (ret) + return ret; =20 if (oob_required) - oob_buf =3D chip->oob_poi; - else - oob_buf =3D NULL; + copy_spare(mtd, true, chip->oob_poi); =20 - return host->devtype_data->read_page(chip, buf, oob_buf, 0, page); + return 0; } =20 static int mxc_nand_read_oob(struct nand_chip *chip, int page) -{ - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - - return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0, - page); -} - -static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf, - bool ecc, int page) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); + int ret; =20 - host->devtype_data->enable_hwecc(chip, ecc); - - host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false); - mxc_do_addr_cycle(mtd, 0, page); - - memcpy32_toio(host->main_area0, buf, mtd->writesize); - copy_spare(mtd, false, chip->oob_poi); + ret =3D nand_read_page_op(chip, page, 0, host->data_buf, mtd->writesize); + if (ret) + return ret; =20 - host->devtype_data->send_page(mtd, NFC_INPUT); - host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true); - mxc_do_addr_cycle(mtd, 0, page); + copy_spare(mtd, true, chip->oob_poi); =20 return 0; } =20 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *= buf, int oob_required, int page) -{ - return mxc_nand_write_page(chip, buf, true, page); -} - -static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *= buf, - int oob_required, int page) -{ - return mxc_nand_write_page(chip, buf, false, page); -} - -static int mxc_nand_write_oob(struct nand_chip *chip, int page) { struct mtd_info *mtd =3D nand_to_mtd(chip); struct mxc_nand_host *host =3D nand_get_controller_data(chip); + int ret; =20 - memset(host->data_buf, 0xff, mtd->writesize); - - return mxc_nand_write_page(chip, host->data_buf, false, page); -} - -static u_char mxc_nand_read_byte(struct nand_chip *nand_chip) -{ - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - uint8_t ret; - - /* Check for status request */ - if (host->status_request) - return host->devtype_data->get_dev_status(host) & 0xFF; + host->devtype_data->enable_hwecc(chip, true); =20 - if (nand_chip->options & NAND_BUSWIDTH_16) { - /* only take the lower byte of each word */ - ret =3D *(uint16_t *)(host->data_buf + host->buf_start); + ret =3D nand_prog_page_op(chip, page, 0, buf, mtd->writesize); =20 - host->buf_start +=3D 2; - } else { - ret =3D *(uint8_t *)(host->data_buf + host->buf_start); - host->buf_start++; - } + host->devtype_data->enable_hwecc(chip, false); =20 - dev_dbg(host->dev, "%s: ret=3D0x%hhx (start=3D%u)\n", __func__, ret, host= ->buf_start); return ret; } =20 -/* Write data of length len to buffer buf. The data to be - * written on NAND Flash is first copied to RAMbuffer. After the Data Input - * Operation by the NFC, the data is written to NAND Flash */ -static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *= buf, - int len) +static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *= buf, + int oob_required, int page) { - struct mtd_info *mtd =3D nand_to_mtd(nand_chip); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - u16 col =3D host->buf_start; - int n =3D mtd->oobsize + mtd->writesize - col; - - n =3D min(n, len); - - memcpy(host->data_buf + col, buf, n); + struct mtd_info *mtd =3D nand_to_mtd(chip); =20 - host->buf_start +=3D n; + return nand_prog_page_op(chip, page, 0, buf, mtd->writesize); } =20 -/* Read the data buffer from the NAND Flash. To read the data from NAND - * Flash first the data output cycle is initiated by the NFC, which copies - * the data to RAMbuffer. This data of length len is then copied to buffer= buf. - */ -static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf, - int len) +static int mxc_nand_write_oob(struct nand_chip *chip, int page) { - struct mtd_info *mtd =3D nand_to_mtd(nand_chip); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - u16 col =3D host->buf_start; - int n =3D mtd->oobsize + mtd->writesize - col; - - n =3D min(n, len); + struct mtd_info *mtd =3D nand_to_mtd(chip); + struct mxc_nand_host *host =3D nand_get_controller_data(chip); =20 - memcpy(buf, host->data_buf + col, n); + memset(host->data_buf, 0xff, mtd->writesize); =20 - host->buf_start +=3D n; + return nand_prog_page_op(chip, page, 0, host->data_buf, mtd->writesize); } =20 /* This function is used by upper layer for select and @@ -1360,107 +1209,6 @@ static void preset_v3(struct mtd_info *mtd) writel(0, NFC_V3_DELAY_LINE); } =20 -/* Used by the upper layer to write command to NAND Flash for - * different operations to be carried out on NAND Flash */ -static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command, - int column, int page_addr) -{ - struct mtd_info *mtd =3D nand_to_mtd(nand_chip); - struct mxc_nand_host *host =3D nand_get_controller_data(nand_chip); - - dev_dbg(host->dev, "mxc_nand_command (cmd =3D 0x%x, col =3D 0x%x, page = =3D 0x%x)\n", - command, column, page_addr); - - /* Reset command state information */ - host->status_request =3D false; - - /* Command pre-processing step */ - switch (command) { - case NAND_CMD_RESET: - host->devtype_data->preset(mtd); - host->devtype_data->send_cmd(host, command, false); - break; - - case NAND_CMD_STATUS: - host->buf_start =3D 0; - host->status_request =3D true; - - host->devtype_data->send_cmd(host, command, true); - WARN_ONCE(column !=3D -1 || page_addr !=3D -1, - "Unexpected column/row value (cmd=3D%u, col=3D%d, row=3D%d)\n", - command, column, page_addr); - mxc_do_addr_cycle(mtd, column, page_addr); - break; - - case NAND_CMD_READID: - host->devtype_data->send_cmd(host, command, true); - mxc_do_addr_cycle(mtd, column, page_addr); - host->devtype_data->send_read_id(host); - host->buf_start =3D 0; - break; - - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - host->devtype_data->send_cmd(host, command, false); - WARN_ONCE(column !=3D -1, - "Unexpected column value (cmd=3D%u, col=3D%d)\n", - command, column); - mxc_do_addr_cycle(mtd, column, page_addr); - - break; - case NAND_CMD_PARAM: - host->devtype_data->send_cmd(host, command, false); - mxc_do_addr_cycle(mtd, column, page_addr); - host->devtype_data->send_page(mtd, NFC_OUTPUT); - memcpy32_fromio(host->data_buf, host->main_area0, 512); - host->buf_start =3D 0; - break; - default: - WARN_ONCE(1, "Unimplemented command (cmd=3D%u)\n", - command); - break; - } -} - -static int mxc_nand_set_features(struct nand_chip *chip, int addr, - u8 *subfeature_param) -{ - struct mtd_info *mtd =3D nand_to_mtd(chip); - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - int i; - - host->buf_start =3D 0; - - for (i =3D 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) - chip->legacy.write_byte(chip, subfeature_param[i]); - - memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize); - host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false); - mxc_do_addr_cycle(mtd, addr, -1); - host->devtype_data->send_page(mtd, NFC_INPUT); - - return 0; -} - -static int mxc_nand_get_features(struct nand_chip *chip, int addr, - u8 *subfeature_param) -{ - struct mtd_info *mtd =3D nand_to_mtd(chip); - struct mxc_nand_host *host =3D nand_get_controller_data(chip); - int i; - - host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false); - mxc_do_addr_cycle(mtd, addr, -1); - host->devtype_data->send_page(mtd, NFC_OUTPUT); - memcpy32_fromio(host->data_buf, host->main_area0, 512); - host->buf_start =3D 0; - - for (i =3D 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) - *subfeature_param++ =3D chip->legacy.read_byte(chip); - - return 0; -} - /* * The generic flash bbt descriptors overlap with our ecc * hardware, so define some i.MX specific ones. @@ -1717,9 +1465,111 @@ static int mxcnd_setup_interface(struct nand_chip *= chip, int chipnr, return host->devtype_data->setup_interface(chip, chipnr, conf); } =20 +static int mxcnd_exec_op(struct nand_chip *chip, + const struct nand_operation *op, + bool check_only) +{ + struct mxc_nand_host *host =3D nand_get_controller_data(chip); + struct mtd_info *mtd =3D nand_to_mtd(chip); + int i, j, buf_len; + void *buf_read =3D NULL; + const void *buf_write =3D NULL; + const struct nand_op_instr *instr; + bool readid =3D false; + bool statusreq =3D false; + + dev_dbg(host->dev, "%s: %d instructions\n", __func__, op->ninstrs); + + if (check_only) + return 0; + + for (i =3D 0; i < op->ninstrs; i++) { + instr =3D &op->instrs[i]; + + nand_op_trace(" ", instr); + + switch (instr->type) { + case NAND_OP_WAITRDY_INSTR: + /* + * NFC handles R/B internally. Therefore, this function + * always returns status as ready. + */ + break; + case NAND_OP_CMD_INSTR: + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_PAGEPROG) + host->devtype_data->send_page(mtd, NFC_INPUT); + + host->devtype_data->send_cmd(host, instr->ctx.cmd.opcode, true); + + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_READID) + readid =3D true; + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_STATUS) + statusreq =3D true; + + break; + case NAND_OP_ADDR_INSTR: + for (j =3D 0; j < instr->ctx.addr.naddrs; j++) { + bool islast =3D j =3D=3D instr->ctx.addr.naddrs - 1; + host->devtype_data->send_addr(host, instr->ctx.addr.addrs[j], islast); + } + break; + case NAND_OP_DATA_OUT_INSTR: + buf_write =3D instr->ctx.data.buf.out; + buf_len =3D instr->ctx.data.len; + + memcpy32_toio(host->main_area0, buf_write, buf_len); + if (chip->oob_poi) + copy_spare(mtd, false, chip->oob_poi); + + break; + case NAND_OP_DATA_IN_INSTR: + + buf_read =3D instr->ctx.data.buf.in; + buf_len =3D instr->ctx.data.len; + + if (readid) { + host->devtype_data->send_read_id(host); + readid =3D false; + + memcpy32_fromio(host->data_buf, host->main_area0, buf_len * 2); + + if (chip->options & NAND_BUSWIDTH_16) { + u8 *bufr =3D buf_read; + u16 *bufw =3D host->data_buf; + for (j =3D 0; j < buf_len; j++) + bufr[j] =3D bufw[j]; + } else { + memcpy(buf_read, host->data_buf, buf_len); + } + break; + } + + if (statusreq) { + *(u8*)buf_read =3D host->devtype_data->get_dev_status(host); + statusreq =3D false; + break; + } + + host->devtype_data->read_page(chip); + + if (IS_ALIGNED(buf_len, 4)) { + memcpy32_fromio(buf_read, host->main_area0, buf_len); + } else { + memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize); + memcpy(buf_read, host->data_buf, buf_len); + } + + break; + } + } + + return 0; +} + static const struct nand_controller_ops mxcnd_controller_ops =3D { .attach_chip =3D mxcnd_attach_chip, .setup_interface =3D mxcnd_setup_interface, + .exec_op =3D mxcnd_exec_op, }; =20 static int mxcnd_probe(struct platform_device *pdev) @@ -1752,13 +1602,6 @@ static int mxcnd_probe(struct platform_device *pdev) =20 nand_set_controller_data(this, host); nand_set_flash_node(this, pdev->dev.of_node); - this->legacy.dev_ready =3D mxc_nand_dev_ready; - this->legacy.cmdfunc =3D mxc_nand_command; - this->legacy.read_byte =3D mxc_nand_read_byte; - this->legacy.write_buf =3D mxc_nand_write_buf; - this->legacy.read_buf =3D mxc_nand_read_buf; - this->legacy.set_features =3D mxc_nand_set_features; - this->legacy.get_features =3D mxc_nand_get_features; =20 host->clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(host->clk)) --=20 2.39.2 From nobody Wed Dec 17 05:55:58 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6E5181749 for ; Wed, 8 May 2024 11:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715166536; cv=none; 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Wed, 08 May 2024 13:08:42 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1s4fA9-000GOC-FN; Wed, 08 May 2024 13:08:41 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1s4fA9-000NrM-1B; Wed, 08 May 2024 13:08:41 +0200 From: Sascha Hauer Date: Wed, 08 May 2024 13:08:29 +0200 Subject: [PATCH v2 3/3] mtd: nand: mxc_nand: support software ECC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240508-mtd-nand-mxc-nand-exec-op-v2-3-6b7366b7831f@pengutronix.de> References: <20240508-mtd-nand-mxc-nand-exec-op-v2-0-6b7366b7831f@pengutronix.de> In-Reply-To: <20240508-mtd-nand-mxc-nand-exec-op-v2-0-6b7366b7831f@pengutronix.de> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715166521; l=5562; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=/VEH8HbAUQ9vRq1WUQ5QTlx2rcRXtWl9g9yWb1j/h/A=; b=9e3+uvrm0Hv+rOQCGeL/ysM5mV0yTHEE6utD6QipEFWa/qtp47wqMmRquhU1/zJCCpP2A2Iq+ 36uyRsfVo5FDjZHjzQhuvMF1yUAivaeKjnYKu4qCxOhXWPDWk/A0srW X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org With these changes the driver can be used with software BCH ECC which is useful for NAND chips that require a stronger ECC than the i.MX hardware supports. The controller normally interleaves user data with OOB data when accessing the NAND chip. With Software BCH ECC we write the data to the NAND in a way that the raw data on the NAND chip matches the way the NAND layer sees it. This way commands like NAND_CMD_RNDOUT work as expected. This was tested on i.MX27 but should work on the other SoCs supported by this driver as well. Signed-off-by: Sascha Hauer --- drivers/mtd/nand/raw/mxc_nand.c | 84 ++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 75 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nan= d.c index 1e8b4553e03ba..7004fd57c80f7 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -178,6 +178,7 @@ struct mxc_nand_host { int used_oobsize; int active_cs; unsigned int ecc_stats_v1; + unsigned int column; =20 struct completion op_completion; =20 @@ -1397,10 +1398,10 @@ static int mxcnd_attach_chip(struct nand_chip *chip) chip->ecc.bytes =3D host->devtype_data->eccbytes; host->eccsize =3D host->devtype_data->eccsize; chip->ecc.size =3D 512; - mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_ON_HOST: + mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); chip->ecc.read_page =3D mxc_nand_read_page; chip->ecc.read_page_raw =3D mxc_nand_read_page_raw; chip->ecc.read_oob =3D mxc_nand_read_oob; @@ -1465,6 +1466,54 @@ static int mxcnd_setup_interface(struct nand_chip *c= hip, int chipnr, return host->devtype_data->setup_interface(chip, chipnr, conf); } =20 +static void copy_page_to_sram(struct mtd_info *mtd) +{ + struct nand_chip *this =3D mtd_to_nand(mtd); + struct mxc_nand_host *host =3D nand_get_controller_data(this); + void *buf =3D host->data_buf; + unsigned int n_subpages =3D mtd->writesize / 512; + int oob_per_subpage, i; + + /* mtd->writesize is not set during ident scanning */ + if (!n_subpages) + n_subpages =3D 1; + + oob_per_subpage =3D (mtd->oobsize / n_subpages) & ~1; + + for (i =3D 0; i < n_subpages; i++) { + memcpy16_toio(host->main_area0 + i * 512, buf, 512); + buf +=3D 512; + + memcpy16_toio(host->spare0 + i * host->devtype_data->spare_len, buf, + oob_per_subpage); + buf +=3D oob_per_subpage; + } +} + +static void copy_page_from_sram(struct mtd_info *mtd) +{ + struct nand_chip *this =3D mtd_to_nand(mtd); + struct mxc_nand_host *host =3D nand_get_controller_data(this); + void *buf =3D host->data_buf; + unsigned int n_subpages =3D mtd->writesize / 512; + int oob_per_subpage, i; + + /* mtd->writesize is not set during ident scanning */ + if (!n_subpages) + n_subpages =3D 1; + + oob_per_subpage =3D (mtd->oobsize / n_subpages) & ~1; + + for (i =3D 0; i < n_subpages; i++) { + memcpy16_fromio(buf, host->main_area0 + i * 512, 512); + buf +=3D 512; + + memcpy16_fromio(buf, host->spare0 + i * host->devtype_data->spare_len, + oob_per_subpage); + buf +=3D oob_per_subpage; + } +} + static int mxcnd_exec_op(struct nand_chip *chip, const struct nand_operation *op, bool check_only) @@ -1496,8 +1545,11 @@ static int mxcnd_exec_op(struct nand_chip *chip, */ break; case NAND_OP_CMD_INSTR: - if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_PAGEPROG) + if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_PAGEPROG) { + if (chip->ecc.engine_type !=3D NAND_ECC_ENGINE_TYPE_ON_HOST) + copy_page_to_sram(mtd); host->devtype_data->send_page(mtd, NFC_INPUT); + } =20 host->devtype_data->send_cmd(host, instr->ctx.cmd.opcode, true); =20 @@ -1506,6 +1558,8 @@ static int mxcnd_exec_op(struct nand_chip *chip, if (instr->ctx.cmd.opcode =3D=3D NAND_CMD_STATUS) statusreq =3D true; =20 + host->column =3D 0; + break; case NAND_OP_ADDR_INSTR: for (j =3D 0; j < instr->ctx.addr.naddrs; j++) { @@ -1517,9 +1571,14 @@ static int mxcnd_exec_op(struct nand_chip *chip, buf_write =3D instr->ctx.data.buf.out; buf_len =3D instr->ctx.data.len; =20 - memcpy32_toio(host->main_area0, buf_write, buf_len); - if (chip->oob_poi) - copy_spare(mtd, false, chip->oob_poi); + if (chip->ecc.engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST) { + memcpy32_toio(host->main_area0, buf_write, buf_len); + if (chip->oob_poi) + copy_spare(mtd, false, chip->oob_poi); + } else { + memcpy(host->data_buf + host->column, buf_write, buf_len); + host->column +=3D buf_len; + } =20 break; case NAND_OP_DATA_IN_INSTR: @@ -1552,11 +1611,18 @@ static int mxcnd_exec_op(struct nand_chip *chip, =20 host->devtype_data->read_page(chip); =20 - if (IS_ALIGNED(buf_len, 4)) { - memcpy32_fromio(buf_read, host->main_area0, buf_len); + if (chip->ecc.engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST) { + if (IS_ALIGNED(buf_len, 4)) { + memcpy32_fromio(buf_read, host->main_area0, buf_len); + } else { + memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize); + memcpy(buf_read, host->data_buf, buf_len); + } } else { - memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize); - memcpy(buf_read, host->data_buf, buf_len); + if (!host->column) + copy_page_from_sram(mtd); + memcpy(buf_read, host->data_buf + host->column, buf_len); + host->column +=3D buf_len; } =20 break; --=20 2.39.2