From nobody Wed Dec 17 07:25:40 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CB6315ECED; Tue, 7 May 2024 21:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715116094; cv=none; b=I/InXNlvHSdhAGKNn3KgBgUXLjFm/JVk4Hsg1nLzZJS8AiWlbuFE16IP99Pc9F4njEdFz9Z4BihgHdvVN06U9ZikBgjv931urxWvLYUkIr9P/dMYxgI94tm1gVUyDIqhYoc9xLilNAnMaJzub4NRK+T0cb3m3T7NIT+iY7ZU3rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715116094; c=relaxed/simple; bh=lHNb0MAV0a6FJlT5OnDvwoktsTsIwlXV9s1tj71oOW8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lRIqGrzrLo67dnLcY6qZL16VeeaVvrART50raWUtQKjUDcrYW0Auxo6MzRHFkICQzGbYhZt87fNG8F60uSkF0msnpc6BhvQvwUM5Pbsv8ujPzJcb7bbc4W4TSswH3Pypoy6dy8R4P2QEbyp/00nii+RP7ZOXktCLsH9dBoNi2pQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G+kHqrf8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G+kHqrf8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC53BC4AF63; Tue, 7 May 2024 21:08:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715116094; bh=lHNb0MAV0a6FJlT5OnDvwoktsTsIwlXV9s1tj71oOW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G+kHqrf8/AFPSW0Nt3vdc89MAR6zdqoP0DFxWWv061JId53cRQwx7RoJmBIcliz8F OXSDbH+qJx2NaKS3c22vdcVNBfdZizY9JkDL4n0DS/2hWapjdIngB8KGn8m/S6sQ4s kHQYdSv6+oCkdk8p2MdJ9yzo1rbpPMAk9Q+deueUH4qnD5JQf0YI7AcYYd9DhnzAMi iPe84okWKr8vMgCZT19KoQJTAYGl20FqL2HF5eK3gVePXuvafl93t55DX17IcfBYmu nhG0ogSlio4RcP23vg8dVp/I0UNZr7iK/lGWymirP2RGQP2CAHBHOWEeAFYn+EHvXz MH/bvBGw4tb1A== From: Stephen Boyd To: Greg Kroah-Hartman Cc: Abel Vesa , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Krzysztof Kozlowski Subject: [PATCH 06/12] dt-bindings: spmi: Add X1E80100 SPMI PMIC ARB schema Date: Tue, 7 May 2024 14:07:43 -0700 Message-ID: <20240507210809.3479953-7-sboyd@kernel.org> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog In-Reply-To: <20240507210809.3479953-1-sboyd@kernel.org> References: <20240507210809.3479953-1-sboyd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Abel Vesa Add dedicated schema for X1E80100 PMIC ARB. This is not the first platform to introduce multiple buses. In fact, all platforms that implement the version 7 for the SPMI PMIC arbiter have multiple buses. Since the compatible should not be version based, the platform specific one is used. The X1E80100 platform is the first platform to really need the second master, as all the available boards have the PMICs that provide the eUSB2 repeater on the second bus. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240417-spmi-multi-master-support-v10-1-5b= c6d322e266@linaro.org Signed-off-by: Stephen Boyd --- .../spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/qcom,x1e80100-sp= mi-pmic-arb.yaml diff --git a/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic= -arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-= arb.yaml new file mode 100644 index 000000000000..a28b70fb330a --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.ya= ml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7) + +maintainers: + - Stephen Boyd + +description: | + The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI + controller with wrapping arbitration logic to allow for multiple on-chip + devices to control up to 2 SPMI separate buses. + + The PMIC Arbiter can also act as an interrupt controller, providing inte= rrupts + to slave devices. + +properties: + compatible: + const: qcom,x1e80100-spmi-pmic-arb + + reg: + items: + - description: core registers + - description: tx-channel per virtual slave registers + - description: rx-channel (called observer) per virtual slave regist= ers + + reg-names: + items: + - const: core + - const: chnls + - const: obsrvr + + ranges: true + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + qcom,ee: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: > + indicates the active Execution Environment identifier + + qcom,channel: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: > + which of the PMIC Arb provided channels to use for accesses + +patternProperties: + "^spmi@[a-f0-9]+$": + type: object + $ref: /schemas/spmi/spmi.yaml + unevaluatedProperties: false + + properties: + reg: + items: + - description: configuration registers + - description: interrupt controller registers + + reg-names: + items: + - const: cnfg + - const: intr + + interrupts: + maxItems: 1 + + interrupt-names: + const: periph_irq + + interrupt-controller: true + + '#interrupt-cells': + const: 4 + description: | + cell 1: slave ID for the requested interrupt (0-15) + cell 2: peripheral ID for requested interrupt (0-255) + cell 3: the requested peripheral interrupt (0-7) + cell 4: interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + +required: + - compatible + - reg-names + - qcom,ee + - qcom,channel + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + spmi: arbiter@c400000 { + compatible =3D "qcom,x1e80100-spmi-pmic-arb"; + reg =3D <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>; + reg-names =3D "core", "chnls", "obsrvr"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg =3D <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names =3D "cnfg", "intr"; + + interrupt-names =3D "periph_irq"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + }; + }; --=20 https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/ https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git