From nobody Wed Dec 17 13:54:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88A01AD5D; Tue, 7 May 2024 10:43:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715078597; cv=none; b=GIrXmbhCplvGaALoc4P8pGq1COajmPleT8PgMr6FAE0QMOSRr/muayWgYPs3TPK7xUnQp6A8s2TgBxAhLMOq/TO1nDbFIJuyyCdE2LLt1KJJJ6BLQm+CouVQglM1USpTAKQAi0LUR8yU2lRwgbKDubMgJjJWc/qyMH3hV5F51dw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715078597; c=relaxed/simple; bh=+TRQfeq8Nw7b6DoQt3C1fHE3AuYEeUkPp5208iLu1YA=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=YhBTLQwhZxHARfcPFcoFEOfkChNoYPOJWvPdZjoTAqkBg9K8HKYu2QX5mxa+w306lWWWNdiHfSMJD7fHZXkV5flhLHH4Ub0W0B9JQK4L7+uy3+P83gHSa46wJGUSXH31YIYEOFAt+LQlh6xj5BdP5+vK3tFNFvr8viylPCofejU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TPJNzY3H; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TPJNzY3H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715078596; x=1746614596; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=+TRQfeq8Nw7b6DoQt3C1fHE3AuYEeUkPp5208iLu1YA=; b=TPJNzY3HVrt/y16SROkopaGKy8UdProYDKJCfpZkhpC2VeT7FslxMBt5 KwbU86rIQY0OdYMINHltm8JYaDf/x5MI8cCGAPVdOueLa4u86yeUWWceg oPx5dmqbWS1iBukos4VtmzSem7pFpJh8R+mqxUygY5hKzlBmgikVyuktd crslEGfAS4Pzt19yPEPhr/G4lLMj1e1X+E2F9OfTBcZMWSDSYjZjak27k ma64nmxGuoRN+DZ+DisPHEdBEd1QHMtelFfT2SPu16Tav5UwNYQt3Fvnn SOoneBA8e9RcrM571GYTYa7scpcFs+HvVjeZmQa2wkQpWuSR5SSDl0Oxb g==; X-CSE-ConnectionGUID: nsCoCiQERXaGxwvUBTLDJw== X-CSE-MsgGUID: AkjPtzKvT82JSjy93C4i5w== X-IronPort-AV: E=McAfee;i="6600,9927,11065"; a="36245724" X-IronPort-AV: E=Sophos;i="6.07,261,1708416000"; d="scan'208";a="36245724" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 03:43:15 -0700 X-CSE-ConnectionGUID: l7+b9JCCSqubT7cmWJcHIg== X-CSE-MsgGUID: euSulxasRP6BMwVw+2KcCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,261,1708416000"; d="scan'208";a="33312129" Received: from xiao-desktop.sh.intel.com ([10.239.46.158]) by orviesa004.jf.intel.com with ESMTP; 07 May 2024 03:43:09 -0700 From: Xiao Wang To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, luke.r.nels@gmail.com, xi.wang@gmail.com, bjorn@kernel.org Cc: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, eddyz87@gmail.com, song@kernel.org, yonghong.song@linux.dev, john.fastabend@gmail.com, kpsingh@kernel.org, sdf@google.com, haoluo@google.com, jolsa@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, pulehui@huawei.com, haicheng.li@intel.com, Xiao Wang Subject: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension Date: Tue, 7 May 2024 18:45:28 +0800 Message-Id: <20240507104528.435980-1-xiao.w.wang@intel.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Zba extension provides add.uw insn which can be used to implement zext.w with rs2 set as ZERO. Signed-off-by: Xiao Wang --- arch/riscv/Kconfig | 19 +++++++++++++++++++ arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6bec1bce6586..0679127cc0ea 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE preemption. Enabling this config will result in higher memory consumption due to the allocation of per-task's kernel Vector context. =20 +config TOOLCHAIN_HAS_ZBA + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zba) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zba) + depends on LLD_VERSION >=3D 150000 || LD_VERSION >=3D 23900 + depends on AS_HAS_OPTION_ARCH + config TOOLCHAIN_HAS_ZBB bool default y @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) depends on AS_HAS_OPTION_ARCH =20 +config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" + depends on TOOLCHAIN_HAS_ZBA + depends on RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the ZBA + extension (address generation acceleration) and enable its usage. + + If you don't know what to do here, say Y. + config RISCV_ISA_ZBB bool "Zbb extension support for bit manipulation instructions" depends on TOOLCHAIN_HAS_ZBB diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h index f4b6b3b9edda..18a7885ba95e 100644 --- a/arch/riscv/net/bpf_jit.h +++ b/arch/riscv/net/bpf_jit.h @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) return IS_ENABLED(CONFIG_RISCV_ISA_C); } =20 +static inline bool rvzba_enabled(void) +{ + return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RIS= CV_ISA_EXT_ZBA); +} + static inline bool rvzbb_enabled(void) { return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RIS= CV_ISA_EXT_ZBB); @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2) return rv_css_insn(0x7, imm, rs2, 0x2); } =20 +/* RV64-only ZBA instructions. */ + +static inline u32 rvzba_zextw(u8 rd, u8 rs1) +{ + /* add.uw rd, rs1, ZERO */ + return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b); +} + #endif /* __riscv_xlen =3D=3D 64 */ =20 /* Helper functions that emit RVC instructions when possible. */ @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct r= v_jit_context *ctx) =20 static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx) { + if (rvzba_enabled()) { + emit(rvzba_zextw(rd, rs), ctx); + return; + } + emit_slli(rd, rs, 32, ctx); emit_srli(rd, rd, 32, ctx); } --=20 2.25.1