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charset="utf-8" From: Matt Ranostay Add support for the USB 3.0 controller Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Tested-by: Andrew Halaney # k3-j784s4-evm --- Changes since v1: ---------------- * Node name 'cdns-usb' renamed to 'usb'=20 Changes since v1: ---------------- * No change v2: https://lore.kernel.org/all/20240506052044.8228-2-r-gunasekaran@ti.com/ v1: https://lore.kernel.org/all/20240502053615.29514-2-r-gunasekaran@ti.com/ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 6a4554c6c9c1..0401043791f8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -75,6 +75,13 @@ , ; }; + + usb_serdes_mux: mux-controller@4000 { + compatible =3D "reg-mux"; + reg =3D <0x4000 0x4>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ + }; }; =20 gic500: interrupt-controller@1800000 { @@ -568,6 +575,38 @@ status =3D "disabled"; }; =20 + usbss0: usb@4104000 { + bootph-all; + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x4104000 0x00 0x100>; + dma-coherent; + power-domains =3D <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 398 21>, <&k3_clks 398 2>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 398 21>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 398 22>; /* HFOSC0 */ + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; /* Needs lane config */ + + usb0: usb@6000000 { + bootph-all; + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ + interrupt-names =3D "host", + "peripheral", + "otg"; + }; + }; + main_i2c0: i2c@2000000 { compatible =3D "ti,j721e-i2c", "ti,omap4-i2c"; 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Tue, 7 May 2024 04:55:57 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 7 May 2024 04:55:56 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 7 May 2024 04:55:57 -0500 Received: from uda0500640.dal.design.ti.com (uda0500640.dhcp.ti.com [172.24.227.88]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4479tjn9007273; Tue, 7 May 2024 04:55:53 -0500 From: Ravi Gunasekaran To: , CC: , , , , , , , , , Subject: [PATCH v3 2/2] arm64: dts: ti: k3-j784s4-evm: Enable USB3 support Date: Tue, 7 May 2024 15:25:45 +0530 Message-ID: <20240507095545.8210-3-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240507095545.8210-1-r-gunasekaran@ti.com> References: <20240507095545.8210-1-r-gunasekaran@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matt Ranostay The board uses SERDES0 Lane 3 for USB3 IP. So update the SerDes lane info for USB. Add the pin mux data and enable USB3 support. Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Tested-by: Andrew Halaney # k3-j784s4-evm --- Changes since v2: ----------------- * No change Changes since v1: ---------------- * Fixed dtbs_check warning by renaming 'main-usbss0-pins-default' to 'main-usbss0-default-pins' v2: https://lore.kernel.org/all/20240506052044.8228-3-r-gunasekaran@ti.com/ v1: https://lore.kernel.org/all/20240502053615.29514-3-r-gunasekaran@ti.com/ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index d511b25d62e3..a2d3cba0423e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -336,6 +336,13 @@ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ >; }; + + main_usbss0_pins_default: main-usbss0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; =20 &wkup_pmx2 { @@ -1041,6 +1048,40 @@ <&k3_clks 218 22>; }; =20 +&serdes0 { + status =3D "okay"; + + serdes0_usb_link: phy@3 { + reg =3D <3>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&usb_serdes_mux { + idle-states =3D <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + status =3D "okay"; + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode =3D "otg"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb_link>; + phy-names =3D "cdns3,usb3-phy"; +}; + &serdes_wiz4 { status =3D "okay"; }; --=20 2.17.1