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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id x2-20020a056402414200b00572cf08369asm5621928eda.23.2024.05.07.07.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:14:47 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 07 May 2024 15:14:48 +0100 Subject: [PATCH 5/5] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org> References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.12.4 While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy instead. I stumbled across this while adding support for the Google Tensor gs101, but this should apply to E850 just the same. Do so. Fixes: 691525074db9 ("phy: exynos5-usbdrd: Add Exynos850 support") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Peter Griffin --- Feel free to drop the Fixes: if you think that is unwarranted here. v2: add missing bitfield.h include (seems this is implied on some platforms, but not on others) --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 1da7a4881f72..15be966b50ae 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -8,6 +8,7 @@ * Author: Vivek Gautam */ =20 +#include #include #include #include @@ -141,6 +142,9 @@ #define CLKRST_PORT_RST BIT(1) #define CLKRST_LINK_SW_RST BIT(0) =20 +#define EXYNOS850_DRD_SSPPLLCTL 0x30 +#define SSPPLLCTL_FSEL GENMASK(2, 0) + #define EXYNOS850_DRD_UTMI 0x50 #define UTMI_FORCE_VBUSVALID BIT(5) #define UTMI_FORCE_BVALID BIT(4) @@ -773,6 +777,31 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_= usbdrd_phy *phy_drd) reg |=3D HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; writel(reg, regs_base + EXYNOS850_DRD_HSP); =20 + reg =3D readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); + reg &=3D ~SSPPLLCTL_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |=3D FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); + /* Power up PHY analog blocks */ reg =3D readl(regs_base + EXYNOS850_DRD_HSP_TEST); reg &=3D ~HSP_TEST_SIDDQ; --=20 2.45.0.rc1.225.g2a3ae87e7f-goog