From nobody Wed Dec 17 17:30:37 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345BD14E2E0; Tue, 7 May 2024 09:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715075868; cv=none; b=fR/Ps+kuttccvj6iWfuToQb1Fzzc8yulTORCNTK7huHPkaqEpjCbPdavy8Yeklc+aN1jhGgTKHDheVvNVYEA0YCAaw28c+ro5Pp02iwPXaIcIkTvox+SONhAyrmol5oT+ReL/CGi/n8oXxuLgCBztJJfiZ/lTR4lMekUAi9BU14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715075868; c=relaxed/simple; bh=RmxKI+6iXMp4T21o/wGUBSdP83ygzbY8wcopsHrQM1Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DG97RzOND15D6pTgTqcqhcntfrwjPI7jvWpzw0u6cBsdOKT9buIaRRV1V4aGWOUfr4PlqoKMZfZSmf/Z06wv1265inpGBAqbvNd8/BLiOpNn1z5NuJU10nwWJcZ7XgPWoUF7pqfyjR/ZUwDKOCDaClxMFXkQpMw+JJ9ikV2JjHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q3qwqrRW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q3qwqrRW" Received: by smtp.kernel.org (Postfix) with ESMTPS id CA945C3277B; Tue, 7 May 2024 09:57:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715075867; bh=RmxKI+6iXMp4T21o/wGUBSdP83ygzbY8wcopsHrQM1Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Q3qwqrRWOwlGCdDW1b6I6ZhLSxdWrkAHSfjje2XHlGM4zjgkjgtU1uTsEUF6s3zMU sZq+TKG4C++vXo/EgU2HPK3099Bj25Ovl7RsNG4SDlGe3MXlbm/FbcR9z5fZHSEKan 0CfQ1AAHbGvz//06M2mWoi/jcG3Hyq7uLrjxLGDxS6iCCCdQqSPpttncHVTJM0ek9o ob/sZS1IH0yNSc16KcdIN/8xOmRreSZeSVrsmr9Qv4KbVlkSpWYl0uKZLjyc7dsWyx CsGl8Ty2o4k6orbEzXJyxHnXBDfSWR3AFaFpCycecPGmRBIGib31Pa5aSbr5+P3SuE bbjtkxy3fPosg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2EEBC25B4F; Tue, 7 May 2024 09:57:47 +0000 (UTC) From: =?utf-8?q?Noralf_Tr=C3=B8nnes_via_B4_Relay?= Date: Tue, 07 May 2024 11:57:26 +0200 Subject: [PATCH 1/5] dt-bindings: display: panel: mipi-dbi-spi: Add a pixel format property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240507-panel-mipi-dbi-rgb666-v1-1-6799234afa3e@tronnes.org> References: <20240507-panel-mipi-dbi-rgb666-v1-0-6799234afa3e@tronnes.org> In-Reply-To: <20240507-panel-mipi-dbi-rgb666-v1-0-6799234afa3e@tronnes.org> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kamlesh Gurudasani , Tommaso Merciai , =?utf-8?q?Noralf_Tr=C3=B8nnes?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715075866; l=4065; i=noralf@tronnes.org; s=20221122; h=from:subject:message-id; bh=TowoM29hMjnIJtoKHYMSjqkFzd4MbRIXH0taXmdrDS8=; b=f1YtxheYlm3GPmINUTjxlecAhf/ja6lIfwSBbF65EtVcpjP5zShveG3KXsE1mHgOeUyMVIB2o DiV3bFyMqcgBikQ9ZxIDN19OYa91ynmDhxdggFedtjKo528e+3UTfRY X-Developer-Key: i=noralf@tronnes.org; a=ed25519; pk=0o9is4iddvvlrY3yON5SVtAbgPnVs0LfQsjfqR2Hvz8= X-Endpoint-Received: by B4 Relay for noralf@tronnes.org/20221122 with auth_id=8 X-Original-From: =?utf-8?q?Noralf_Tr=C3=B8nnes?= Reply-To: noralf@tronnes.org From: Noralf Tr=C3=B8nnes The MIPI DBI 2.0 specification (2005) lists only two pixel formats for the Type C Interface (SPI) and that is 3-bits/pixel RGB111 with 2 options for bit layout. For Type A and B (parallel) the following formats are listed: RGB332, RGB444, RGB565, RGB666 and RGB888 (some have 2 options for the bit layout). Many MIPI DBI compatible controllers support all interface types on the same chip and often the manufacturers have chosen to provide support for the Type A/B interface pixel formats also on the Type C interface. Some chips provide many pixel formats with optional bit layouts over SPI, but the most common by far are RGB565 and RGB666. So even if the specification doesn't list these formats for the Type C interface, the industry has chosen to include them. The MIPI DCS specification lists the standard commands that can be sent over the MIPI DBI interface. The set_address_mode (36h) command has one bit in the parameter that controls RGB/BGR order: This bit controls the RGB data latching order transferred from the peripheral=E2=80=99s frame memory to the display device. This means that each supported RGB format also has a BGR variant. Based on this rationale document the following pixel formats describing the bit layout going over the wire: - RGB111 (option 1): x2r1g1b1r1g1b1 (2 pixels per byte) - BGR111 (option 1): x2b1g1r1b1g1r1 (2 pixels per byte) - RGB111 (option 2): x1r1g1b1x1r1g1b1 (2 pixels per byte) - BGR111 (option 2): x1b1g1r1x1b1g1r1 (2 pixels per byte) - RGB565: r5g6b5 (2 bytes) - BGR565: b5g6r5 (2 bytes) - RGB666: r6x2g6x2b6x2 (3 bytes) - BGR666: b6x2g6x2r6x2 (3 bytes) (x: don't care) Signed-off-by: Noralf Tr=C3=B8nnes --- .../bindings/display/panel/panel-mipi-dbi-spi.yaml | 31 ++++++++++++++++++= ++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi= -spi.yaml b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-= spi.yaml index e808215cb39e..dac8f9af100e 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.ya= ml +++ b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.ya= ml @@ -50,6 +50,12 @@ description: | | Command or data | || =20 + The standard defines one pixel format for type C: RGB111. The industry + however has decided to provide the type A/B interface pixel formats also= on + the Type C interface and most common among these are RGB565 and RGB666. + The MIPI DCS command set_address_mode (36h) has one bit that controls RG= B/BGR + order. This gives each supported RGB format a BGR variant. + The panel resolution is specified using the panel-timing node properties hactive (width) and vactive (height). The other mandatory panel-timing properties should be set to zero except clock-frequency which can be @@ -90,6 +96,29 @@ properties: =20 spi-3wire: true =20 + format: + description: > + Pixel format in bit order as going on the wire: + * `x2r1g1b1r1g1b1` - RGB111, 2 pixels per byte + * `x2b1g1r1b1g1r1` - BGR111, 2 pixels per byte + * `x1r1g1b1x1r1g1b1` - RGB111, 2 pixels per byte + * `x1b1g1r1x1b1g1r1` - BGR111, 2 pixels per byte + * `r5g6b5` - RGB565, 2 bytes + * `b5g6r5` - BGR565, 2 bytes + * `r6x2g6x2b6x2` - RGB666, 3 bytes + * `b6x2g6x2r6x2` - BGR666, 3 bytes + This property is optional for backwards compatibility and `r5g6b5` is + assumed in its absence. + enum: + - x2r1g1b1r1g1b1 + - x2b1g1r1b1g1r1 + - x1r1g1b1x1r1g1b1 + - x1b1g1r1x1b1g1r1 + - r5g6b5 + - b5g6r5 + - r6x2g6x2b6x2 + - b6x2g6x2r6x2 + required: - compatible - reg @@ -116,6 +145,8 @@ examples: reset-gpios =3D <&gpio 25 GPIO_ACTIVE_HIGH>; write-only; =20 + format =3D "r5g6b5"; + backlight =3D <&backlight>; =20 width-mm =3D <35>; --=20 2.45.0