From nobody Wed Dec 17 17:27:58 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA8A9143C4E for ; Mon, 6 May 2024 12:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997763; cv=none; b=DC1C2dw70/0KhbPWfDWgXm7OCcK7HryXVwSmhdd+gTPWDpRQLIjoBSPaSmunMHENhhcTrOXSokIRL6/tHe+Sd4DYmGSorR8CBKOR0UbYttkJWdXF2+AtYNahNqZyaLfgrDjeAmf1XCQu5vbZF5bWZ9QTevimQphZ9vaLGOMJ3Vc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997763; c=relaxed/simple; bh=UWI7SZcBOgCHA8M9jnJU6XD2NRmEw9ukmCbYEbQq3A4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LQTzUvuQAisi+2H4Qr6STq2CGWb9dUVBmSCpoHlzAHvpTV2LZ8lx6Kj2vs5J9jGXLcPNANzLXR0qPRBBXeRnG00QiXADamJZgyMHOWf4HQRFmOU0ldoNonPaKDjsgBiiRLPYxs6TfZ5jc/ya6pY7jrVfRSwhgt07nRJqPclQeCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YCyP90g5; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YCyP90g5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714997762; x=1746533762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UWI7SZcBOgCHA8M9jnJU6XD2NRmEw9ukmCbYEbQq3A4=; b=YCyP90g5jShosYMbGTwgEXoXTcXK05SWfcEulNIut1H71uYKlyL4Zs2e rfvClZFOpuw9OClc4hpjTDZxqP3A61lp0oaPw/gNgUZ5RjHn13HpeS6z7 4k41oV3lFYMMQyAws267bf3W3znGPPOLD4bMqhlWbjLubtUehIhLBpkJN M6V1vrZsWykHkyZkgKDhYkhsDJhgk5eFBeKBwP7G287YNAleQatuAcvOm Fl3WX7JTU9cebwN1ftz0WyvoOhM8w7s+TU149cAgz+FwEAD1lOZ7ICtC8 Y6zlqdkxRoguskiTkPsDR7oXbCcmuIgzkMTix2t0maAAycTj8CPrLd9pL A==; X-CSE-ConnectionGUID: CyzDtEFsSXiqf8VWlYY4aQ== X-CSE-MsgGUID: sdYBnUS+RXCFzCw1YC3HFA== X-IronPort-AV: E=McAfee;i="6600,9927,11064"; a="14544143" X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="14544143" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 05:15:58 -0700 X-CSE-ConnectionGUID: OKLBKEwtQieC/6PqpPobyQ== X-CSE-MsgGUID: irIzFggdSm6mCpgEpf1how== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="32951441" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa004.jf.intel.com with ESMTP; 06 May 2024 05:15:56 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id DC7D5161; Mon, 06 May 2024 15:15:54 +0300 (EEST) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Kai Huang , Kuppuswamy Sathyanarayanan Subject: [PATCHv3 1/4] x86/tdx: Factor out TD metadata write TDCALL Date: Mon, 6 May 2024 15:15:50 +0300 Message-ID: <20240506121553.3824346-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> References: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TDG_VM_WR TDCALL is used to ask the TDX module to change some TD-specific VM configuration. There is currently only one user in the kernel of this TDCALL leaf. More will be added shortly. Refactor to make way for more users of TDG_VM_WR who will need to modify other TD configuration values. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan --- arch/x86/coco/tdx/tdx.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 59776ce1c1d7..b926221f1264 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -77,6 +77,18 @@ static inline void tdcall(u64 fn, struct tdx_module_args= *args) panic("TDCALL %lld failed (Buggy TDX module!)\n", fn); } =20 +/* Write TD-scoped metadata */ +static inline u64 tdg_vm_wr(u64 field, u64 value, u64 mask) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + .r8 =3D value, + .r9 =3D mask, + }; + + return __tdcall(TDG_VM_WR, &args); +} + /** * tdx_mcall_get_report0() - Wrapper to get TDREPORT0 (a.k.a. TDREPORT * subtype 0) using TDG.MR.REPORT TDCALL. @@ -902,10 +914,6 @@ static void tdx_kexec_unshare_mem(void) =20 void __init tdx_early_init(void) { - struct tdx_module_args args =3D { - .rdx =3D TDCS_NOTIFY_ENABLES, - .r9 =3D -1ULL, - }; u64 cc_mask; u32 eax, sig[3]; =20 @@ -924,7 +932,7 @@ void __init tdx_early_init(void) cc_set_mask(cc_mask); =20 /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ - tdcall(TDG_VM_WR, &args); + tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); =20 /* * All bits above GPA width are reserved and kernel treats shared bit --=20 2.43.0 From nobody Wed Dec 17 17:27:58 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C377E143C46 for ; Mon, 6 May 2024 12:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997763; cv=none; b=Lv8I+r6H0tKDgN8PiaVwRNu5YW3W9bzknnx/coqY7qWBJllOEYxAxc6m49V3BUVmuYuQ4ZI61b5fWnnaHBLhrufwb8TAI6Vzj6LH1vOSeyPlXS1Eybi5FXVdY6PFX7uYWYfOr9YZnRzuB25/qriEoQY3RDTM8MstXQk/HSFIIpc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997763; c=relaxed/simple; bh=thgtjAPUlcHd9NBfHBwdSKUpdpm4qAYPqeeCKH2/TjY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=In7zCHlfkzFUvo4DDN8XIyh+s6uRDIs/XNusLH/Tovp067ZhulSl2MfmYSTJ45bzxPuB0wq8Q1/K8woDHs1eNpHrsOd5ByXG4HUn6vl69Hn8hcWQmix4MJjgjRBhUMzO2WV6dyRx1PJckUPYlgbrBONEeeTsmN432oJlZS1rA2w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CRYep0uf; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CRYep0uf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714997761; x=1746533761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=thgtjAPUlcHd9NBfHBwdSKUpdpm4qAYPqeeCKH2/TjY=; b=CRYep0ufX1NCImI5vmfj/9VtOefhcD2YnFuOmGRNyOLdykv7rwXcgHZN ndsvdKoiHd3wyiGvpRp/2lyh5bwpnev8O3TlS3mBsym9LBePjIj+l2sGx EKb1ckCuxKq9pe/cGRxWDAUIrZXgWHvMYW0c9iBpXujF/nk1ngoZFfWqV XzSsgG10vefryVhwMXHBM6EyhTsst8nbfsqrPgUnWjwz8U3Z7ID0+4Iq9 jg1ebV12p8RyGyHm+PQVCN/e28BX+E1zvAn8cthbN8HVaUTq8OmmMH992 9QScUc5g2iP+vYrUFNCUGlkKBxqY5R2aQzl2cbAR8Nf6t8LsUUrA/AoL+ g==; X-CSE-ConnectionGUID: cfYnQHlNRsyTQRdA08uf2A== X-CSE-MsgGUID: MAJQqZTfSe6KyE8kcNNpog== X-IronPort-AV: E=McAfee;i="6600,9927,11064"; a="11271853" X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="11271853" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 05:15:58 -0700 X-CSE-ConnectionGUID: OCeGGIsWT0aQrv1fu/2uwg== X-CSE-MsgGUID: +V2NucTLRbG9e9qKnnRqMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="28140603" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa007.fm.intel.com with ESMTP; 06 May 2024 05:15:56 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id E931F2DC; Mon, 06 May 2024 15:15:54 +0300 (EEST) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Kuppuswamy Sathyanarayanan , Kai Huang Subject: [PATCHv3 2/4] x86/tdx: Rename tdx_parse_tdinfo() to tdx_setup() Date: Mon, 6 May 2024 15:15:51 +0300 Message-ID: <20240506121553.3824346-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> References: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename tdx_parse_tdinfo() to tdx_setup() and move setting NOTIFY_ENABLES there. The function will be extended to adjust TD configuration. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Kai Huang --- arch/x86/coco/tdx/tdx.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index b926221f1264..964149d3be5e 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -179,7 +179,7 @@ static void __noreturn tdx_panic(const char *msg) __tdx_hypercall(&args); } =20 -static void tdx_parse_tdinfo(u64 *cc_mask) +static void tdx_setup(u64 *cc_mask) { struct tdx_module_args args =3D {}; unsigned int gpa_width; @@ -204,6 +204,9 @@ static void tdx_parse_tdinfo(u64 *cc_mask) gpa_width =3D args.rcx & GENMASK(5, 0); *cc_mask =3D BIT_ULL(gpa_width - 1); =20 + /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ + tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); + /* * The kernel can not handle #VE's when accessing normal kernel * memory. Ensure that no #VE will be delivered for accesses to @@ -928,11 +931,11 @@ void __init tdx_early_init(void) setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); =20 cc_vendor =3D CC_VENDOR_INTEL; - tdx_parse_tdinfo(&cc_mask); - cc_set_mask(cc_mask); =20 - /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ - tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); + /* Configure the TD */ + tdx_setup(&cc_mask); + + cc_set_mask(cc_mask); =20 /* * All bits above GPA width are reserved and kernel treats shared bit --=20 2.43.0 From nobody Wed Dec 17 17:27:58 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28FDC143896 for ; Mon, 6 May 2024 12:15:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997761; cv=none; b=XbE4257pTvrV0cMCTQjSxGywDcNZTEs5HtNquaUu79Epunw6KtaPETtTlzgDMrUPLoFP2dKCAToKRqSMrjEAiEMWUvcvYtUuoovfM9Re/IxX8eJL924E0CrkQ2vejPqcm0EAM7TP79L6lmQ5GMSthFDcOm8/2fvqdLyBUMz6M6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997761; c=relaxed/simple; bh=9oUZ3YbVKWgyrNdYFYkzttpGYTGgf33f/fi108YIgTc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EwYSbV8XVIol+IOUG16UmnP6d7W+R2ksDeysDwC1oZ3GbF4vWVBfQPvTGu4QiT650Xwg2wMjt+YGhBSCWrSxwjN36LXrUTscEKU/d0A1kXKzWfqhJMuBlwuoTROw/u4CF8IDrB9aWH+37Fp8uGN96Wgr9JgMDF4VYqv7/YHIPoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E3hHVnNO; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E3hHVnNO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714997759; x=1746533759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9oUZ3YbVKWgyrNdYFYkzttpGYTGgf33f/fi108YIgTc=; b=E3hHVnNOP1b3NbIuUfe5GyMn2bK2yGEGvXXBqKRFAK8fNfxfkyjFM8w+ W4PcC4gSgXTs8sTbRYVS69aazZB+uYnpIXnsBucJHnMuX4igzlh8pVEBh Ov5iLy73dPQh+qwyb9uC274aQyrpH3ZzyxalfpfNBhz6jRntER8E+AbRk gaho2RLsGU2sD1XHq8NexXyzZAij8sY2K/8jMbMxTBeWHCeNVES88qJ/K pLHMyqhT+qowjGiA4Y9Zhbu1PiKTCx2XN5QMo/CFRmHlhn7IAYUaSQcsy hvkW5CDtx/d0JMaAHCaCIrp5Wz0XgaEVjz7M1LPBS2fceSTQCWwRT5R2A A==; X-CSE-ConnectionGUID: 4mHHkDfZQZWoSvifrzxalA== X-CSE-MsgGUID: 3dYsPVMFRCaB2Nj2H5BRcw== X-IronPort-AV: E=McAfee;i="6600,9927,11064"; a="14544136" X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="14544136" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 05:15:58 -0700 X-CSE-ConnectionGUID: QM3xDSqWSwqxbqi5Q/3QLA== X-CSE-MsgGUID: XtlBxlu2Sfi+nNmPODLuAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="32951425" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa004.jf.intel.com with ESMTP; 06 May 2024 05:15:56 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 01F573DC; Mon, 06 May 2024 15:15:54 +0300 (EEST) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCHv3 3/4] x86/tdx: Handle PENDING_EPT_VIOLATION_V2 Date: Mon, 6 May 2024 15:15:52 +0300 Message-ID: <20240506121553.3824346-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> References: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A "SEPT #VE" occurs when a TDX guest touches memory that is not properly mapped into the "secure EPT". This can be the result of hypervisor attacks or bugs, *OR* guest bugs. Most notably, buggy guests might touch unaccepted memory for lots of different memory safety bugs like buffer overflows. TDX guests do not want to continue in the face of hypervisor attacks or hypervisor bugs. They want to terminate as fast and safely as possible. This is done by checking SEPT_VE_DISABLE attribute. The attribute controlled by VMM on TD creation and the guest only consumes it. Newer TDX module versions have PENDING_EPT_VIOLATION_V2 feature that allows TD to control whether access to memory that is not properly mapped into the "secure EPT" causes #VE. Try to disable #VE on SEPT violation, if PENDING_EPT_VIOLATION_V2 is supported. Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx/tdx.c | 102 ++++++++++++++++++++++++++++-- arch/x86/include/asm/shared/tdx.h | 18 +++++- 2 files changed, 114 insertions(+), 6 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 964149d3be5e..6124d86e0b1d 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -77,6 +77,20 @@ static inline void tdcall(u64 fn, struct tdx_module_args= *args) panic("TDCALL %lld failed (Buggy TDX module!)\n", fn); } =20 +/* Read TD-scoped metadata */ +static inline u64 tdg_vm_rd(u64 field, u64 *value) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + }; + u64 ret; + + ret =3D __tdcall_ret(TDG_VM_RD, &args); + *value =3D args.r8; + + return ret; +} + /* Write TD-scoped metadata */ static inline u64 tdg_vm_wr(u64 field, u64 value, u64 mask) { @@ -89,6 +103,20 @@ static inline u64 tdg_vm_wr(u64 field, u64 value, u64 m= ask) return __tdcall(TDG_VM_WR, &args); } =20 +/* Read system-wide TDX metadata */ +static inline u64 tdg_sys_rd(u64 field, u64 *value) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + }; + u64 ret; + + ret =3D __tdcall_ret(TDG_SYS_RD, &args); + *value =3D args.r8; + + return ret; +} + /** * tdx_mcall_get_report0() - Wrapper to get TDREPORT0 (a.k.a. TDREPORT * subtype 0) using TDG.MR.REPORT TDCALL. @@ -179,11 +207,54 @@ static void __noreturn tdx_panic(const char *msg) __tdx_hypercall(&args); } =20 +/* + * PENDING_EPT_VIOLATION_V2 feature allows TDX guest to control if it want= s to + * receive SEPT violation #VEs. + * + * Check if the feature is available and disable SEPT #VE if possible. + */ +static int try_to_disable_sept_ve(u64 features0, u64 td_attr) +{ + u64 config, controls; + + /* Does the TDX module support flexible SEPT #VE */ + if (!(features0 & TDX_FEATURES0_PENDING_EPT_VIOLATION_V2)) + return -EOPNOTSUPP; + + /* Read TD config flags */ + if (tdg_vm_rd(TDCS_CONFIG_FLAGS, &config)) + return -EIO; + + /* Is this TD allowed to disable SEPT #VE */ + if (!(config & TDCS_CONFIG_FLEXIBLE_PENDING_VE)) + return -EOPNOTSUPP; + + if (tdg_vm_rd(TDCS_TD_CTLS, &controls)) + return -EIO; + + /* Check if SEPT #VE has been disabled before us */ + if (controls & TD_CTLS_PENDING_VE_DISABLE) + return 0; + + /* Keep #VE's enabled for splats in debugging environments */ + if (td_attr & ATTR_DEBUG) + return -EOPNOTSUPP; + + /* Try to disable */ + if (tdg_vm_wr(TDCS_TD_CTLS, TD_CTLS_PENDING_VE_DISABLE, + TD_CTLS_PENDING_VE_DISABLE)) { + return -EIO; + } + + return 0; +} + static void tdx_setup(u64 *cc_mask) { struct tdx_module_args args =3D {}; unsigned int gpa_width; - u64 td_attr; + u64 features0, td_attr; + bool sept_ve_disabled; =20 /* * TDINFO TDX module call is used to get the TD execution environment @@ -204,19 +275,40 @@ static void tdx_setup(u64 *cc_mask) gpa_width =3D args.rcx & GENMASK(5, 0); *cc_mask =3D BIT_ULL(gpa_width - 1); =20 + td_attr =3D args.rdx; + /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); =20 + if (tdg_sys_rd(TDX_FEATURES0, &features0)) { + /* + * TDX 1.0 does not have the field. No optional features are + * supported. + */ + features0 =3D 0; + } + /* * The kernel can not handle #VE's when accessing normal kernel * memory. Ensure that no #VE will be delivered for accesses to * TD-private memory. Only VMM-shared memory (MMIO) will #VE. + * + * Try to disable SEPT #VE if possible. */ - td_attr =3D args.rdx; - if (!(td_attr & ATTR_SEPT_VE_DISABLE)) { - const char *msg =3D "TD misconfiguration: SEPT_VE_DISABLE attribute must= be set."; + if (!try_to_disable_sept_ve(features0, td_attr)) { + sept_ve_disabled =3D true; + } else { + /* + * If SEPT #VE cannot be disabled from guest side, check + * TD attribute if the #VE going to be delivered. + */ + sept_ve_disabled =3D td_attr & ATTR_SEPT_VE_DISABLE; + } =20 - /* Relax SEPT_VE_DISABLE check for debug TD. */ + if (!sept_ve_disabled) { + const char *msg =3D "TD misconfiguration: SEPT #VE has to be disabled"; + + /* Relax SEPT #VE disable check for debug TD. */ if (td_attr & ATTR_DEBUG) pr_warn("%s\n", msg); else diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index fdfd41511b02..282497d2964b 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -16,11 +16,27 @@ #define TDG_VP_VEINFO_GET 3 #define TDG_MR_REPORT 4 #define TDG_MEM_PAGE_ACCEPT 6 +#define TDG_VM_RD 7 #define TDG_VM_WR 8 +#define TDG_SYS_RD 11 =20 -/* TDCS fields. To be used by TDG.VM.WR and TDG.VM.RD module calls */ +/* TDX Global Metadata. To be used by TDG.SYS.RD */ +#define TDX_FEATURES0 0x0A00000300000008 + +/* TDX TD-Scope Metadata. To be used by TDG.VM.WR and TDG.VM.RD */ +#define TDCS_CONFIG_FLAGS 0x1110000300000016 +#define TDCS_TD_CTLS 0x1110000300000017 #define TDCS_NOTIFY_ENABLES 0x9100000000000010 =20 +/* TDX_FEATURES0 bits */ +#define TDX_FEATURES0_PENDING_EPT_VIOLATION_V2 BIT_ULL(16) + +/* TDCS_CONFIG_FLAGS bits */ +#define TDCS_CONFIG_FLEXIBLE_PENDING_VE BIT_ULL(1) + +/* TDCS_TD_CTLS bits */ +#define TD_CTLS_PENDING_VE_DISABLE BIT_ULL(0) + /* TDX hypercall Leaf IDs */ #define TDVMCALL_MAP_GPA 0x10001 #define TDVMCALL_GET_QUOTE 0x10002 --=20 2.43.0 From nobody Wed Dec 17 17:27:58 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB68143898 for ; Mon, 6 May 2024 12:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997762; cv=none; b=eKgnd/1LPIuzGqoK9dnnMIoupeqZY/6WN49augbmqceRsG9BGA2I+KCQ/VYGoQqgIO+JqjXwn/0g9lpbCd+zN5YENlszmCSfy+QCnWY3XVMrH2ay5cZqpQ9TaG1NK/3yrUhssx+yLYXQgwcic3Q5IT/yvjJ34HFMMGPSzT8FwG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714997762; c=relaxed/simple; bh=K+dV6HEn8WSN1OZJCuqaweN1G3AuuzUtKe1m6ZoBwds=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XCGvQQTSk0frTWnEYdxL74+kPY38mdf/GwulxgSedha7jkVWeBh8uRZLkyfHlPLv11UH9TiycP3gHKXkzjysKBTQFO0alXJiHeohow9RbAGOotN93HRmEu5j0kSwhb/iM7qWgHkk34kPCYUATXcGLqBdSsXl6DM3XNIAt18mHnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=n+hPW172; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="n+hPW172" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714997761; x=1746533761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K+dV6HEn8WSN1OZJCuqaweN1G3AuuzUtKe1m6ZoBwds=; b=n+hPW172Irj5s9mTY6i2yvwKWRR+IP0DOGE4d+T/qMqfC4954nQZyTjK AE5FK47oQPZJC2+yaLxTG91I0U2LC8dSJqyBPxqVFddjObMHL1FMkMXN0 JwGjj1tXCNdpdZ6hu2AOKMJi0z9pBmvrI+wN3gB/GXnptQd9cn/TFJKz3 4rWzkw0f19mln+r5AA4TMgjK+Pgr+z6t6eGCL01SIGhK+Gs85O/x1pSJ0 CfPo4jhcCkR7n55aiEHYxvwY372tKCMnYNJGaxY/rkWe3MOOp9EkNYjyT pJf+FQNc8MneXoLFhlm1kOSK+CdvE0kOoZRmIoxf9N9nfv14pZZ3qbNzD g==; X-CSE-ConnectionGUID: dcCazPIqRYaWMm+dlLHshw== X-CSE-MsgGUID: 7Z6G+taISvuaQCBPnoLM4Q== X-IronPort-AV: E=McAfee;i="6600,9927,11064"; a="11271848" X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="11271848" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 05:15:58 -0700 X-CSE-ConnectionGUID: JsTlhZnvTX+Iai9KaWWj5w== X-CSE-MsgGUID: 8M7Q8N/WTtesgOOV+M5sZw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,258,1708416000"; d="scan'208";a="28140600" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa007.fm.intel.com with ESMTP; 06 May 2024 05:15:56 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 0E931452; Mon, 06 May 2024 15:15:55 +0300 (EEST) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCHv3 4/4] x86/tdx: Enable ENUM_TOPOLOGY Date: Mon, 6 May 2024 15:15:53 +0300 Message-ID: <20240506121553.3824346-5-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> References: <20240506121553.3824346-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX 1.0 defines baseline behaviour of TDX guest platform. In TDX 1.0 generates a #VE when accessing topology-related CPUID leafs (0xB and 0x1F) and the X2APIC_APICID MSR. The kernel returns all zeros on CPUID topology. Any complications will cause problems. The ENUM_TOPOLOGY feature allows the VMM to provide topology information to the guest. Enabling the feature eliminates topology-related #VEs: the TDX module virtualizes accesses to the CPUID leafs and the MSR. Enable ENUM_TOPOLOGY if it is available. Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx/tdx.c | 32 +++++++++++++++++++++++++++++++ arch/x86/include/asm/shared/tdx.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 6124d86e0b1d..23c507fa4057 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -249,6 +249,36 @@ static int try_to_disable_sept_ve(u64 features0, u64 t= d_attr) return 0; } =20 +/* + * TDX 1.0 generates a #VE when accessing topology-related CPUID leafs (0x= B and + * 0x1F) and the X2APIC_APICID MSR. The kernel returns all zeros on CPUID = #VEs. + * In practice, this means that the kernel can only boot with a plain topo= logy. + * Any complications will cause problems. + * + * The ENUM_TOPOLOGY feature allows the VMM to provide topology informatio= n. + * Enabling the feature eliminates topology-related #VEs: the TDX module + * virtualizes accesses to the CPUID leafs and the MSR. + * + * Enable ENUM_TOPOLOGY if it is available. + */ +static void enable_cpu_topology_enumeration(u64 features0) +{ + u64 configured; + + /* Does the TDX module support topology enumeration? */ + if (!(features0 & TDX_FEATURES0_ENUM_TOPOLOGY)) + return; + + /* Has the VMM provided a valid topology configuration? */ + if (tdg_vm_rd(TDCS_TOPOLOGY_ENUM_CONFIGURED, &configured) && + configured) { + pr_err("VMM did not configure X2APIC_IDs properly\n"); + return; + } + + tdg_vm_wr(TDCS_TD_CTLS, TD_CTLS_ENUM_TOPOLOGY, TD_CTLS_ENUM_TOPOLOGY); +} + static void tdx_setup(u64 *cc_mask) { struct tdx_module_args args =3D {}; @@ -314,6 +344,8 @@ static void tdx_setup(u64 *cc_mask) else tdx_panic(msg); } + + enable_cpu_topology_enumeration(features0); } =20 /* diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 282497d2964b..08a9ef35d04e 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -27,15 +27,18 @@ #define TDCS_CONFIG_FLAGS 0x1110000300000016 #define TDCS_TD_CTLS 0x1110000300000017 #define TDCS_NOTIFY_ENABLES 0x9100000000000010 +#define TDCS_TOPOLOGY_ENUM_CONFIGURED 0x9100000000000019 =20 /* TDX_FEATURES0 bits */ #define TDX_FEATURES0_PENDING_EPT_VIOLATION_V2 BIT_ULL(16) +#define TDX_FEATURES0_ENUM_TOPOLOGY BIT_ULL(20) =20 /* TDCS_CONFIG_FLAGS bits */ #define TDCS_CONFIG_FLEXIBLE_PENDING_VE BIT_ULL(1) =20 /* TDCS_TD_CTLS bits */ #define TD_CTLS_PENDING_VE_DISABLE BIT_ULL(0) +#define TD_CTLS_ENUM_TOPOLOGY BIT_ULL(1) =20 /* TDX hypercall Leaf IDs */ #define TDVMCALL_MAP_GPA 0x10001 --=20 2.43.0