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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-th1520-clk-v3-5-085a18a23a7f@tenstorrent.com> References: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> In-Reply-To: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715057849; l=4110; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=52sEPjDrM2eROoC2nwe3EiBnyP8Dcq8Rt5meeISouww=; b=HmEeRhWb790IkFfO3C5BC2jB3AYXLPWOY7mhRD44oal2XW7/ZwuGHe1i92UCCZqb4bhapFIyY XN1gFmAudK9C5BUsbr5GFCWbE0xZbA90aO1ILnVV4OMXti18mT5HORG X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the clock property in TH1520 uart nodes to a clock provided by AP_SUBSYS clock controller. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-------= ---- 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index d9b4de9e4757..164afd18b56c 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -52,10 +52,6 @@ &sdhci_clk { clock-frequency =3D <198000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1365d3a512a3..1b7ede570994 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -33,10 +33,6 @@ &sdhci_clk { clock-frequency =3D <198000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index e193f8d9ab8a..963c786f3c53 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -141,12 +141,6 @@ apb_clk: apb-clk-clock { #clock-cells =3D <0>; }; =20 - uart_sclk: uart-sclk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "uart_sclk"; - #clock-cells =3D <0>; - }; - sdhci_clk: sdhci-clock { compatible =3D "fixed-clock"; clock-frequency =3D <198000000>; @@ -196,7 +190,8 @@ uart0: serial@ffe7014000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7014000 0x0 0x100>; interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -233,7 +228,8 @@ uart1: serial@ffe7f00000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f00000 0x0 0x100>; interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -243,7 +239,8 @@ uart3: serial@ffe7f04000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f04000 0x0 0x100>; interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -325,7 +322,8 @@ uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -387,7 +385,8 @@ uart4: serial@fff7f08000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xf7f08000 0x0 0x4000>; interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -397,7 +396,8 @@ uart5: serial@fff7f0c000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xf7f0c000 0x0 0x4000>; interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; --=20 2.34.1