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a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= From: Thomas Bonnefille According to the device tree coding style, nodes shall be ordered by unit address in ascending order. Signed-off-by: Thomas Bonnefille Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/thead/th1520.dtsi | 54 +++++++++++++++++--------------= ---- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 8b915e206f3a..d2fa25839012 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -193,6 +193,33 @@ uart0: serial@ffe7014000 { status =3D "disabled"; }; =20 + emmc: mmc@ffe7080000 { + compatible =3D "thead,th1520-dwcmshc"; + reg =3D <0xff 0xe7080000 0x0 0x10000>; + interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&sdhci_clk>; + clock-names =3D "core"; + status =3D "disabled"; + }; + + sdio0: mmc@ffe7090000 { + compatible =3D "thead,th1520-dwcmshc"; + reg =3D <0xff 0xe7090000 0x0 0x10000>; + interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&sdhci_clk>; + clock-names =3D "core"; + status =3D "disabled"; + }; + + sdio1: mmc@ffe70a0000 { + compatible =3D "thead,th1520-dwcmshc"; + reg =3D <0xff 0xe70a0000 0x0 0x10000>; + interrupts =3D <71 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&sdhci_clk>; + clock-names =3D "core"; + status =3D "disabled"; + }; + uart1: serial@ffe7f00000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f00000 0x0 0x100>; @@ -311,33 +338,6 @@ dmac0: dma-controller@ffefc00000 { status =3D "disabled"; }; =20 - emmc: mmc@ffe7080000 { - compatible =3D "thead,th1520-dwcmshc"; - reg =3D <0xff 0xe7080000 0x0 0x10000>; - interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&sdhci_clk>; - clock-names =3D "core"; - status =3D "disabled"; - }; - - sdio0: mmc@ffe7090000 { - compatible =3D "thead,th1520-dwcmshc"; - reg =3D <0xff 0xe7090000 0x0 0x10000>; - interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&sdhci_clk>; - clock-names =3D "core"; - status =3D "disabled"; - }; - - sdio1: mmc@ffe70a0000 { - compatible =3D "thead,th1520-dwcmshc"; - reg =3D <0xff 0xe70a0000 0x0 0x10000>; - interrupts =3D <71 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&sdhci_clk>; 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a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Document bindings for the T-Head TH1520 AP sub-system clock controller. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li Signed-off-by: Yangtao Li Signed-off-by: Drew Fustini Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/thead,th1520-clk-ap.yaml | 64 +++++++++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/thead,th1520-clk-ap.h | 96 ++++++++++++++++++= ++++ 3 files changed, 162 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.ya= ml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml new file mode 100644 index 000000000000..d7e665c1534a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AP sub-system clock controller + +description: | + The T-HEAD TH1520 AP sub-system clock controller configures the + CPU, DPU, GMAC and TEE PLLs. + + SoC reference manual + https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH15= 20%20System%20User%20Manual.pdf + +maintainers: + - Jisheng Zhang + - Wei Fu + - Drew Fustini + +properties: + compatible: + const: thead,th1520-clk-ap + + reg: + maxItems: 1 + + clocks: + items: + - description: main oscillator (24MHz) + + clock-names: + items: + - const: osc + + "#clock-cells": + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@ffef010000 { + compatible =3D "thead,th1520-clk-ap"; + reg =3D <0xff 0xef010000 0x0 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index ec0284125e8f..2b4fa9a81a01 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19014,7 +19014,9 @@ M: Guo Ren M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained +F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: arch/riscv/boot/dts/thead/ +F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-b= indings/clock/thead,th1520-clk-ap.h new file mode 100644 index 000000000000..d0d1ab1e672a --- /dev/null +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#ifndef _DT_BINDINGS_CLK_TH1520_H_ +#define _DT_BINDINGS_CLK_TH1520_H_ + +#define CLK_CPU_PLL0 0 +#define CLK_CPU_PLL1 1 +#define CLK_GMAC_PLL 2 +#define CLK_VIDEO_PLL 3 +#define CLK_DPU0_PLL 4 +#define CLK_DPU1_PLL 5 +#define CLK_TEE_PLL 6 +#define CLK_C910_I0 7 +#define CLK_C910 8 +#define CLK_BROM 9 +#define CLK_BMU 10 +#define CLK_AHB2_CPUSYS_HCLK 11 +#define CLK_APB3_CPUSYS_PCLK 12 +#define CLK_AXI4_CPUSYS2_ACLK 13 +#define CLK_AON2CPU_A2X 14 +#define CLK_X2X_CPUSYS 15 +#define CLK_AXI_ACLK 16 +#define CLK_CPU2AON_X2H 17 +#define CLK_PERI_AHB_HCLK 18 +#define CLK_CPU2PERI_X2H 19 +#define CLK_PERI_APB_PCLK 20 +#define CLK_PERI2APB_PCLK 21 +#define CLK_PERI_APB1_HCLK 22 +#define CLK_PERI_APB2_HCLK 23 +#define CLK_PERI_APB3_HCLK 24 +#define CLK_PERI_APB4_HCLK 25 +#define CLK_OSC12M 26 +#define CLK_OUT1 27 +#define CLK_OUT2 28 +#define CLK_OUT3 29 +#define CLK_OUT4 30 +#define CLK_APB_PCLK 31 +#define CLK_NPU 32 +#define CLK_NPU_AXI 33 +#define CLK_VI 34 +#define CLK_VI_AHB 35 +#define CLK_VO_AXI 36 +#define CLK_VP_APB 37 +#define CLK_VP_AXI 38 +#define CLK_CPU2VP 39 +#define CLK_VENC 40 +#define CLK_DPU0 41 +#define CLK_DPU1 42 +#define CLK_EMMC_SDIO 43 +#define CLK_GMAC1 44 +#define CLK_PADCTRL1 45 +#define CLK_DSMART 46 +#define CLK_PADCTRL0 47 +#define CLK_GMAC_AXI 48 +#define CLK_GPIO3 49 +#define CLK_GMAC0 50 +#define CLK_PWM 51 +#define CLK_QSPI0 52 +#define CLK_QSPI1 53 +#define CLK_SPI 54 +#define CLK_UART0_PCLK 55 +#define CLK_UART1_PCLK 56 +#define CLK_UART2_PCLK 57 +#define CLK_UART3_PCLK 58 +#define CLK_UART4_PCLK 59 +#define CLK_UART5_PCLK 60 +#define CLK_GPIO0 61 +#define CLK_GPIO1 62 +#define CLK_GPIO2 63 +#define CLK_I2C0 64 +#define CLK_I2C1 65 +#define CLK_I2C2 66 +#define CLK_I2C3 67 +#define CLK_I2C4 68 +#define CLK_I2C5 69 +#define CLK_SPINLOCK 70 +#define CLK_DMA 71 +#define CLK_MBOX0 72 +#define CLK_MBOX1 73 +#define CLK_MBOX2 74 +#define CLK_MBOX3 75 +#define CLK_WDT0 76 +#define CLK_WDT1 77 +#define CLK_TIMER0 78 +#define CLK_TIMER1 79 +#define CLK_SRAM0 80 +#define CLK_SRAM1 81 +#define CLK_SRAM2 82 +#define CLK_SRAM3 83 +#define CLK_PLL_GMAC_100M 84 +#define CLK_UART_SCLK 85 +#endif --=20 2.34.1 From nobody Sat Feb 7 05:57:03 2026 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 210E86BFA9 for ; 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Mon, 06 May 2024 21:57:33 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:6870:7119:e255:c3a0]) by smtp.gmail.com with ESMTPSA id o14-20020a637e4e000000b005f80aced5f3sm8987249pgn.0.2024.05.06.21.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 21:57:33 -0700 (PDT) From: Drew Fustini Date: Mon, 06 May 2024 21:55:16 -0700 Subject: [PATCH RFC v3 3/7] clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-th1520-clk-v3-3-085a18a23a7f@tenstorrent.com> References: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> In-Reply-To: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715057849; l=34261; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=oF6AgN7BW3AB3YyktiB6Cgiq6DiEL5jdZKTUcQsUcw0=; b=RRtWirsjmM4LLYeOc8W6jg8g2btDt883fCxFDWcnyDU4nKJ6elrR+cOne/wf41nTTB9a7GaMA BvXFVq8JskTDQN8YowFAKj5IZAzc046VFHabjnqaxpAQqOBkvHVCc21 X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Add support for the AP sub-system clock controller in the T-Head TH1520. This include CPU, DPU, GMAC and TEE PLLs. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li Signed-off-by: Yangtao Li Co-developed-by: Jisheng Zhang Signed-off-by: Jisheng Zhang Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/thead/Kconfig | 12 + drivers/clk/thead/Makefile | 2 + drivers/clk/thead/clk-th1520-ap.c | 1074 +++++++++++++++++++++++++++++++++= ++++ 6 files changed, 1091 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2b4fa9a81a01..d17e64eee42a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19016,6 +19016,7 @@ L: linux-riscv@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: arch/riscv/boot/dts/thead/ +F: drivers/clk/thead/clk-th1520-ap.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 RNBD BLOCK DRIVERS diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 50af5fc7f570..c9057e41df34 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -494,6 +494,7 @@ source "drivers/clk/starfive/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sunxi-ng/Kconfig" source "drivers/clk/tegra/Kconfig" +source "drivers/clk/thead/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 14fa8d4ecc1f..2eafc268f498 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -126,6 +126,7 @@ obj-y +=3D starfive/ obj-$(CONFIG_ARCH_SUNXI) +=3D sunxi/ obj-y +=3D sunxi-ng/ obj-$(CONFIG_ARCH_TEGRA) +=3D tegra/ +obj-$(CONFIG_ARCH_THEAD) +=3D thead/ obj-y +=3D ti/ obj-$(CONFIG_CLK_UNIPHIER) +=3D uniphier/ obj-$(CONFIG_ARCH_U8500) +=3D ux500/ diff --git a/drivers/clk/thead/Kconfig b/drivers/clk/thead/Kconfig new file mode 100644 index 000000000000..1710d50bf9d4 --- /dev/null +++ b/drivers/clk/thead/Kconfig @@ -0,0 +1,12 @@ +#SPDX-License-Identifier: GPL-2.0 + +config CLK_THEAD_TH1520_AP + bool "T-HEAD TH1520 AP clock support" + depends on ARCH_THEAD || COMPILE_TEST + default ARCH_THEAD + select REGMAP_MMIO + help + Say yes here to support the AP sub system clock controller + on the T-HEAD TH1520 SoC. This includes configuration of + both CPU PLLs, both DPU PLLs as well as the GMAC, VIDEO, + and TEE PLLs. diff --git a/drivers/clk/thead/Makefile b/drivers/clk/thead/Makefile new file mode 100644 index 000000000000..7ee0bec1f251 --- /dev/null +++ b/drivers/clk/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_THEAD_TH1520_AP) +=3D clk-th1520-ap.o diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c new file mode 100644 index 000000000000..2a4949013354 --- /dev/null +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -0,0 +1,1074 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#include +#include +#include +#include +#include +#include + +struct ccu_internal { + u8 shift; + u8 width; +}; + +struct ccu_div_internal { + u8 shift; + u8 width; + u32 flags; +}; + +struct ccu_common { + struct regmap *map; + u16 reg; + struct clk_hw hw; +}; + +struct ccu_mux { + struct ccu_internal mux; + struct ccu_common common; +}; + +struct ccu_gate { + u32 enable; + struct ccu_common common; +}; + +struct ccu_div { + u32 enable; + struct ccu_div_internal div; + struct ccu_internal mux; + struct ccu_common common; +}; + +/* + * struct ccu_mdiv - Definition of an M-D-I-V clock + * + * Clocks based on the formula (parent * M) / (D * I * V) + */ +struct ccu_mdiv { + struct ccu_internal m; + struct ccu_internal d; + struct ccu_internal i; + struct ccu_internal v; + struct ccu_common common; +}; + +#define TH_CCU_ARG(_shift, _width) \ + { \ + .shift =3D _shift, \ + .width =3D _width, \ + } + +#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ + { \ + .shift =3D _shift, \ + .width =3D _width, \ + .flags =3D _flags, \ + } + +#define CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ + struct ccu_gate _struct =3D { \ + .enable =3D _gate, \ + .common =3D { \ + .reg =3D _reg, \ + .hw.init =3D CLK_HW_INIT_PARENTS_DATA(_name,\ + _parent, \ + &ccu_gate_ops, \ + _flags), \ + } \ + } + +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) +{ + return container_of(hw, struct ccu_common, hw); +} + +static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mux, common); +} + +static inline struct ccu_mdiv *hw_to_ccu_mdiv(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mdiv, common); +} + +static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_div, common); +} + +static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_gate, common); +} + +static u8 ccu_get_parent_helper(struct ccu_common *common, + struct ccu_internal *mux) +{ + unsigned int val; + u8 parent; + + regmap_read(common->map, common->reg, &val); + parent =3D val >> mux->shift; + parent &=3D GENMASK(mux->width - 1, 0); + + return parent; +} + +static int ccu_set_parent_helper(struct ccu_common *common, + struct ccu_internal *mux, + u8 index) +{ + return regmap_update_bits(common->map, common->reg, + GENMASK(mux->width - 1, 0) << mux->shift, + index << mux->shift); +} + +static u8 ccu_mux_get_parent(struct clk_hw *hw) +{ + struct ccu_mux *cm =3D hw_to_ccu_mux(hw); + + return ccu_get_parent_helper(&cm->common, &cm->mux); +} + +static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_mux *cm =3D hw_to_ccu_mux(hw); + + return ccu_set_parent_helper(&cm->common, &cm->mux, index); +} + +static const struct clk_ops ccu_mux_ops =3D { + .get_parent =3D ccu_mux_get_parent, + .set_parent =3D ccu_mux_set_parent, + .determine_rate =3D __clk_mux_determine_rate, +}; + +static void ccu_disable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return; + + regmap_update_bits(common->map, common->reg, + gate, ~gate); +} + +static int ccu_enable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return 0; + + return regmap_update_bits(common->map, common->reg, + gate, gate); +} + +static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate) +{ + unsigned int val; + + if (!gate) + return true; + + regmap_read(common->map, common->reg, &val); + return val & gate; +} + +static int ccu_gate_is_enabled(struct clk_hw *hw) +{ + struct ccu_gate *cg =3D hw_to_ccu_gate(hw); + + return ccu_is_enabled_helper(&cg->common, cg->enable); +} + +static void ccu_gate_disable(struct clk_hw *hw) +{ + struct ccu_gate *cg =3D hw_to_ccu_gate(hw); + + ccu_disable_helper(&cg->common, cg->enable); +} + +static int ccu_gate_enable(struct clk_hw *hw) +{ + struct ccu_gate *cg =3D hw_to_ccu_gate(hw); + + return ccu_enable_helper(&cg->common, cg->enable); +} + +static const struct clk_ops ccu_gate_ops =3D { + .disable =3D ccu_gate_disable, + .enable =3D ccu_gate_enable, + .is_enabled =3D ccu_gate_is_enabled, +}; + +static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + unsigned int val; + + regmap_read(cd->common.map, cd->common.reg, &val); + val =3D val >> cd->div.shift; + val &=3D GENMASK(cd->div.width - 1, 0); + + val =3D divider_recalc_rate(hw, parent_rate, val, NULL, + cd->div.flags, cd->div.width); + + return val; +} + +static u8 ccu_div_get_parent(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_get_parent_helper(&cd->common, &cd->mux); +} + +static int ccu_div_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_set_parent_helper(&cd->common, &cd->mux, index); +} + +static void ccu_div_disable(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + ccu_disable_helper(&cd->common, cd->enable); +} + +static int ccu_div_enable(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_enable_helper(&cd->common, cd->enable); +} + +static int ccu_div_is_enabled(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_is_enabled_helper(&cd->common, cd->enable); +} + +static const struct clk_ops ccu_div_ops =3D { + .disable =3D ccu_div_disable, + .enable =3D ccu_div_enable, + .is_enabled =3D ccu_div_is_enabled, + .get_parent =3D ccu_div_get_parent, + .set_parent =3D ccu_div_set_parent, + .recalc_rate =3D ccu_div_recalc_rate, + .determine_rate =3D clk_hw_determine_rate_no_reparent, +}; + +static unsigned long ccu_mdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_mdiv *mdiv =3D hw_to_ccu_mdiv(hw); + unsigned long div, rate =3D parent_rate; + unsigned int m, d, i, v, val; + + regmap_read(mdiv->common.map, mdiv->common.reg, &val); + + m =3D val >> mdiv->m.shift; + m &=3D GENMASK(mdiv->m.width - 1, 0); + + d =3D val >> mdiv->d.shift; + d &=3D GENMASK(mdiv->d.width - 1, 0); + + i =3D val >> mdiv->i.shift; + i &=3D GENMASK(mdiv->i.width - 1, 0); + + v =3D val >> mdiv->v.shift; + v &=3D GENMASK(mdiv->v.width - 1, 0); + + rate =3D parent_rate * m; + div =3D d * i * v; + do_div(rate, div); + + return rate; +} + +static const struct clk_ops clk_mdiv_ops =3D { + .recalc_rate =3D ccu_mdiv_recalc_rate, +}; + +static struct ccu_mdiv cpu_pll0_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x000, + .hw.init =3D CLK_HW_INIT("cpu-pll0", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv cpu_pll1_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x010, + .hw.init =3D CLK_HW_INIT("cpu-pll1", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv gmac_pll_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x020, + .hw.init =3D CLK_HW_INIT("gmac-pll", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static const struct clk_parent_data gmac_pll_clk_parent_data[] =3D { + { .hw =3D &gmac_pll_clk.common.hw } +}; + +static struct ccu_mdiv video_pll_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x030, + .hw.init =3D CLK_HW_INIT("video-pll", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static const struct clk_parent_data video_pll_clk_parent_data[] =3D { + { .hw =3D &video_pll_clk.common.hw } +}; + +static struct ccu_mdiv dpu0_pll_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x040, + .hw.init =3D CLK_HW_INIT("dpu0-pll", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static const struct clk_parent_data dpu0_pll_clk_parent_data[] =3D { + { .hw =3D &dpu0_pll_clk.common.hw } +}; + +static struct ccu_mdiv dpu1_pll_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x050, + .hw.init =3D CLK_HW_INIT("dpu1-pll", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static const struct clk_parent_data dpu1_pll_clk_parent_data[] =3D { + { .hw =3D &dpu1_pll_clk.common.hw } +}; + +static struct ccu_mdiv tee_pll_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x060, + .hw.init =3D CLK_HW_INIT("tee-pll", "osc_24m", + &clk_mdiv_ops, + 0), + }, +}; + +static const char * const c910_i0_parents[] =3D { "cpu-pll0", "osc_24m" }; + +struct ccu_mux c910_i0_clk =3D { + .mux =3D TH_CCU_ARG(1, 1), + .common =3D { + .reg =3D 0x100, + .hw.init =3D CLK_HW_INIT_PARENTS("c910-i0", + c910_i0_parents, + &ccu_mux_ops, + 0), + } +}; + +static const struct clk_parent_data c910_parents[] =3D { + { .hw =3D &c910_i0_clk.common.hw }, + { .hw =3D &cpu_pll1_clk.common.hw } +}; + +struct ccu_mux c910_clk =3D { + .mux =3D TH_CCU_ARG(0, 1), + .common =3D { + .reg =3D 0x100, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("c910", + c910_parents, + &ccu_mux_ops, + 0), + } +}; + +static const char * const ahb2_cpusys_parents[] =3D { "gmac-pll", "osc_24m= " }; +static struct ccu_div ahb2_cpusys_hclk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .reg =3D 0x120, + .hw.init =3D CLK_HW_INIT_PARENTS("ahb2-cpusys-hclk", + ahb2_cpusys_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data ahb2_cpusys_hclk_parent_data[] =3D { + { .hw =3D &ahb2_cpusys_hclk.common.hw } +}; + +static struct ccu_div apb3_cpusys_pclk =3D { + .div =3D TH_CCU_ARG(0, 3), + .common =3D { + .reg =3D 0x130, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("apb3-cpusys-pclk", + ahb2_cpusys_hclk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data apb3_cpusys_pclk_parent_data[] =3D { + { .hw =3D &apb3_cpusys_pclk.common.hw } +}; + +static struct ccu_div axi4_cpusys2_aclk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x134, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("axi4-cpusys2-aclk", + gmac_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data axi4_cpusys2_aclk_parent_data[] =3D { + { .hw =3D &axi4_cpusys2_aclk.common.hw } +}; + +static CCU_GATE(aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_aclk_parent_d= ata, + 0x134, BIT(8), 0); + +static CCU_GATE(x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_parent_dat= a, + 0x134, BIT(7), 0); + +static CCU_GATE(brom_clk, "brom", ahb2_cpusys_hclk_parent_data, + 0x100, BIT(4), 0); + +static CCU_GATE(bmu_clk, "bmu", axi4_cpusys2_aclk_parent_data, + 0x100, BIT(5), 0); + +static const char * const axi_parents[] =3D { "video-pll", "osc_24m" }; +static struct ccu_div axi_aclk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .reg =3D 0x138, + .hw.init =3D CLK_HW_INIT_PARENTS("axi-aclk", + axi_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data axi_aclk_parent_data[] =3D { + { .hw =3D &axi_aclk.common.hw } +}; + +static CCU_GATE(cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_parent_data, + 0x138, BIT(8), 0); + +static const char * const perisys_ahb_hclk_parents[] =3D { "gmac-pll", "os= c_24m" }; +static struct ccu_div perisys_ahb_hclk =3D { + .enable =3D BIT(6), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .reg =3D 0x140, + .hw.init =3D CLK_HW_INIT_PARENTS("perisys-ahb-hclk", + perisys_ahb_hclk_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data perisys_ahb_hclk_parent_data[] =3D { + { .hw =3D &perisys_ahb_hclk.common.hw } +}; + +static CCU_GATE(cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_parent= _data, + 0x140, BIT(9), 0); + +static struct ccu_div perisys_apb_pclk =3D { + .div =3D TH_CCU_ARG(0, 3), + .common =3D { + .reg =3D 0x150, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("perisys-apb-pclk", + perisys_ahb_hclk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data perisys_apb_pclk_parent_data[] =3D { + { .hw =3D &perisys_apb_pclk.common.hw } +}; + +static struct ccu_div peri2sys_apb_pclk =3D { + .div =3D TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x150, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("peri2sys-apb-pclk", + gmac_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data peri2sys_apb_pclk_parent_data[] =3D { + { .hw =3D &peri2sys_apb_pclk.common.hw } +}; + +static CCU_GATE(perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_p= arent_data, + 0x150, BIT(9), 0); + +static CCU_GATE(perisys_apb2_hclk, "perisys-apb2-hclk", perisys_ahb_hclk_p= arent_data, + 0x150, BIT(10), 0); + +static CCU_GATE(perisys_apb3_hclk, "perisys-apb3-hclk", perisys_ahb_hclk_p= arent_data, + 0x150, BIT(11), 0); + +static CCU_GATE(perisys_apb4_hclk, "perisys-apb4-hclk", perisys_ahb_hclk_p= arent_data, + 0x150, BIT(12), 0); + +static CLK_FIXED_FACTOR_FW_NAME(osc12m_clk, "osc_12m", "osc_24m", 2, 1, 0); + +static const char * const out_parents[] =3D { "osc_24m", "osc_12m" }; + +static struct ccu_div out1_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1b4, + .hw.init =3D CLK_HW_INIT_PARENTS("out1", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out2_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1b8, + .hw.init =3D CLK_HW_INIT_PARENTS("out2", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out3_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1bc, + .hw.init =3D CLK_HW_INIT_PARENTS("out3", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out4_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1c0, + .hw.init =3D CLK_HW_INIT_PARENTS("out4", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static const char * const apb_parents[] =3D { "gmac-pll", "osc_24m" }; +static struct ccu_div apb_pclk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(7, 1), + .common =3D { + .reg =3D 0x1c4, + .hw.init =3D CLK_HW_INIT_PARENTS("apb-pclk", + apb_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data npu_parents[] =3D { + { .hw =3D &gmac_pll_clk.common.hw }, + { .hw =3D &video_pll_clk.common.hw } +}; + +static struct ccu_div npu_clk =3D { + .enable =3D BIT(4), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(6, 1), + .common =3D { + .reg =3D 0x1c8, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("npu", + npu_parents, + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(npu_axi_clk, "npu-axi", axi_aclk_parent_data, + 0x1c8, BIT(5), 0); + +static struct ccu_div vi_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1d0, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vi", + video_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vi_ahb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1d0, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vi-ahb", + video_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vo_axi_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1dc, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vo-axi", + video_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vp_apb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e0, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vp-apb", + gmac_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vp_axi_clk =3D { + .enable =3D BIT(15), + .div =3D TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e0, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("vp-axi", + video_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(cpu2vp_clk, "cpu2vp", axi_aclk_parent_data, + 0x1e0, BIT(13), 0); + +static struct ccu_div venc_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e4, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("venc", + gmac_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div dpu0_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e8, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("dpu0", + dpu0_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div dpu1_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1ec, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("dpu1", + dpu1_pll_clk_parent_data, + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(emmc_sdio_clk, "emmc-sdio", video_pll_clk_parent_data, 0x2= 04, BIT(30), 0); +static CCU_GATE(gmac1_clk, "gmac1", gmac_pll_clk_parent_data, 0x204, BIT(2= 6), 0); +static CCU_GATE(padctrl1_clk, "padctrl1", perisys_apb_pclk_parent_data, 0x= 204, BIT(24), 0); +static CCU_GATE(dsmart_clk, "dsmart", perisys_apb_pclk_parent_data, 0x204,= BIT(23), 0); +static CCU_GATE(padctrl0_clk, "padctrl0", perisys_apb_pclk_parent_data, 0x= 204, BIT(22), 0); +static CCU_GATE(gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_parent_data, 0= x204, BIT(21), 0); +static CCU_GATE(gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_parent_data, 0x2= 04, BIT(20), 0); +static CCU_GATE(gmac0_clk, "gmac0", gmac_pll_clk_parent_data, 0x204, BIT(1= 9), 0); +static CCU_GATE(pwm_clk, "pwm", perisys_apb_pclk_parent_data, 0x204, BIT(1= 8), 0); +static CCU_GATE(qspi0_clk, "qspi0", video_pll_clk_parent_data, 0x204, BIT(= 17), 0); +static CCU_GATE(qspi1_clk, "qspi1", video_pll_clk_parent_data, 0x204, BIT(= 16), 0); +static CCU_GATE(spi_clk, "spi", video_pll_clk_parent_data, 0x204, BIT(15),= 0); +static CCU_GATE(uart0_pclk, "uart0-pclk", perisys_apb_pclk_parent_data, 0x= 204, BIT(14), 0); +static CCU_GATE(uart1_pclk, "uart1-pclk", perisys_apb_pclk_parent_data, 0x= 204, BIT(13), 0); +static CCU_GATE(uart2_pclk, "uart2-pclk", perisys_apb_pclk_parent_data, 0x= 204, BIT(12), 0); +static CCU_GATE(uart3_pclk, "uart3-pclk", perisys_apb_pclk_parent_data, 0x= 204, BIT(11), 0); +static CCU_GATE(uart4_pclk, "uart4-pclk", perisys_apb_pclk_parent_data, 0x= 204, BIT(10), 0); +static CCU_GATE(uart5_pclk, "uart5-pclk", perisys_apb_pclk_parent_data, 0x= 204, BIT(9), 0); +static CCU_GATE(gpio0_clk, "gpio0-clk", perisys_apb_pclk_parent_data, 0x20= 4, BIT(8), 0); +static CCU_GATE(gpio1_clk, "gpio1-clk", perisys_apb_pclk_parent_data, 0x20= 4, BIT(7), 0); +static CCU_GATE(gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_parent_data, 0x2= 04, BIT(6), 0); +static CCU_GATE(i2c0_clk, "i2c0", perisys_apb_pclk_parent_data, 0x204, BIT= (5), 0); +static CCU_GATE(i2c1_clk, "i2c1", perisys_apb_pclk_parent_data, 0x204, BIT= (4), 0); +static CCU_GATE(i2c2_clk, "i2c2", perisys_apb_pclk_parent_data, 0x204, BIT= (3), 0); +static CCU_GATE(i2c3_clk, "i2c3", perisys_apb_pclk_parent_data, 0x204, BIT= (2), 0); +static CCU_GATE(i2c4_clk, "i2c4", perisys_apb_pclk_parent_data, 0x204, BIT= (1), 0); +static CCU_GATE(i2c5_clk, "i2c5", perisys_apb_pclk_parent_data, 0x204, BIT= (0), 0); + +static CCU_GATE(spinlock_clk, "spinlock", ahb2_cpusys_hclk_parent_data, 0x= 208, BIT(10), 0); +static CCU_GATE(dma_clk, "dma", axi4_cpusys2_aclk_parent_data, 0x208, BIT(= 8), 0); +static CCU_GATE(mbox0_clk, "mbox0", apb3_cpusys_pclk_parent_data, 0x208, B= IT(7), 0); +static CCU_GATE(mbox1_clk, "mbox1", apb3_cpusys_pclk_parent_data, 0x208, B= IT(6), 0); +static CCU_GATE(mbox2_clk, "mbox2", apb3_cpusys_pclk_parent_data, 0x208, B= IT(5), 0); +static CCU_GATE(mbox3_clk, "mbox3", apb3_cpusys_pclk_parent_data, 0x208, B= IT(4), 0); +static CCU_GATE(wdt0_clk, "wdt0", apb3_cpusys_pclk_parent_data, 0x208, BIT= (3), 0); +static CCU_GATE(wdt1_clk, "wdt1", apb3_cpusys_pclk_parent_data, 0x208, BIT= (2), 0); +static CCU_GATE(timer0_clk, "timer0", apb3_cpusys_pclk_parent_data, 0x208,= BIT(1), 0); +static CCU_GATE(timer1_clk, "timer1", apb3_cpusys_pclk_parent_data, 0x208,= BIT(0), 0); + +static CCU_GATE(sram0_clk, "sram0", axi_aclk_parent_data, 0x20c, BIT(4), 0= ); +static CCU_GATE(sram1_clk, "sram1", axi_aclk_parent_data, 0x20c, BIT(3), 0= ); +static CCU_GATE(sram2_clk, "sram2", axi_aclk_parent_data, 0x20c, BIT(2), 0= ); +static CCU_GATE(sram3_clk, "sram3", axi_aclk_parent_data, 0x20c, BIT(1), 0= ); + +static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", + &gmac_pll_clk.common.hw, + 10, 1, 0); + +static const char * const uart_sclk_parents[] =3D { "gmac-pll-clk-100m", "= osc_24m" }; +struct ccu_mux uart_sclk =3D { + .mux =3D TH_CCU_ARG(0, 1), + .common =3D { + .reg =3D 0x210, + .hw.init =3D CLK_HW_INIT_PARENTS("uart-sclk", + uart_sclk_parents, + &ccu_mux_ops, + 0), + } +}; + +static struct ccu_common *th1520_clks[] =3D { + &cpu_pll0_clk.common, + &cpu_pll1_clk.common, + &gmac_pll_clk.common, + &video_pll_clk.common, + &dpu0_pll_clk.common, + &dpu1_pll_clk.common, + &tee_pll_clk.common, + &c910_i0_clk.common, + &c910_clk.common, + &brom_clk.common, + &bmu_clk.common, + &ahb2_cpusys_hclk.common, + &apb3_cpusys_pclk.common, + &axi4_cpusys2_aclk.common, + &aon2cpu_a2x_clk.common, + &x2x_cpusys_clk.common, + &axi_aclk.common, + &cpu2aon_x2h_clk.common, + &perisys_ahb_hclk.common, + &cpu2peri_x2h_clk.common, + &perisys_apb_pclk.common, + &peri2sys_apb_pclk.common, + &perisys_apb1_hclk.common, + &perisys_apb2_hclk.common, + &perisys_apb3_hclk.common, + &perisys_apb4_hclk.common, + &out1_clk.common, + &out2_clk.common, + &out3_clk.common, + &out4_clk.common, + &apb_pclk.common, + &npu_clk.common, + &npu_axi_clk.common, + &vi_clk.common, + &vi_ahb_clk.common, + &vo_axi_clk.common, + &vp_apb_clk.common, + &vp_axi_clk.common, + &cpu2vp_clk.common, + &venc_clk.common, + &dpu0_clk.common, + &dpu1_clk.common, + &emmc_sdio_clk.common, + &gmac1_clk.common, + &padctrl1_clk.common, + &dsmart_clk.common, + &padctrl0_clk.common, + &gmac_axi_clk.common, + &gpio3_clk.common, + &gmac0_clk.common, + &pwm_clk.common, + &qspi0_clk.common, + &qspi1_clk.common, + &spi_clk.common, + &uart0_pclk.common, + &uart1_pclk.common, + &uart2_pclk.common, + &uart3_pclk.common, + &uart4_pclk.common, + &uart5_pclk.common, + &gpio0_clk.common, + &gpio1_clk.common, + &gpio2_clk.common, + &i2c0_clk.common, + &i2c1_clk.common, + &i2c2_clk.common, + &i2c3_clk.common, + &i2c4_clk.common, + &i2c5_clk.common, + &spinlock_clk.common, + &dma_clk.common, + &mbox0_clk.common, + &mbox1_clk.common, + &mbox2_clk.common, + &mbox3_clk.common, + &wdt0_clk.common, + &wdt1_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &sram0_clk.common, + &sram1_clk.common, + &sram2_clk.common, + &sram3_clk.common, + &uart_sclk.common, +}; + +#define NR_CLKS (CLK_UART_SCLK + 1) + +static struct clk_hw_onecell_data th1520_hw_clks =3D { + .hws =3D { + [CLK_OSC12M] =3D &osc12m_clk.hw, + [CLK_CPU_PLL0] =3D &cpu_pll0_clk.common.hw, + [CLK_CPU_PLL1] =3D &cpu_pll1_clk.common.hw, + [CLK_GMAC_PLL] =3D &gmac_pll_clk.common.hw, + [CLK_VIDEO_PLL] =3D &video_pll_clk.common.hw, + [CLK_DPU0_PLL] =3D &dpu0_pll_clk.common.hw, + [CLK_DPU1_PLL] =3D &dpu1_pll_clk.common.hw, + [CLK_TEE_PLL] =3D &tee_pll_clk.common.hw, + [CLK_C910_I0] =3D &c910_i0_clk.common.hw, + [CLK_C910] =3D &c910_clk.common.hw, + [CLK_BROM] =3D &brom_clk.common.hw, + [CLK_BMU] =3D &bmu_clk.common.hw, + [CLK_AHB2_CPUSYS_HCLK] =3D &ahb2_cpusys_hclk.common.hw, + [CLK_APB3_CPUSYS_PCLK] =3D &apb3_cpusys_pclk.common.hw, + [CLK_AXI4_CPUSYS2_ACLK] =3D &axi4_cpusys2_aclk.common.hw, + [CLK_AON2CPU_A2X] =3D &aon2cpu_a2x_clk.common.hw, + [CLK_X2X_CPUSYS] =3D &x2x_cpusys_clk.common.hw, + [CLK_AXI_ACLK] =3D &axi_aclk.common.hw, + [CLK_CPU2AON_X2H] =3D &cpu2aon_x2h_clk.common.hw, + [CLK_PERI_AHB_HCLK] =3D &perisys_ahb_hclk.common.hw, + [CLK_CPU2PERI_X2H] =3D &cpu2peri_x2h_clk.common.hw, + [CLK_PERI_APB_PCLK] =3D &perisys_apb_pclk.common.hw, + [CLK_PERI2APB_PCLK] =3D &peri2sys_apb_pclk.common.hw, + [CLK_PERI_APB1_HCLK] =3D &perisys_apb1_hclk.common.hw, + [CLK_PERI_APB2_HCLK] =3D &perisys_apb2_hclk.common.hw, + [CLK_PERI_APB3_HCLK] =3D &perisys_apb3_hclk.common.hw, + [CLK_PERI_APB4_HCLK] =3D &perisys_apb4_hclk.common.hw, + [CLK_OUT1] =3D &out1_clk.common.hw, + [CLK_OUT2] =3D &out2_clk.common.hw, + [CLK_OUT3] =3D &out3_clk.common.hw, + [CLK_OUT4] =3D &out4_clk.common.hw, + [CLK_APB_PCLK] =3D &apb_pclk.common.hw, + [CLK_NPU] =3D &npu_clk.common.hw, + [CLK_NPU_AXI] =3D &npu_axi_clk.common.hw, + [CLK_VI] =3D &vi_clk.common.hw, + [CLK_VI_AHB] =3D &vi_ahb_clk.common.hw, + [CLK_VO_AXI] =3D &vo_axi_clk.common.hw, + [CLK_VP_APB] =3D &vp_apb_clk.common.hw, + [CLK_VP_AXI] =3D &vp_axi_clk.common.hw, + [CLK_CPU2VP] =3D &cpu2vp_clk.common.hw, + [CLK_VENC] =3D &venc_clk.common.hw, + [CLK_DPU0] =3D &dpu0_clk.common.hw, + [CLK_DPU1] =3D &dpu1_clk.common.hw, + [CLK_EMMC_SDIO] =3D &emmc_sdio_clk.common.hw, + [CLK_GMAC1] =3D &gmac1_clk.common.hw, + [CLK_PADCTRL1] =3D &padctrl1_clk.common.hw, + [CLK_DSMART] =3D &dsmart_clk.common.hw, + [CLK_PADCTRL0] =3D &padctrl0_clk.common.hw, + [CLK_GMAC_AXI] =3D &gmac_axi_clk.common.hw, + [CLK_GPIO3] =3D &gpio3_clk.common.hw, + [CLK_GMAC0] =3D &gmac0_clk.common.hw, + [CLK_PWM] =3D &pwm_clk.common.hw, + [CLK_QSPI0] =3D &qspi0_clk.common.hw, + [CLK_QSPI1] =3D &qspi1_clk.common.hw, + [CLK_SPI] =3D &spi_clk.common.hw, + [CLK_UART0_PCLK] =3D &uart0_pclk.common.hw, + [CLK_UART1_PCLK] =3D &uart1_pclk.common.hw, + [CLK_UART2_PCLK] =3D &uart2_pclk.common.hw, + [CLK_UART3_PCLK] =3D &uart3_pclk.common.hw, + [CLK_UART4_PCLK] =3D &uart4_pclk.common.hw, + [CLK_UART5_PCLK] =3D &uart5_pclk.common.hw, + [CLK_GPIO0] =3D &gpio0_clk.common.hw, + [CLK_GPIO1] =3D &gpio1_clk.common.hw, + [CLK_GPIO2] =3D &gpio2_clk.common.hw, + [CLK_I2C0] =3D &i2c0_clk.common.hw, + [CLK_I2C1] =3D &i2c1_clk.common.hw, + [CLK_I2C2] =3D &i2c2_clk.common.hw, + [CLK_I2C3] =3D &i2c3_clk.common.hw, + [CLK_I2C4] =3D &i2c4_clk.common.hw, + [CLK_I2C5] =3D &i2c5_clk.common.hw, + [CLK_SPINLOCK] =3D &spinlock_clk.common.hw, + [CLK_DMA] =3D &dma_clk.common.hw, + [CLK_MBOX0] =3D &mbox0_clk.common.hw, + [CLK_MBOX1] =3D &mbox1_clk.common.hw, + [CLK_MBOX2] =3D &mbox2_clk.common.hw, + [CLK_MBOX3] =3D &mbox3_clk.common.hw, + [CLK_WDT0] =3D &wdt0_clk.common.hw, + [CLK_WDT1] =3D &wdt1_clk.common.hw, + [CLK_TIMER0] =3D &timer0_clk.common.hw, + [CLK_TIMER1] =3D &timer1_clk.common.hw, + [CLK_SRAM0] =3D &sram0_clk.common.hw, + [CLK_SRAM1] =3D &sram1_clk.common.hw, + [CLK_SRAM2] =3D &sram2_clk.common.hw, + [CLK_SRAM3] =3D &sram3_clk.common.hw, + [CLK_PLL_GMAC_100M] =3D &gmac_pll_clk_100m.hw, + [CLK_UART_SCLK] =3D &uart_sclk.common.hw, + }, + .num =3D NR_CLKS, +}; + +static const struct regmap_config th1520_clk_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .fast_io =3D true, +}; + +static int th1520_clk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *map; + void __iomem *regs; + int ret, i; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + map =3D devm_regmap_init_mmio(dev, regs, &th1520_clk_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + for (i =3D 0; i < ARRAY_SIZE(th1520_clks); i++) + th1520_clks[i]->map =3D map; + + for (i =3D 0; i < th1520_hw_clks.num; i++) { + ret =3D devm_clk_hw_register(dev, th1520_hw_clks.hws[i]); + if (ret) + return ret; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &th1520_hw_clks); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id th1520_clk_match[] =3D { + { + .compatible =3D "thead,th1520-clk-ap", + }, + { /* sentinel */ }, +}; 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Mon, 06 May 2024 21:57:34 -0700 (PDT) From: Drew Fustini Date: Mon, 06 May 2024 21:55:17 -0700 Subject: [PATCH RFC v3 4/7] riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-th1520-clk-v3-4-085a18a23a7f@tenstorrent.com> References: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> In-Reply-To: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715057849; l=1160; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=6PV2bpf3dXOpJag32DfU7y2Gi0ru2guu8y2sRZs5RmA=; b=4exMVJ4xzbDXC65KXMLDO8sJeX/DSsbUp2hf1w0Dv6pU91zrS6Osgwql3mmUi6my0DL13QSh7 VXf/l+EKB0oDAgK0QRc6WSqWYrnUbsMoyXBAkkUFB+hNy9WFwuZt+Y5 X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Add node for the AP_SUBSYS clock controller on the T-Head TH1520 SoC. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index d2fa25839012..e193f8d9ab8a 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -5,6 +5,7 @@ */ =20 #include +#include =20 / { compatible =3D "thead,th1520"; @@ -161,6 +162,14 @@ soc { dma-noncoherent; ranges; =20 + clk: clock-controller@ffef010000 { + compatible =3D "thead,th1520-clk-ap"; + reg =3D <0xff 0xef010000 0x0 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + }; + plic: interrupt-controller@ffd8000000 { compatible =3D "thead,th1520-plic", "thead,c900-plic"; reg =3D <0xff 0xd8000000 0x0 0x01000000>; --=20 2.34.1 From nobody Sat Feb 7 05:57:03 2026 Received: from mail-yw1-f169.google.com (mail-yw1-f169.google.com [209.85.128.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12BD56E61B for ; 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Mon, 06 May 2024 21:57:35 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:6870:7119:e255:c3a0]) by smtp.gmail.com with ESMTPSA id o14-20020a637e4e000000b005f80aced5f3sm8987249pgn.0.2024.05.06.21.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 21:57:35 -0700 (PDT) From: Drew Fustini Date: Mon, 06 May 2024 21:55:18 -0700 Subject: [PATCH RFC v3 5/7] riscv: dts: thead: change TH1520 uart nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-th1520-clk-v3-5-085a18a23a7f@tenstorrent.com> References: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> In-Reply-To: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715057849; l=4110; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=52sEPjDrM2eROoC2nwe3EiBnyP8Dcq8Rt5meeISouww=; b=HmEeRhWb790IkFfO3C5BC2jB3AYXLPWOY7mhRD44oal2XW7/ZwuGHe1i92UCCZqb4bhapFIyY XN1gFmAudK9C5BUsbr5GFCWbE0xZbA90aO1ILnVV4OMXti18mT5HORG X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the clock property in TH1520 uart nodes to a clock provided by AP_SUBSYS clock controller. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-------= ---- 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index d9b4de9e4757..164afd18b56c 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -52,10 +52,6 @@ &sdhci_clk { clock-frequency =3D <198000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1365d3a512a3..1b7ede570994 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -33,10 +33,6 @@ &sdhci_clk { clock-frequency =3D <198000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index e193f8d9ab8a..963c786f3c53 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -141,12 +141,6 @@ apb_clk: apb-clk-clock { #clock-cells =3D <0>; }; =20 - uart_sclk: uart-sclk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "uart_sclk"; - #clock-cells =3D <0>; - }; - sdhci_clk: sdhci-clock { compatible =3D "fixed-clock"; clock-frequency =3D <198000000>; @@ -196,7 +190,8 @@ uart0: serial@ffe7014000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7014000 0x0 0x100>; interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -233,7 +228,8 @@ uart1: serial@ffe7f00000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f00000 0x0 0x100>; interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -243,7 +239,8 @@ uart3: serial@ffe7f04000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f04000 0x0 0x100>; interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -325,7 +322,8 @@ uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -387,7 +385,8 @@ uart4: serial@fff7f08000 { compatible =3D "snps,dw-apb-uart"; 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Mon, 06 May 2024 21:57:36 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:6870:7119:e255:c3a0]) by smtp.gmail.com with ESMTPSA id o14-20020a637e4e000000b005f80aced5f3sm8987249pgn.0.2024.05.06.21.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 21:57:36 -0700 (PDT) From: Drew Fustini Date: Mon, 06 May 2024 21:55:19 -0700 Subject: [PATCH RFC v3 6/7] riscv: dts: thead: change TH1520 mmc nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-th1520-clk-v3-6-085a18a23a7f@tenstorrent.com> References: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> In-Reply-To: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715057849; l=2852; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=OUFR3qpXcXj7TePvrKOEf7IaTgZBtQzS5Gcb0JSxYYc=; b=iNarSOopWZV22F1WTSuygcpwGBUXFmpXfraZzMxIY0BKPrRyPthQNT34GelMdfKFz4c4M4PLj e+PrCy1ghpfDUt8tgw2ezv2sWsYMcU8xsnYX8yVasA66jKVcOZZeh0f X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the clock property in the TH1520 mmc controller nodes to a clock provided by AP_SYS clock controller. Remove sdhci fixed clock reference from BeagleV Ahead and LPI4a dts. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 13 +++---------- 3 files changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 164afd18b56c..55f1ed0cb433 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -48,10 +48,6 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 -&sdhci_clk { - clock-frequency =3D <198000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1b7ede570994..762eceb415f8 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,10 +29,6 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 -&sdhci_clk { - clock-frequency =3D <198000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 963c786f3c53..cf2141c3976f 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -141,13 +141,6 @@ apb_clk: apb-clk-clock { #clock-cells =3D <0>; }; =20 - sdhci_clk: sdhci-clock { - compatible =3D "fixed-clock"; - clock-frequency =3D <198000000>; - clock-output-names =3D "sdhci_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -201,7 +194,7 @@ emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&sdhci_clk>; + clocks =3D <&clk CLK_EMMC_SDIO>; clock-names =3D "core"; status =3D "disabled"; }; @@ -210,7 +203,7 @@ sdio0: mmc@ffe7090000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7090000 0x0 0x10000>; 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Mon, 06 May 2024 21:57:37 -0700 (PDT) From: Drew Fustini Date: Mon, 06 May 2024 21:55:20 -0700 Subject: [PATCH RFC v3 7/7] riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-th1520-clk-v3-7-085a18a23a7f@tenstorrent.com> References: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> In-Reply-To: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715057849; l=4851; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=uoSZcE5Xsilp2h5kGfeS4a/3IqaGYxAdmgKgnxrBUNU=; b=BifQO2sCcHe9fBTRk7kaehpgYjaAujHk0VCVti7HuFvmS4vxrzgImnYMt0/hjY1s2xpIUoVAI 3VNZYMYtEGwCH+FsfP6I8l3tUiDWT1Vg/QZawgOwqZNahnDphwqvTET X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the dma-controller and timer nodes to use the APB clock provided by the AP_SUBSYS clock controller. Remove apb_clk reference from BeagleV Ahead and LPI4a dts. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++----------= ---- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 55f1ed0cb433..1180e41c7b07 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,10 +44,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 762eceb415f8..78977bdbbe3d 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,10 +25,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index cf2141c3976f..34bd58b45baa 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -135,12 +135,6 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 - apb_clk: apb-clk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "apb_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -326,7 +320,7 @@ dmac0: dma-controller@ffefc00000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0xff 0xefc00000 0x0 0x1000>; interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&apb_clk>, <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; dma-channels =3D <4>; @@ -341,7 +335,7 @@ dmac0: dma-controller@ffefc00000 { timer0: timer@ffefc32000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -350,7 +344,7 @@ timer0: timer@ffefc32000 { timer1: timer@ffefc32014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -359,7 +353,7 @@ timer1: timer@ffefc32014 { timer2: timer@ffefc32028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -368,7 +362,7 @@ timer2: timer@ffefc32028 { timer3: timer@ffefc3203c { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc3203c 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -399,7 +393,7 @@ uart5: serial@fff7f0c000 { timer4: timer@ffffc33000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -408,7 +402,7 @@ timer4: timer@ffffc33000 { timer5: timer@ffffc33014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -417,7 +411,7 @@ timer5: timer@ffffc33014 { timer6: timer@ffffc33028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -426,7 +420,7 @@ timer6: timer@ffffc33028 { timer7: timer@ffffc3303c { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc3303c 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; --=20 2.34.1