From nobody Thu Sep 19 23:11:47 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B60C7F476 for ; Mon, 6 May 2024 13:36:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715002582; cv=none; b=DxDXULyDbWzcG01TCFBplLWadVrYdtdSkLbmwL3PX3aTjy5PJEDurGwTErLe0Iu6PRBRYWQAUDvVETkhep6CdM0rc29yTDQZY1rLZNCs+GLf+QV1BWYB202654jvLojtR+uKcLA8SYlw9iun9Rr+RiKGHIiCc30T+i/gzsWdTgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715002582; c=relaxed/simple; bh=MJDOXWqTjpbjsQTnGrv4MfUIC0eogdPWXfz9qOdcOCA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OXJ/V5N+APgo5B2Ltm7XOEZACBctmjaHEU8nEyij3AG+NKOZu9mOxccS6tcbGYGB2DCoV1/levnIWFufQQ3zUJyaeAgvuLy1WqnNUqSl+7aSdo1J8XzMDU8tmD22fKJCrWp/oyNhtvUSWCxfCV2LsBlWAm+OQtzlxR6+++MtrPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K1lVik91; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K1lVik91" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 466E6C3277B; Mon, 6 May 2024 13:36:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715002581; bh=MJDOXWqTjpbjsQTnGrv4MfUIC0eogdPWXfz9qOdcOCA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=K1lVik91lKB3BsVDt1TF6+YiO2iiiAcRRDupmDnuWDqXPQ8Od8Umgmb4EtrUlopDN TsljnH30VDHb9P+oXMK37QRBqO5oRv6/iX8acZo2y6Yj1ilVudcgi2/5dhVKB6zuU1 8p28dpI+vQ1zLpqoQlNQvyptH0Di2CH2ZoyZcDbhk2ZnQ0bdp3AgZBWM+CE927F1+E g3Pz48GTKs6FSdKTWpCdxE9cHzcI4mKi7htABfoi1FWHs4RFYma2htWtzGeGhx/ztz y+g8VuQy5lKed4jXxjd1GUueDfwtuHIn8ERKlXRwtJfHgN27jbkcAqzRaKGXO13TAr 05eXigYD3g/ng== From: Michael Walle Date: Mon, 06 May 2024 15:34:45 +0200 Subject: [PATCH 16/20] drm/bridge: tc358775: use proper defines to configure LVDS timings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-tc358775-fix-powerup-v1-16-545dcf00b8dd@kernel.org> References: <20240506-tc358775-fix-powerup-v1-0-545dcf00b8dd@kernel.org> In-Reply-To: <20240506-tc358775-fix-powerup-v1-0-545dcf00b8dd@kernel.org> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Sam Ravnborg , Vinay Simha BN , Tony Lindgren Cc: Daniel Semkowicz , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Michael Walle X-Mailer: b4 0.12.4 Provide bitfield macros for the individual fields in the LVDS timing registers and get rid of the magic values. Signed-off-by: Michael Walle --- drivers/gpu/drm/bridge/tc358775.c | 52 +++++++++++++++++++++++++----------= ---- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc3= 58775.c index 33a97ddba7b5..c50554ec4b28 100644 --- a/drivers/gpu/drm/bridge/tc358775.c +++ b/drivers/gpu/drm/bridge/tc358775.c @@ -111,11 +111,19 @@ #define VPCTRL_OPXLFMT BIT(8) #define VPCTRL_EVTMODE BIT(5) /* Video event mode enable, tc35876x only */ #define HTIM1 0x0454 /* Horizontal Timing Control 1 */ +#define HTIM1_HPW GENMASK(8, 0) +#define HTIM1_HBPR GENMASK(24, 16) #define HTIM2 0x0458 /* Horizontal Timing Control 2 */ +#define HTIM2_HACT GENMASK(10, 0) +#define HTIM2_HFPR GENMASK(24, 16) #define VTIM1 0x045C /* Vertical Timing Control 1 */ +#define VTIM1_VPW GENMASK(7, 0) +#define VTIM1_VBPR GENMASK(23, 16) #define VTIM2 0x0460 /* Vertical Timing Control 2 */ +#define VTIM2_VACT GENMASK(10, 0) +#define VTIM2_VFPR GENMASK(23, 16) #define VFUEN 0x0464 /* Video Frame Timing Update Enable */ -#define VFUEN_EN BIT(0) /* Upload Enable */ +#define VFUEN_VFUEN BIT(0) /* Upload Enable */ =20 /* Mux Input Select for LVDS LINK Input */ #define LV_MX0003 0x0480 /* Bit 0 to 3 */ @@ -346,24 +354,19 @@ static void tc358775_configure_dsi(struct tc_data *tc= , unsigned int pixelclk) static void tc358775_configure_lvds_timings(struct tc_data *tc, struct drm_display_mode *mode) { - u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2; - u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2; + u32 hback_porch, hsync_len, hfront_porch, hactive; + u32 vback_porch, vsync_len, vfront_porch, vactive; + unsigned int val; =20 hback_porch =3D mode->htotal - mode->hsync_end; hsync_len =3D mode->hsync_end - mode->hsync_start; + hactive =3D mode->hdisplay; + hfront_porch =3D mode->hsync_start - mode->hdisplay; + vback_porch =3D mode->vtotal - mode->vsync_end; vsync_len =3D mode->vsync_end - mode->vsync_start; - - htime1 =3D (hback_porch << 16) + hsync_len; - vtime1 =3D (vback_porch << 16) + vsync_len; - - hfront_porch =3D mode->hsync_start - mode->hdisplay; - hactive =3D mode->hdisplay; - vfront_porch =3D mode->vsync_start - mode->vdisplay; vactive =3D mode->vdisplay; - - htime2 =3D (hfront_porch << 16) + hactive; - vtime2 =3D (vfront_porch << 16) + vactive; + vfront_porch =3D mode->vsync_start - mode->vdisplay; =20 /* Video event mode vs pulse mode bit, does not exist for tc358775 */ if (tc->type =3D=3D TC358765) @@ -379,12 +382,23 @@ static void tc358775_configure_lvds_timings(struct tc= _data *tc, regmap_update_bits(tc->regmap, VPCTRL, val, VPCTRL_OPXLFMT | VPCTRL_MSF | VPCTRL_EVTMODE); =20 - regmap_write(tc->regmap, HTIM1, htime1); - regmap_write(tc->regmap, VTIM1, vtime1); - regmap_write(tc->regmap, HTIM2, htime2); - regmap_write(tc->regmap, VTIM2, vtime2); + val =3D u32_encode_bits(hsync_len, HTIM1_HPW); + val |=3D u32_encode_bits(hback_porch, HTIM1_HBPR); + regmap_write(tc->regmap, HTIM1, val); + + val =3D u32_encode_bits(hactive, HTIM2_HACT); + val |=3D u32_encode_bits(hfront_porch, HTIM2_HFPR); + regmap_write(tc->regmap, HTIM2, val); + + val =3D u32_encode_bits(vsync_len, VTIM1_VPW); + val |=3D u32_encode_bits(vback_porch, VTIM1_VBPR); + regmap_write(tc->regmap, VTIM1, val); + + val =3D u32_encode_bits(vactive, VTIM2_VACT); + val |=3D u32_encode_bits(vfront_porch, VTIM2_VFPR); + regmap_write(tc->regmap, VTIM2, val); =20 - regmap_write(tc->regmap, VFUEN, VFUEN_EN); + regmap_write(tc->regmap, VFUEN, VFUEN_VFUEN); } =20 static const struct tc358775_pll_settings tc358775_pll_settings[] =3D { @@ -475,7 +489,7 @@ static void tc358775_bridge_enable(struct drm_bridge *b= ridge) tc358775_configure_lvds_timings(tc, mode); tc358775_configure_pll(tc, mode->crtc_clock); tc358775_configure_color_mapping(tc, connector->display_info.bus_formats[= 0]); - regmap_write(tc->regmap, VFUEN, VFUEN_EN); + regmap_write(tc->regmap, VFUEN, VFUEN_VFUEN); tc358775_configure_lvds_clock(tc); =20 /* Finally, enable the LVDS transmitter */ --=20 2.39.2