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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-rk-dts-additions-v4-1-271023ddfd40@gmail.com> References: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> In-Reply-To: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714988224; l=4796; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=+CRjCu5/qMbviqrE7tKv0CDQlxSHs+JH5lEn/bmXM3Y=; b=EzL8gJdaHg+A1S3Q8nrUlNLWmEKSCa0G7Sxga0J9K3BPOvz6Ld9L11TR3dmiltGPq92SM/bLY N9PjqYnNTheAGDY2BCBsg8YbcF95OobZ1LadcHzT2Pj+MPWM0QHIerj X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= This includes the necessary device tree data to allow thermal monitoring on RK3588(s) using the on-chip TSADC device, along with trip points for automatic thermal management. Each of the CPU clusters (one for the little cores and two for the big cores) get a passive cooling trip point at 85C, which will trigger DVFS throttling of the respective cluster upon reaching a high temperature condition. All zones also have a critical trip point at 115C, which will trigger a reset. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 147 ++++++++++++++++++++++++++= ++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 6ac5ac8b48ab..ef06c1f742e8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include =20 / { compatible =3D "rockchip,rk3588"; @@ -2368,6 +2369,152 @@ pwm15: pwm@febf0030 { status =3D "disabled"; }; =20 + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 1>; + + trips { + bigcore0_alert: bigcore0-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + bigcore0_crit: bigcore0-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&bigcore0_alert>; + cooling-device =3D + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 2>; + + trips { + bigcore2_alert: bigcore2-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + bigcore2_crit: bigcore2-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&bigcore2_alert>; + cooling-device =3D + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 3>; + + trips { + littlecore_alert: littlecore-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + littlecore_crit: littlecore-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&littlecore_alert>; + cooling-device =3D + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 5>; + + trips { + gpu_crit: gpu-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + tsadc: tsadc@fec00000 { compatible =3D "rockchip,rk3588-tsadc"; reg =3D <0x0 0xfec00000 0x0 0x400>; --=20 2.45.0 From nobody Wed Dec 17 17:25:02 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA281142E7D; Mon, 6 May 2024 09:37:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 06 May 2024 02:37:16 -0700 (PDT) Received: from [172.30.32.119] ([2001:8f8:183b:f2c::d35]) by smtp.gmail.com with ESMTPSA id f6-20020a056402160600b005722ce89ae2sm4983647edv.38.2024.05.06.02.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 02:37:15 -0700 (PDT) From: Alexey Charkov Date: Mon, 06 May 2024 13:36:33 +0400 Subject: [PATCH v4 2/6] arm64: dts: rockchip: enable thermal management on all RK3588 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-rk-dts-additions-v4-2-271023ddfd40@gmail.com> References: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> In-Reply-To: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714988224; l=4390; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=lraF8Hbej6o/vzD2ibMl+sD1o6QIvu8qx6CUPylhTS0=; b=L+SmgqiZUWX1QlD1lAl8Fvx6rg3te0i8Dfivs/4C85qKwq5x8IqH2l/yBUMfv+hG0SscnqBb5 /rqtiXXtC+xCIsVzjy5l4iHbWTkC4rlKbTBgxQjs9K1pcoxUz13N3BS X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= This enables the on-chip thermal monitoring sensor (TSADC) on all RK3588(s) boards that don't have it enabled yet. It provides temperature monitoring for the SoC and emergency thermal shutdowns, and is thus important to have in place before CPU DVFS is enabled, as high CPU operating performance points can overheat the chip quickly in the absence of thermal management. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++ 8 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/ar= m64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 98c622b27647..c667704ba985 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -673,6 +673,10 @@ regulator-state-mem { }; }; =20 +&tsadc { + status =3D "okay"; +}; + &u2phy0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi = b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index 709d348cf06b..03fd193be253 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -466,3 +466,7 @@ regulator-state-mem { }; }; }; + +&tsadc { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts index 7be2190244ba..7c3696a3ad3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -1131,6 +1131,10 @@ &sata0 { status =3D "okay"; }; =20 +&tsadc { + status =3D "okay"; +}; + &u2phy0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/= boot/dts/rockchip/rk3588-ok3588-c.dts index 009566d881f3..230e630820b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -376,6 +376,10 @@ &sdmmc { status =3D "okay"; }; =20 +&tsadc { + status =3D "okay"; +}; + &u2phy2 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index b8e15b76a8a6..21e96c212dd8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -742,6 +742,10 @@ regulator-state-mem { }; }; =20 +&tsadc { + status =3D "okay"; +}; + &uart2 { pinctrl-0 =3D <&uart2m0_xfer>; status =3D "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts b/arch/arm= 64/boot/dts/rockchip/rk3588-toybrick-x0.dts index 9090c5c99f2a..d0021524e7f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts @@ -648,6 +648,10 @@ regulator-state-mem { }; }; =20 +&tsadc { + status =3D "okay"; +}; + &u2phy2 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6b9206ce4a03..77bcf0f6b028 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -601,6 +601,10 @@ regulator-state-mem { }; }; =20 +&tsadc { + status =3D "okay"; +}; + &uart2 { pinctrl-0 =3D <&uart2m0_xfer>; status =3D "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/= boot/dts/rockchip/rk3588s-rock-5a.dts index 8e2a07612d17..c671a61d3aef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -697,6 +697,10 @@ regulator-state-mem { }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-rk-dts-additions-v4-3-271023ddfd40@gmail.com> References: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> In-Reply-To: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714988224; l=1255; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=QMB2BQUFw504Si0nPhgwd4U1cGB1jsKPa2V0a7oyVXA=; b=kOJ0Ccq6KM+zlPF5AmBsuM09NjiaXHs7BkcQ43+BtvNRKJFT8LEz+ydboCdWRkGjp1pcFJNgq YfaX5AKGTxsAeKGf08Q0SYC6Lt+B7TVrNrDrlkoUuC7CKxfBqCVafZX X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= As the GPU support on RK3588 has been merged upstream, along with OPP values, add a corresponding cooling map for passive cooling using the GPU. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index ef06c1f742e8..57c2d998ae75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2487,17 +2487,29 @@ center_crit: center-crit { }; =20 gpu_thermal: gpu-thermal { - polling-delay-passive =3D <0>; + polling-delay-passive =3D <100>; polling-delay =3D <0>; thermal-sensors =3D <&tsadc 5>; =20 trips { + gpu_alert: gpu-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; gpu_crit: gpu-crit { temperature =3D <115000>; hysteresis =3D <0>; type =3D "critical"; }; }; + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 npu_thermal: npu-thermal { --=20 2.45.0 From nobody Wed Dec 17 17:25:02 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0911D143874; 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Mon, 06 May 2024 02:37:23 -0700 (PDT) Received: from [172.30.32.119] ([2001:8f8:183b:f2c::d35]) by smtp.gmail.com with ESMTPSA id f6-20020a056402160600b005722ce89ae2sm4983647edv.38.2024.05.06.02.37.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 02:37:22 -0700 (PDT) From: Alexey Charkov Date: Mon, 06 May 2024 13:36:35 +0400 Subject: [PATCH v4 4/6] arm64: dts: rockchip: enable automatic fan control on Rock 5B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-rk-dts-additions-v4-4-271023ddfd40@gmail.com> References: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> In-Reply-To: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714988224; l=1732; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=M2euxf6Q8SBg4Hukc8wh3jha9LlUxWfNoH85/fD9b74=; b=MahjJ0I2pQJ4AW3JzNQC9fccwUyhos/l9FLjyPDexr0mdVocKlMIJIoQ564q3b6hHPkFvMV06 d43aMKeL9/xCskjRFLK+lSYGdbjw526FpglZ7y4rHmfArWI/C/9Otwf X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= This links the PWM fan on Radxa Rock 5B as an active cooling device managed automatically by the thermal subsystem, with a target SoC temperature of 65C and a minimum-spin interval from 55C to 65C to ensure airflow when the system gets warm Helped-by: Dragan Simic Reviewed-by: Dragan Simic Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 30 +++++++++++++++++++++= +++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 21e96c212dd8..b70313643af8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -52,7 +52,7 @@ led_rgb_b { =20 fan: pwm-fan { compatible =3D "pwm-fan"; - cooling-levels =3D <0 95 145 195 255>; + cooling-levels =3D <0 120 150 180 210 240 255>; fan-supply =3D <&vcc5v0_sys>; pwms =3D <&pwm1 0 50000 0>; #cooling-cells =3D <2>; @@ -279,6 +279,34 @@ i2s0_8ch_p0_0: endpoint { }; }; =20 +&package_thermal { + polling-delay =3D <1000>; + + trips { + package_fan0: package-fan0 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + package_fan1: package-fan1 { + temperature =3D <65000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map1 { + trip =3D <&package_fan0>; + cooling-device =3D <&fan THERMAL_NO_LIMIT 1>; + }; + map2 { + trip =3D <&package_fan1>; + cooling-device =3D <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie2_0_rst>; --=20 2.45.0 From nobody Wed Dec 17 17:25:02 2025 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A785143892; 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Mon, 06 May 2024 02:37:26 -0700 (PDT) Received: from [172.30.32.119] ([2001:8f8:183b:f2c::d35]) by smtp.gmail.com with ESMTPSA id f6-20020a056402160600b005722ce89ae2sm4983647edv.38.2024.05.06.02.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 02:37:26 -0700 (PDT) From: Alexey Charkov Date: Mon, 06 May 2024 13:36:36 +0400 Subject: [PATCH v4 5/6] arm64: dts: rockchip: Add CPU/memory regulator coupling for RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-rk-dts-additions-v4-5-271023ddfd40@gmail.com> References: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> In-Reply-To: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714988224; l=5927; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=hRIkjs6ilNO5CkTYJyMd31t+JYZiL+ZsbuuDrU+GbqI=; b=XVssbaVtYFgNJD/XqYSrTYailN5Ixj2qPGOg//g6Locd7JznRCRUL/ireurFFFp18tnJlooDf tXw2RHepzHuAmunHqLkS8cBfLNJvwfiLch3E3gsH6QRKwVokgZS+b30 X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= RK3588 chips allow for their CPU cores to be powered by a different supply vs. their corresponding memory interfaces, and two of the boards currently upstream do that (EVB1 and QuartzPro64). The voltage of the memory interface though has to match that of the CPU cores that use it, which downstream kernels achieve by the means of a custom cpufreq driver which adjusts both at the same time. It seems that regulator coupling is a more appropriate generic interface for it, so this patch introduces coupling to affected device trees to ensure that memory interface voltage is also updated whenever cpufreq switches between CPU OPPs. Note that other boards, such as Radxa Rock 5B, define both the CPU and memory interface regulators as aliases to the same DT node, so this doesn't apply there. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts index 7c3696a3ad3a..00f660d50127 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -878,6 +878,8 @@ regulators { vdd_cpu_big1_s0: dcdc-reg1 { regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -890,6 +892,8 @@ regulator-state-mem { vdd_cpu_big0_s0: dcdc-reg2 { regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -902,6 +906,8 @@ regulator-state-mem { vdd_cpu_lit_s0: dcdc-reg3 { regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <950000>; regulator-ramp-delay =3D <12500>; @@ -926,6 +932,8 @@ regulator-state-mem { vdd_cpu_big1_mem_s0: dcdc-reg5 { regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -939,6 +947,8 @@ regulator-state-mem { vdd_cpu_big0_mem_s0: dcdc-reg6 { regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -963,6 +973,8 @@ regulator-state-mem { vdd_cpu_lit_mem_s0: dcdc-reg8 { regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <950000>; regulator-ramp-delay =3D <12500>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm= 64/boot/dts/rockchip/rk3588-quartzpro64.dts index b4f22d95ac0e..baeb08d665c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -832,6 +832,8 @@ vdd_cpu_big1_s0: dcdc-reg1 { regulator-name =3D "vdd_cpu_big1_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big1_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -845,6 +847,8 @@ vdd_cpu_big0_s0: dcdc-reg2 { regulator-name =3D "vdd_cpu_big0_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big0_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -858,6 +862,8 @@ vdd_cpu_lit_s0: dcdc-reg3 { regulator-name =3D "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_lit_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <950000>; regulator-ramp-delay =3D <12500>; @@ -884,6 +890,8 @@ vdd_cpu_big1_mem_s0: dcdc-reg5 { regulator-name =3D "vdd_cpu_big1_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big1_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -898,6 +906,8 @@ vdd_cpu_big0_mem_s0: dcdc-reg6 { regulator-name =3D "vdd_cpu_big0_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_big0_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <1050000>; regulator-ramp-delay =3D <12500>; @@ -924,6 +934,8 @@ vdd_cpu_lit_mem_s0: dcdc-reg8 { regulator-name =3D "vdd_cpu_lit_mem_s0"; regulator-always-on; regulator-boot-on; + regulator-coupled-with =3D <&vdd_cpu_lit_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <950000>; regulator-ramp-delay =3D <12500>; --=20 2.45.0 From nobody Wed Dec 17 17:25:02 2025 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EB03143C4E; Mon, 6 May 2024 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; 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Mon, 06 May 2024 02:37:30 -0700 (PDT) Received: from [172.30.32.119] ([2001:8f8:183b:f2c::d35]) by smtp.gmail.com with ESMTPSA id f6-20020a056402160600b005722ce89ae2sm4983647edv.38.2024.05.06.02.37.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 02:37:29 -0700 (PDT) From: Alexey Charkov Date: Mon, 06 May 2024 13:36:37 +0400 Subject: [PATCH v4 6/6] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240506-rk-dts-additions-v4-6-271023ddfd40@gmail.com> References: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> In-Reply-To: <20240506-rk-dts-additions-v4-0-271023ddfd40@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , Chen-Yu Tsai , Diederik de Haas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714988225; l=7420; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=u0gM6tgf6YzJQvPrv4bbdJjzpHgMPBoZnVPNA5o69i0=; b=NfzFHVbPxKtMkrjMx7ITPK0l9dIz6TK3LMlotIOo6u548b6Xuf0R6hhxasx1fOlIhVYKEcYv/ J0vR7Nvg0SADzl2KsFF5wijg/ZINprMkziy6RTlh00QO7fHZLtRxYeE X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= By default the CPUs on RK3588 start up in a conservative performance mode. Add frequency and voltage mappings to the device tree to enable dynamic scaling via cpufreq. OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], stripping them down to the minimum frequency and voltage combinations as expected by the generic upstream cpufreq-dt driver, and also dropping those OPPs that don't differ in voltage but only in frequency (keeping the top frequency OPP in each case). Note that this patch ignores voltage scaling for the CPU memory interface which the downstream kernel does through a custom cpufreq driver, and which is why the downstream version has two sets of voltage values for each OPP (the second one being meant for the memory interface supply regulator). This is done instead via regulator coupling between CPU and memory interface supplies on affected boards. This has been tested on Rock 5B with u-boot 2023.11 compiled from Collabora's integration tree [2] with binary bl31 and appears to be stable both under active cooling and passive cooling (with throttling) [1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/= dts/rockchip/rk3588s.dtsi [2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++++++++++++++++++= ++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 57c2d998ae75..85c25d5efdad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -97,6 +97,7 @@ cpu_l0: cpu@0 { clocks =3D <&scmi_clk SCMI_CLK_CPUL>; assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUL>; assigned-clock-rates =3D <816000000>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -116,6 +117,7 @@ cpu_l1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -135,6 +137,7 @@ cpu_l2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -154,6 +157,7 @@ cpu_l3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -175,6 +179,7 @@ cpu_b0: cpu@400 { clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; assigned-clock-rates =3D <816000000>; + operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -194,6 +199,7 @@ cpu_b1: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -215,6 +221,7 @@ cpu_b2: cpu@600 { clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; assigned-clock-rates =3D <816000000>; + operating-points-v2 =3D <&cluster2_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -234,6 +241,7 @@ cpu_b3: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 =3D <&cluster2_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -348,6 +356,120 @@ l3_cache: l3-cache { }; }; =20 + cluster0_opp_table: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <675000 675000 950000>; + clock-latency-ns =3D <40000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <712500 712500 950000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <762500 762500 950000>; + clock-latency-ns =3D <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <850000 850000 950000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <950000 950000 950000>; + clock-latency-ns =3D <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <725000 725000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <762500 762500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <850000 850000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <925000 925000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-microvolt =3D <987500 987500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <725000 725000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <762500 762500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <850000 850000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <925000 925000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-microvolt =3D <987500 987500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + }; + display_subsystem: display-subsystem { compatible =3D "rockchip,display-subsystem"; ports =3D <&vop_out>; --=20 2.45.0