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Acked-by: Conor Dooley Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..5c9014087c17 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 =20 + - description: i.MX95 based Boards + items: + - enum: + - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: --=20 2.37.1 From nobody Sun Feb 8 17:12:53 2026 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2048.outbound.protection.outlook.com [40.107.20.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E8F31798F; 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This patch is to add a minimal dtsi, with cpu cores, coresight, scmi, gic, uart, mu, sdhc, lpi2c added. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95-clock.h | 187 +++++ arch/arm64/boot/dts/freescale/imx95-power.h | 55 ++ arch/arm64/boot/dts/freescale/imx95.dtsi | 1049 +++++++++++++++++++++++= ++++ 3 files changed, 1291 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/= dts/freescale/imx95-clock.h new file mode 100644 index 000000000000..5badaace3148 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __CLOCK_IMX95_H +#define __CLOCK_IMX95_H + +/* The index should match i.MX95 SCMI Firmware */ +#define IMX95_CLK_32K 1 +#define IMX95_CLK_24M 2 +#define IMX95_CLK_FRO 3 +#define IMX95_CLK_SYSPLL1_VCO 4 +#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX95_CLK_SYSPLL1_PFD0 6 +#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX95_CLK_SYSPLL1_PFD1 9 +#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX95_CLK_SYSPLL1_PFD2 12 +#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX95_CLK_AUDIOPLL1_VCO 14 +#define IMX95_CLK_AUDIOPLL1 15 +#define IMX95_CLK_AUDIOPLL2_VCO 16 +#define IMX95_CLK_AUDIOPLL2 17 +#define IMX95_CLK_VIDEOPLL1_VCO 18 +#define IMX95_CLK_VIDEOPLL1 19 +#define IMX95_CLK_RESERVED20 20 +#define IMX95_CLK_RESERVED21 21 +#define IMX95_CLK_RESERVED22 22 +#define IMX95_CLK_RESERVED23 23 +#define IMX95_CLK_ARMPLL_VCO 24 +#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX95_CLK_ARMPLL_PFD0 26 +#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX95_CLK_ARMPLL_PFD1 28 +#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX95_CLK_ARMPLL_PFD2 30 +#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX95_CLK_ARMPLL_PFD3 32 +#define IMX95_CLK_DRAMPLL_VCO 33 +#define IMX95_CLK_DRAMPLL 34 +#define IMX95_CLK_HSIOPLL_VCO 35 +#define IMX95_CLK_HSIOPLL 36 +#define IMX95_CLK_LDBPLL_VCO 37 +#define IMX95_CLK_LDBPLL 38 +#define IMX95_CLK_EXT1 39 +#define IMX95_CLK_EXT2 40 + +#define IMX95_CCM_NUM_CLK_SRC 41 + +#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0) +#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1) +#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2) +#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3) +#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4) +#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5) +#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6) +#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7) +#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8) +#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9) +#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10) +#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11) +#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12) +#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13) +#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14) +#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15) +#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16) +#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17) +#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18) +#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19) +#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20) +#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21) +#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22) +#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23) +#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24) +#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25) +#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26) +#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27) +#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28) +#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29) +#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30) +#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31) +#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32) +#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33) +#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34) +#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35) +#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36) +#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37) +#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38) +#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39) +#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40) +#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41) +#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42) +#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43) +#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44) +#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45) +#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46) +#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47) +#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48) +#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49) +#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50) +#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51) +#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52) +#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53) +#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54) +#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55) +#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56) +#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57) +#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58) +#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59) +#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60) +#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61) +#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62) +#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63) +#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64) +#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65) +#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66) +#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67) +#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68) +#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69) +#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70) +#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71) +#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72) +#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73) +#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74) +#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75) +#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76) +#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77) +#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78) +#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79) +#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80) +#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81) +#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82) +#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83) +#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84) +#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85) +#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86) +#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87) +#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88) +#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89) +#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90) +#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91) +#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92) +#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93) +#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94) +#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95) +#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96) +#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97) +#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98) +#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99) +#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100) +#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101) +#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102) +#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103) +#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104) +#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105) +#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106) +#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107) +#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108) +#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109) +#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110) +#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111) +#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112) +#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113) +#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114) +#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115) +#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116) +#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117) +#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118) +#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119) +#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120) +#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121) +#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122) +#define IMX95_CLK_SEL_EXT (IMX95_CCM_NUM_CLK_SRC + 123 + = 0) +#define IMX95_CLK_SEL_A55C0 (IMX95_CCM_NUM_CLK_SRC + 123 + = 1) +#define IMX95_CLK_SEL_A55C1 (IMX95_CCM_NUM_CLK_SRC + 123 + = 2) +#define IMX95_CLK_SEL_A55C2 (IMX95_CCM_NUM_CLK_SRC + 123 + = 3) +#define IMX95_CLK_SEL_A55C3 (IMX95_CCM_NUM_CLK_SRC + 123 + = 4) +#define IMX95_CLK_SEL_A55C4 (IMX95_CCM_NUM_CLK_SRC + 123 + = 5) +#define IMX95_CLK_SEL_A55C5 (IMX95_CCM_NUM_CLK_SRC + 123 + = 6) +#define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + = 7) +#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + = 8) +#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + = 9) + +#endif /* __DT_BINDINGS_CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-power.h b/arch/arm64/boot/= dts/freescale/imx95-power.h new file mode 100644 index 000000000000..a43779317fed --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-power.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __IMX95_POWER_H__ +#define __IMX95_POWER_H__ + +#define IMX95_PD_ANA 0 +#define IMX95_PD_AON 1 +#define IMX95_PD_BBSM 2 +#define IMX95_PD_CAMERA 3 +#define IMX95_PD_CCMSRCGPC 4 +#define IMX95_PD_A55C0 5 +#define IMX95_PD_A55C1 6 +#define IMX95_PD_A55C2 7 +#define IMX95_PD_A55C3 8 +#define IMX95_PD_A55C4 9 +#define IMX95_PD_A55C5 10 +#define IMX95_PD_A55P 11 +#define IMX95_PD_DDR 12 +#define IMX95_PD_DISPLAY 13 +#define IMX95_PD_GPU 14 +#define IMX95_PD_HSIO_TOP 15 +#define IMX95_PD_HSIO_WAON 16 +#define IMX95_PD_M7 17 +#define IMX95_PD_NETC 18 +#define IMX95_PD_NOC 19 +#define IMX95_PD_NPU 20 +#define IMX95_PD_VPU 21 +#define IMX95_PD_WAKEUP 22 + +#define IMX95_PERF_ELE 0 +#define IMX95_PERF_M33 1 +#define IMX95_PERF_WAKEUP 2 +#define IMX95_PERF_M7 3 +#define IMX95_PERF_DRAM 4 +#define IMX95_PERF_HSIO 5 +#define IMX95_PERF_NPU 6 +#define IMX95_PERF_NOC 7 +#define IMX95_PERF_A55 8 +#define IMX95_PERF_GPU 9 +#define IMX95_PERF_VPU 10 +#define IMX95_PERF_CAM 11 +#define IMX95_PERF_DISP 12 +#define IMX95_PERF_A55PER 13 +#define IMX95_PERF_A55P 14 +#define IMX95_PERF_A55C0 15 +#define IMX95_PERF_A55C1 16 +#define IMX95_PERF_A55C2 17 +#define IMX95_PERF_A55C3 18 +#define IMX95_PERF_A55C4 19 +#define IMX95_PERF_A55C5 20 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi new file mode 100644 index 000000000000..eeb995c39481 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -0,0 +1,1049 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include + +#include "imx95-clock.h" +#include "imx95-power.h" + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + idle-states { + entry-method =3D "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x0010033>; + local-timer-stop; + entry-latency-us =3D <10000>; + exit-latency-us =3D <7000>; + min-residency-us =3D <27000>; + wakeup-latency-us =3D <15000>; + status =3D "disabled"; + }; + }; + + A55_0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + cpu-idle-states =3D <&cpu_pd_wait>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + cpu-idle-states =3D <&cpu_pd_wait>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + cpu-idle-states =3D <&cpu_pd_wait>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l3>; + }; + + A55_4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + cpu-idle-states =3D <&cpu_pd_wait>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l4>; + }; + + A55_5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + cpu-idle-states =3D <&cpu_pd_wait>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l5>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l4: l2-cache-l4 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l5: l2-cache-l5 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&A55_0>; + }; + + core1 { + cpu =3D <&A55_1>; + }; + + core2 { + cpu =3D <&A55_2>; + }; + + core3 { + cpu =3D <&A55_3>; + }; + + core4 { + cpu =3D <&A55_4>; + }; + + core5 { + cpu =3D <&A55_5>; + }; + }; + }; + }; + + clk_ext1: clock-ext1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <133000000>; + clock-output-names =3D "clk_ext1"; + }; + + sai1_mclk: sai-mclk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai1_mclk"; + }; + + sai2_mclk: sai-mclk2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai2_mclk"; + }; + + sai3_mclk: sai-mclk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai3_mclk"; + }; + + sai4_mclk: sai-mclk4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai4_mclk"; + }; + + sai5_mclk: sai-mclk5 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai5_mclk"; + }; + + osc_24m: osc-24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc_24m"; + }; + + sram1: sram@20480000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x204c0000 0x0 0x18000>; + ranges =3D <0x0 0x0 0x204c0000 0x18000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + firmware { + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; + shmem =3D <&scmi_buf0>, <&scmi_buf1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_devpd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi_perf: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + + scmi_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + }; + }; + + pmu { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + thermal-zones { + a55-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&scmi_sensor 1>; + + trips { + cpu_alert0: trip0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_crit0: trip1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_alert0>; + cooling-device =3D + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <24000000>; + arm,no-tick-in-suspend; + interrupt-parent =3D <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + interrupt-parent =3D <&gic>; + dma-noncoherent; + ranges; + + its: msi-controller@48040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + dma-noncoherent; + }; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aips2: bus@42000000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0x0 0x42000000 0x0 0x800000>; + ranges =3D <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mu7: mailbox@42430000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x42430000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + wdog3: watchdog@42490000 { + compatible =3D "fsl,imx93-wdt"; + reg =3D <0x42490000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + timeout-sec =3D <40>; + status =3D "disabled"; + }; + + tpm3: pwm@424e0000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x424e0000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x424f0000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM4>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm5: pwm@42500000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x42500000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM5>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm6: pwm@42510000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x42510000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM6>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x42530000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x42540000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42550000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42560000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpuart3: serial@42570000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42570000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART3>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart4: serial@42580000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42580000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART4>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart5: serial@42590000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42590000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART5>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x425a0000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART6>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart7: serial@42690000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42690000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART7>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x426a0000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART8>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426b0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426c0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426d0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426e0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x426f0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42700000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42710000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42720000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + mu8: mailbox@42730000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x42730000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0 0x42800000 0 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x42800000 0x0 0x42800000 0x800000>; + + usdhc1: mmc@42850000 { + compatible =3D "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg =3D <0x42850000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC1>; + clock-names =3D "ipg", "ahb", "per"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_USDHC1>; + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <8>; + fsl,tuning-start-tap =3D <1>; + fsl,tuning-step=3D <2>; + status =3D "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible =3D "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg =3D <0x42860000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC2>; + clock-names =3D "ipg", "ahb", "per"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_USDHC2>; + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <4>; + fsl,tuning-start-tap =3D <1>; + fsl,tuning-step=3D <2>; + status =3D "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible =3D "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg =3D <0x428b0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC3>; + clock-names =3D "ipg", "ahb", "per"; + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <4>; + fsl,tuning-start-tap =3D <1>; + fsl,tuning-step=3D <2>; + status =3D "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + }; + + gpio3: gpio@43820000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + }; + + gpio4: gpio@43840000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + }; + + gpio5: gpio@43850000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + }; + + aips1: bus@44000000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0x0 0x44000000 0x0 0x800000>; + ranges =3D <0x44000000 0x0 0x44000000 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mu1: mailbox@44220000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x44220000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + tpm1: pwm@44310000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x44310000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm2: pwm@44320000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x44320000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM2>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x44340000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x44350000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x44360000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x44370000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpuart1: serial@44380000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x44380000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART1>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart2: serial@44390000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x44390000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART2>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + adc1: adc@44530000 { + compatible =3D "nxp,imx93-adc"; + reg =3D <0x44530000 0x10000>; + interrupts =3D , + , + ; + clocks =3D <&scmi_clk IMX95_CLK_ADC>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x445b0000 0x1000>; + ranges; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + #mbox-cells =3D <2>; + + sram0: sram@445b1000 { + compatible =3D "mmio-sram"; + reg =3D <0x445b1000 0x400>; + ranges =3D <0x0 0x445b1000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x445d0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x445f0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + mu6: mailbox@44630000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x44630000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + }; + + mailbox@47320000 { + compatible =3D "fsl,imx95-mu-v2x"; + reg =3D <0x0 0x47320000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + + mailbox@47350000 { + compatible =3D "fsl,imx95-mu-v2x"; + reg =3D <0x0 0x47350000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_M33>, + <&scmi_clk IMX95_CLK_M33>; + clock-names =3D "gpio", "port"; + status =3D "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47520000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47530000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47540000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47550000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + + elemu4: mailbox@47560000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47560000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47570000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + aips4: bus@49000000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0x0 0x49000000 0x0 0x800000>; + ranges =3D <0x49000000 0x0 0x49000000 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + smmu: iommu@490d0000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x490d0000 0x100000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells =3D <1>; + status =3D "disabled"; + }; + }; + }; +}; --=20 2.37.1 From nobody Sun Feb 8 17:12:53 2026 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2048.outbound.protection.outlook.com [40.107.20.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3707DF5B; Fri, 3 May 2024 01:29:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c3ed73c8-b16b-4758-5c98-08dc6b107dc1 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 01:29:35.4113 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tHPCXpzOGgi2BITlbgO2DqU7H66rQarsn6de+DwbusBhhbBUY0L85XDKjKYCvYkdjMontXyVGPKx82OKlyh+Lw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10275 From: Peng Fan Add a minimal dts for i.MX95 19x19 EVK board: - lpuart1 as console - sdhc1/2 as storage As of now, because scmi pinctrl support not ready, so count on bootloader to set the pinctrl. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 112 ++++++++++++++++++= ++++ 2 files changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index bd443c2bc5a4..057e23fde780 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -236,6 +236,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk.dtb =20 imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64= /boot/dts/freescale/imx95-19x19-evk.dts new file mode 100644 index 000000000000..7e7271b0c545 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include "imx95.dtsi" + +/ { + model =3D "NXP i.MX95 19X19 board"; + compatible =3D "fsl,imx95-19x19-evk", "fsl,imx95"; + + aliases { + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + gpio4 =3D &gpio5; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + i2c3 =3D &lpi2c4; + i2c4 =3D &lpi2c5; + i2c5 =3D &lpi2c6; + i2c6 =3D &lpi2c7; + i2c7 =3D &lpi2c8; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + mmc2 =3D &usdhc3; + serial0 =3D &lpuart1; + serial1 =3D &lpuart2; + serial2 =3D &lpuart3; + serial3 =3D &lpuart4; + serial4 =3D &lpuart5; + serial5 =3D &lpuart6; + serial6 =3D &lpuart7; + serial7 =3D &lpuart8; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux_cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x7F000000>; + size =3D <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; +}; + +&lpuart1 { + /* console */ + status =3D "okay"; +}; + +&mu7 { + status =3D "okay"; +}; + +&usdhc1 { + bus-width =3D <8>; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&usdhc2 { + non-removable; + bus-width =3D <4>; + status =3D "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status =3D "okay"; +}; --=20 2.37.1